LLVM 22.0.0git
AArch64InstPrinter.cpp
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1//==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This class prints an AArch64 MCInst to a .s file.
10//
11//===----------------------------------------------------------------------===//
12
13#include "AArch64InstPrinter.h"
14#include "MCTargetDesc/AArch64AddressingModes.h"
15#include "Utils/AArch64BaseInfo.h"
16#include "llvm/ADT/StringExtras.h"
17#include "llvm/ADT/StringRef.h"
18#include "llvm/MC/MCAsmInfo.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCRegisterInfo.h"
22#include "llvm/MC/MCSubtargetInfo.h"
23#include "llvm/Support/Casting.h"
24#include "llvm/Support/ErrorHandling.h"
25#include "llvm/Support/Format.h"
26#include "llvm/Support/MathExtras.h"
27#include "llvm/Support/raw_ostream.h"
28#include <cassert>
29#include <cstdint>
30#include <string>
31
32using namespace llvm;
33
34#define DEBUG_TYPE "asm-printer"
35
36#define GET_INSTRUCTION_NAME
37#define PRINT_ALIAS_INSTR
38#include "AArch64GenAsmWriter.inc"
39#define GET_INSTRUCTION_NAME
40#define PRINT_ALIAS_INSTR
41#include "AArch64GenAsmWriter1.inc"
42
47
52
53bool AArch64InstPrinter::applyTargetSpecificCLOption(StringRef Opt) {
54 if (Opt == "no-aliases") {
55 PrintAliases = false;
56 return true;
57 }
58 return false;
59}
60
64
65void AArch64InstPrinter::printRegName(raw_ostream &OS, MCRegister Reg,
66 unsigned AltIdx) {
67 markup(OS, Markup::Register) << getRegisterName(Reg, AltIdx);
68}
69
73
74void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
75 StringRef Annot, const MCSubtargetInfo &STI,
76 raw_ostream &O) {
77 // Check for special encodings and print the canonical alias instead.
78
79 unsigned Opcode = MI->getOpcode();
80
81 if (Opcode == AArch64::SYSxt)
82 if (printSysAlias(MI, STI, O)) {
83 printAnnotation(O, Annot);
84 return;
85 }
86
87 if (Opcode == AArch64::SYSPxt || Opcode == AArch64::SYSPxt_XZR)
88 if (printSyspAlias(MI, STI, O)) {
89 printAnnotation(O, Annot);
90 return;
91 }
92
93 // RPRFM overlaps PRFM (reg), so try to print it as RPRFM here.
94 if ((Opcode == AArch64::PRFMroX) || (Opcode == AArch64::PRFMroW)) {
95 if (printRangePrefetchAlias(MI, STI, O, Annot))
96 return;
97 }
98
99 // SBFM/UBFM should print to a nicer aliased form if possible.
100 if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri ||
101 Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) {
102 const MCOperand &Op0 = MI->getOperand(0);
103 const MCOperand &Op1 = MI->getOperand(1);
104 const MCOperand &Op2 = MI->getOperand(2);
105 const MCOperand &Op3 = MI->getOperand(3);
106
107 bool IsSigned = (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri);
108 bool Is64Bit = (Opcode == AArch64::SBFMXri || Opcode == AArch64::UBFMXri);
109 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) {
110 const char *AsmMnemonic = nullptr;
111
112 switch (Op3.getImm()) {
113 default:
114 break;
115 case 7:
116 if (IsSigned)
117 AsmMnemonic = "sxtb";
118 else if (!Is64Bit)
119 AsmMnemonic = "uxtb";
120 break;
121 case 15:
122 if (IsSigned)
123 AsmMnemonic = "sxth";
124 else if (!Is64Bit)
125 AsmMnemonic = "uxth";
126 break;
127 case 31:
128 // *xtw is only valid for signed 64-bit operations.
129 if (Is64Bit && IsSigned)
130 AsmMnemonic = "sxtw";
131 break;
132 }
133
134 if (AsmMnemonic) {
135 O << '\t' << AsmMnemonic << '\t';
136 printRegName(O, Op0.getReg());
137 O << ", ";
138 printRegName(O, getWRegFromXReg(Op1.getReg()));
139 printAnnotation(O, Annot);
140 return;
141 }
142 }
143
144 // All immediate shifts are aliases, implemented using the Bitfield
145 // instruction. In all cases the immediate shift amount shift must be in
146 // the range 0 to (reg.size -1).
147 if (Op2.isImm() && Op3.isImm()) {
148 const char *AsmMnemonic = nullptr;
149 int shift = 0;
150 int64_t immr = Op2.getImm();
151 int64_t imms = Op3.getImm();
152 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
153 AsmMnemonic = "lsl";
154 shift = 31 - imms;
155 } else if (Opcode == AArch64::UBFMXri && imms != 0x3f &&
156 ((imms + 1 == immr))) {
157 AsmMnemonic = "lsl";
158 shift = 63 - imms;
159 } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) {
160 AsmMnemonic = "lsr";
161 shift = immr;
162 } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) {
163 AsmMnemonic = "lsr";
164 shift = immr;
165 } else if (Opcode == AArch64::SBFMWri && imms == 0x1f) {
166 AsmMnemonic = "asr";
167 shift = immr;
168 } else if (Opcode == AArch64::SBFMXri && imms == 0x3f) {
169 AsmMnemonic = "asr";
170 shift = immr;
171 }
172 if (AsmMnemonic) {
173 O << '\t' << AsmMnemonic << '\t';
174 printRegName(O, Op0.getReg());
175 O << ", ";
176 printRegName(O, Op1.getReg());
177 O << ", ";
178 markup(O, Markup::Immediate) << "#" << shift;
179 printAnnotation(O, Annot);
180 return;
181 }
182 }
183
184 // SBFIZ/UBFIZ aliases
185 if (Op2.getImm() > Op3.getImm()) {
186 O << '\t' << (IsSigned ? "sbfiz" : "ubfiz") << '\t';
187 printRegName(O, Op0.getReg());
188 O << ", ";
189 printRegName(O, Op1.getReg());
190 O << ", ";
191 markup(O, Markup::Immediate) << "#" << (Is64Bit ? 64 : 32) - Op2.getImm();
192 O << ", ";
193 markup(O, Markup::Immediate) << "#" << Op3.getImm() + 1;
194 printAnnotation(O, Annot);
195 return;
196 }
197
198 // Otherwise SBFX/UBFX is the preferred form
199 O << '\t' << (IsSigned ? "sbfx" : "ubfx") << '\t';
200 printRegName(O, Op0.getReg());
201 O << ", ";
202 printRegName(O, Op1.getReg());
203 O << ", ";
204 markup(O, Markup::Immediate) << "#" << Op2.getImm();
205 O << ", ";
206 markup(O, Markup::Immediate) << "#" << Op3.getImm() - Op2.getImm() + 1;
207 printAnnotation(O, Annot);
208 return;
209 }
210
211 if (Opcode == AArch64::BFMXri || Opcode == AArch64::BFMWri) {
212 const MCOperand &Op0 = MI->getOperand(0); // Op1 == Op0
213 const MCOperand &Op2 = MI->getOperand(2);
214 int ImmR = MI->getOperand(3).getImm();
215 int ImmS = MI->getOperand(4).getImm();
216
217 if ((Op2.getReg() == AArch64::WZR || Op2.getReg() == AArch64::XZR) &&
218 (ImmR == 0 || ImmS < ImmR) && STI.hasFeature(AArch64::HasV8_2aOps)) {
219 // BFC takes precedence over its entire range, slightly differently to BFI.
220 int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32;
221 int LSB = (BitWidth - ImmR) % BitWidth;
222 int Width = ImmS + 1;
223
224 O << "\tbfc\t";
225 printRegName(O, Op0.getReg());
226 O << ", ";
227 markup(O, Markup::Immediate) << "#" << LSB;
228 O << ", ";
229 markup(O, Markup::Immediate) << "#" << Width;
230 printAnnotation(O, Annot);
231 return;
232 } else if (ImmS < ImmR) {
233 // BFI alias
234 int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32;
235 int LSB = (BitWidth - ImmR) % BitWidth;
236 int Width = ImmS + 1;
237
238 O << "\tbfi\t";
239 printRegName(O, Op0.getReg());
240 O << ", ";
241 printRegName(O, Op2.getReg());
242 O << ", ";
243 markup(O, Markup::Immediate) << "#" << LSB;
244 O << ", ";
245 markup(O, Markup::Immediate) << "#" << Width;
246 printAnnotation(O, Annot);
247 return;
248 }
249
250 int LSB = ImmR;
251 int Width = ImmS - ImmR + 1;
252 // Otherwise BFXIL the preferred form
253 O << "\tbfxil\t";
254 printRegName(O, Op0.getReg());
255 O << ", ";
256 printRegName(O, Op2.getReg());
257 O << ", ";
258 markup(O, Markup::Immediate) << "#" << LSB;
259 O << ", ";
260 markup(O, Markup::Immediate) << "#" << Width;
261 printAnnotation(O, Annot);
262 return;
263 }
264
265 // Symbolic operands for MOVZ, MOVN and MOVK already imply a shift
266 // (e.g. :gottprel_g1: is always going to be "lsl #16") so it should not be
267 // printed.
268 if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi ||
269 Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) &&
270 MI->getOperand(1).isExpr()) {
271 if (Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi)
272 O << "\tmovz\t";
273 else
274 O << "\tmovn\t";
275
276 printRegName(O, MI->getOperand(0).getReg());
277 O << ", ";
278 {
279 WithMarkup M = markup(O, Markup::Immediate);
280 O << "#";
281 MAI.printExpr(O, *MI->getOperand(1).getExpr());
282 }
283 return;
284 }
285
286 if ((Opcode == AArch64::MOVKXi || Opcode == AArch64::MOVKWi) &&
287 MI->getOperand(2).isExpr()) {
288 O << "\tmovk\t";
289 printRegName(O, MI->getOperand(0).getReg());
290 O << ", ";
291 {
292 WithMarkup M = markup(O, Markup::Immediate);
293 O << "#";
294 MAI.printExpr(O, *MI->getOperand(2).getExpr());
295 }
296 return;
297 }
298
299 auto PrintMovImm = [&](uint64_t Value, int RegWidth) {
300 int64_t SExtVal = SignExtend64(Value, RegWidth);
301 O << "\tmov\t";
302 printRegName(O, MI->getOperand(0).getReg());
303 O << ", ";
304 markup(O, Markup::Immediate) << "#" << formatImm(SExtVal);
305 if (CommentStream) {
306 // Do the opposite to that used for instruction operands.
307 if (getPrintImmHex())
308 *CommentStream << '=' << formatDec(SExtVal) << '\n';
309 else {
310 uint64_t Mask = maskTrailingOnes<uint64_t>(RegWidth);
311 *CommentStream << '=' << formatHex(SExtVal & Mask) << '\n';
312 }
313 }
314 };
315
316 // MOVZ, MOVN and "ORR wzr, #imm" instructions are aliases for MOV, but their
317 // domains overlap so they need to be prioritized. The chain is "MOVZ lsl #0 >
318 // MOVZ lsl #N > MOVN lsl #0 > MOVN lsl #N > ORR". The highest instruction
319 // that can represent the move is the MOV alias, and the rest get printed
320 // normally.
321 if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi) &&
322 MI->getOperand(1).isImm() && MI->getOperand(2).isImm()) {
323 int RegWidth = Opcode == AArch64::MOVZXi ? 64 : 32;
324 int Shift = MI->getOperand(2).getImm();
325 uint64_t Value = (uint64_t)MI->getOperand(1).getImm() << Shift;
326
327 if (AArch64_AM::isMOVZMovAlias(Value, Shift,
328 Opcode == AArch64::MOVZXi ? 64 : 32)) {
329 PrintMovImm(Value, RegWidth);
330 return;
331 }
332 }
333
334 if ((Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) &&
335 MI->getOperand(1).isImm() && MI->getOperand(2).isImm()) {
336 int RegWidth = Opcode == AArch64::MOVNXi ? 64 : 32;
337 int Shift = MI->getOperand(2).getImm();
338 uint64_t Value = ~((uint64_t)MI->getOperand(1).getImm() << Shift);
339 if (RegWidth == 32)
340 Value = Value & 0xffffffff;
341
342 if (AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth)) {
343 PrintMovImm(Value, RegWidth);
344 return;
345 }
346 }
347
348 if ((Opcode == AArch64::ORRXri || Opcode == AArch64::ORRWri) &&
349 (MI->getOperand(1).getReg() == AArch64::XZR ||
350 MI->getOperand(1).getReg() == AArch64::WZR) &&
351 MI->getOperand(2).isImm()) {
352 int RegWidth = Opcode == AArch64::ORRXri ? 64 : 32;
353 uint64_t Value = AArch64_AM::decodeLogicalImmediate(
354 MI->getOperand(2).getImm(), RegWidth);
355 if (!AArch64_AM::isAnyMOVWMovAlias(Value, RegWidth)) {
356 PrintMovImm(Value, RegWidth);
357 return;
358 }
359 }
360
361 if (Opcode == AArch64::SPACE) {
362 O << '\t' << MAI.getCommentString() << " SPACE "
363 << MI->getOperand(1).getImm();
364 printAnnotation(O, Annot);
365 return;
366 }
367
368 if (!PrintAliases || !printAliasInstr(MI, Address, STI, O))
369 printInstruction(MI, Address, STI, O);
370
371 printAnnotation(O, Annot);
372
373 if (atomicBarrierDroppedOnZero(Opcode) &&
374 (MI->getOperand(0).getReg() == AArch64::XZR ||
375 MI->getOperand(0).getReg() == AArch64::WZR)) {
376 printAnnotation(O, "acquire semantics dropped since destination is zero");
377 }
378}
379
380static bool isTblTbxInstruction(unsigned Opcode, StringRef &Layout,
381 bool &IsTbx) {
382 switch (Opcode) {
383 case AArch64::TBXv8i8One:
384 case AArch64::TBXv8i8Two:
385 case AArch64::TBXv8i8Three:
386 case AArch64::TBXv8i8Four:
387 IsTbx = true;
388 Layout = ".8b";
389 return true;
390 case AArch64::TBLv8i8One:
391 case AArch64::TBLv8i8Two:
392 case AArch64::TBLv8i8Three:
393 case AArch64::TBLv8i8Four:
394 IsTbx = false;
395 Layout = ".8b";
396 return true;
397 case AArch64::TBXv16i8One:
398 case AArch64::TBXv16i8Two:
399 case AArch64::TBXv16i8Three:
400 case AArch64::TBXv16i8Four:
401 IsTbx = true;
402 Layout = ".16b";
403 return true;
404 case AArch64::TBLv16i8One:
405 case AArch64::TBLv16i8Two:
406 case AArch64::TBLv16i8Three:
407 case AArch64::TBLv16i8Four:
408 IsTbx = false;
409 Layout = ".16b";
410 return true;
411 default:
412 return false;
413 }
414}
415
416struct LdStNInstrDesc {
417 unsigned Opcode;
418 const char *Mnemonic;
419 const char *Layout;
420 int ListOperand;
421 bool HasLane;
422 int NaturalOffset;
423};
424
425static const LdStNInstrDesc LdStNInstInfo[] = {
426 { AArch64::LD1i8, "ld1", ".b", 1, true, 0 },
427 { AArch64::LD1i16, "ld1", ".h", 1, true, 0 },
428 { AArch64::LD1i32, "ld1", ".s", 1, true, 0 },
429 { AArch64::LD1i64, "ld1", ".d", 1, true, 0 },
430 { AArch64::LD1i8_POST, "ld1", ".b", 2, true, 1 },
431 { AArch64::LD1i16_POST, "ld1", ".h", 2, true, 2 },
432 { AArch64::LD1i32_POST, "ld1", ".s", 2, true, 4 },
433 { AArch64::LD1i64_POST, "ld1", ".d", 2, true, 8 },
434 { AArch64::LD1Rv16b, "ld1r", ".16b", 0, false, 0 },
435 { AArch64::LD1Rv8h, "ld1r", ".8h", 0, false, 0 },
436 { AArch64::LD1Rv4s, "ld1r", ".4s", 0, false, 0 },
437 { AArch64::LD1Rv2d, "ld1r", ".2d", 0, false, 0 },
438 { AArch64::LD1Rv8b, "ld1r", ".8b", 0, false, 0 },
439 { AArch64::LD1Rv4h, "ld1r", ".4h", 0, false, 0 },
440 { AArch64::LD1Rv2s, "ld1r", ".2s", 0, false, 0 },
441 { AArch64::LD1Rv1d, "ld1r", ".1d", 0, false, 0 },
442 { AArch64::LD1Rv16b_POST, "ld1r", ".16b", 1, false, 1 },
443 { AArch64::LD1Rv8h_POST, "ld1r", ".8h", 1, false, 2 },
444 { AArch64::LD1Rv4s_POST, "ld1r", ".4s", 1, false, 4 },
445 { AArch64::LD1Rv2d_POST, "ld1r", ".2d", 1, false, 8 },
446 { AArch64::LD1Rv8b_POST, "ld1r", ".8b", 1, false, 1 },
447 { AArch64::LD1Rv4h_POST, "ld1r", ".4h", 1, false, 2 },
448 { AArch64::LD1Rv2s_POST, "ld1r", ".2s", 1, false, 4 },
449 { AArch64::LD1Rv1d_POST, "ld1r", ".1d", 1, false, 8 },
450 { AArch64::LD1Onev16b, "ld1", ".16b", 0, false, 0 },
451 { AArch64::LD1Onev8h, "ld1", ".8h", 0, false, 0 },
452 { AArch64::LD1Onev4s, "ld1", ".4s", 0, false, 0 },
453 { AArch64::LD1Onev2d, "ld1", ".2d", 0, false, 0 },
454 { AArch64::LD1Onev8b, "ld1", ".8b", 0, false, 0 },
455 { AArch64::LD1Onev4h, "ld1", ".4h", 0, false, 0 },
456 { AArch64::LD1Onev2s, "ld1", ".2s", 0, false, 0 },
457 { AArch64::LD1Onev1d, "ld1", ".1d", 0, false, 0 },
458 { AArch64::LD1Onev16b_POST, "ld1", ".16b", 1, false, 16 },
459 { AArch64::LD1Onev8h_POST, "ld1", ".8h", 1, false, 16 },
460 { AArch64::LD1Onev4s_POST, "ld1", ".4s", 1, false, 16 },
461 { AArch64::LD1Onev2d_POST, "ld1", ".2d", 1, false, 16 },
462 { AArch64::LD1Onev8b_POST, "ld1", ".8b", 1, false, 8 },
463 { AArch64::LD1Onev4h_POST, "ld1", ".4h", 1, false, 8 },
464 { AArch64::LD1Onev2s_POST, "ld1", ".2s", 1, false, 8 },
465 { AArch64::LD1Onev1d_POST, "ld1", ".1d", 1, false, 8 },
466 { AArch64::LD1Twov16b, "ld1", ".16b", 0, false, 0 },
467 { AArch64::LD1Twov8h, "ld1", ".8h", 0, false, 0 },
468 { AArch64::LD1Twov4s, "ld1", ".4s", 0, false, 0 },
469 { AArch64::LD1Twov2d, "ld1", ".2d", 0, false, 0 },
470 { AArch64::LD1Twov8b, "ld1", ".8b", 0, false, 0 },
471 { AArch64::LD1Twov4h, "ld1", ".4h", 0, false, 0 },
472 { AArch64::LD1Twov2s, "ld1", ".2s", 0, false, 0 },
473 { AArch64::LD1Twov1d, "ld1", ".1d", 0, false, 0 },
474 { AArch64::LD1Twov16b_POST, "ld1", ".16b", 1, false, 32 },
475 { AArch64::LD1Twov8h_POST, "ld1", ".8h", 1, false, 32 },
476 { AArch64::LD1Twov4s_POST, "ld1", ".4s", 1, false, 32 },
477 { AArch64::LD1Twov2d_POST, "ld1", ".2d", 1, false, 32 },
478 { AArch64::LD1Twov8b_POST, "ld1", ".8b", 1, false, 16 },
479 { AArch64::LD1Twov4h_POST, "ld1", ".4h", 1, false, 16 },
480 { AArch64::LD1Twov2s_POST, "ld1", ".2s", 1, false, 16 },
481 { AArch64::LD1Twov1d_POST, "ld1", ".1d", 1, false, 16 },
482 { AArch64::LD1Threev16b, "ld1", ".16b", 0, false, 0 },
483 { AArch64::LD1Threev8h, "ld1", ".8h", 0, false, 0 },
484 { AArch64::LD1Threev4s, "ld1", ".4s", 0, false, 0 },
485 { AArch64::LD1Threev2d, "ld1", ".2d", 0, false, 0 },
486 { AArch64::LD1Threev8b, "ld1", ".8b", 0, false, 0 },
487 { AArch64::LD1Threev4h, "ld1", ".4h", 0, false, 0 },
488 { AArch64::LD1Threev2s, "ld1", ".2s", 0, false, 0 },
489 { AArch64::LD1Threev1d, "ld1", ".1d", 0, false, 0 },
490 { AArch64::LD1Threev16b_POST, "ld1", ".16b", 1, false, 48 },
491 { AArch64::LD1Threev8h_POST, "ld1", ".8h", 1, false, 48 },
492 { AArch64::LD1Threev4s_POST, "ld1", ".4s", 1, false, 48 },
493 { AArch64::LD1Threev2d_POST, "ld1", ".2d", 1, false, 48 },
494 { AArch64::LD1Threev8b_POST, "ld1", ".8b", 1, false, 24 },
495 { AArch64::LD1Threev4h_POST, "ld1", ".4h", 1, false, 24 },
496 { AArch64::LD1Threev2s_POST, "ld1", ".2s", 1, false, 24 },
497 { AArch64::LD1Threev1d_POST, "ld1", ".1d", 1, false, 24 },
498 { AArch64::LD1Fourv16b, "ld1", ".16b", 0, false, 0 },
499 { AArch64::LD1Fourv8h, "ld1", ".8h", 0, false, 0 },
500 { AArch64::LD1Fourv4s, "ld1", ".4s", 0, false, 0 },
501 { AArch64::LD1Fourv2d, "ld1", ".2d", 0, false, 0 },
502 { AArch64::LD1Fourv8b, "ld1", ".8b", 0, false, 0 },
503 { AArch64::LD1Fourv4h, "ld1", ".4h", 0, false, 0 },
504 { AArch64::LD1Fourv2s, "ld1", ".2s", 0, false, 0 },
505 { AArch64::LD1Fourv1d, "ld1", ".1d", 0, false, 0 },
506 { AArch64::LD1Fourv16b_POST, "ld1", ".16b", 1, false, 64 },
507 { AArch64::LD1Fourv8h_POST, "ld1", ".8h", 1, false, 64 },
508 { AArch64::LD1Fourv4s_POST, "ld1", ".4s", 1, false, 64 },
509 { AArch64::LD1Fourv2d_POST, "ld1", ".2d", 1, false, 64 },
510 { AArch64::LD1Fourv8b_POST, "ld1", ".8b", 1, false, 32 },
511 { AArch64::LD1Fourv4h_POST, "ld1", ".4h", 1, false, 32 },
512 { AArch64::LD1Fourv2s_POST, "ld1", ".2s", 1, false, 32 },
513 { AArch64::LD1Fourv1d_POST, "ld1", ".1d", 1, false, 32 },
514 { AArch64::LD2i8, "ld2", ".b", 1, true, 0 },
515 { AArch64::LD2i16, "ld2", ".h", 1, true, 0 },
516 { AArch64::LD2i32, "ld2", ".s", 1, true, 0 },
517 { AArch64::LD2i64, "ld2", ".d", 1, true, 0 },
518 { AArch64::LD2i8_POST, "ld2", ".b", 2, true, 2 },
519 { AArch64::LD2i16_POST, "ld2", ".h", 2, true, 4 },
520 { AArch64::LD2i32_POST, "ld2", ".s", 2, true, 8 },
521 { AArch64::LD2i64_POST, "ld2", ".d", 2, true, 16 },
522 { AArch64::LD2Rv16b, "ld2r", ".16b", 0, false, 0 },
523 { AArch64::LD2Rv8h, "ld2r", ".8h", 0, false, 0 },
524 { AArch64::LD2Rv4s, "ld2r", ".4s", 0, false, 0 },
525 { AArch64::LD2Rv2d, "ld2r", ".2d", 0, false, 0 },
526 { AArch64::LD2Rv8b, "ld2r", ".8b", 0, false, 0 },
527 { AArch64::LD2Rv4h, "ld2r", ".4h", 0, false, 0 },
528 { AArch64::LD2Rv2s, "ld2r", ".2s", 0, false, 0 },
529 { AArch64::LD2Rv1d, "ld2r", ".1d", 0, false, 0 },
530 { AArch64::LD2Rv16b_POST, "ld2r", ".16b", 1, false, 2 },
531 { AArch64::LD2Rv8h_POST, "ld2r", ".8h", 1, false, 4 },
532 { AArch64::LD2Rv4s_POST, "ld2r", ".4s", 1, false, 8 },
533 { AArch64::LD2Rv2d_POST, "ld2r", ".2d", 1, false, 16 },
534 { AArch64::LD2Rv8b_POST, "ld2r", ".8b", 1, false, 2 },
535 { AArch64::LD2Rv4h_POST, "ld2r", ".4h", 1, false, 4 },
536 { AArch64::LD2Rv2s_POST, "ld2r", ".2s", 1, false, 8 },
537 { AArch64::LD2Rv1d_POST, "ld2r", ".1d", 1, false, 16 },
538 { AArch64::LD2Twov16b, "ld2", ".16b", 0, false, 0 },
539 { AArch64::LD2Twov8h, "ld2", ".8h", 0, false, 0 },
540 { AArch64::LD2Twov4s, "ld2", ".4s", 0, false, 0 },
541 { AArch64::LD2Twov2d, "ld2", ".2d", 0, false, 0 },
542 { AArch64::LD2Twov8b, "ld2", ".8b", 0, false, 0 },
543 { AArch64::LD2Twov4h, "ld2", ".4h", 0, false, 0 },
544 { AArch64::LD2Twov2s, "ld2", ".2s", 0, false, 0 },
545 { AArch64::LD2Twov16b_POST, "ld2", ".16b", 1, false, 32 },
546 { AArch64::LD2Twov8h_POST, "ld2", ".8h", 1, false, 32 },
547 { AArch64::LD2Twov4s_POST, "ld2", ".4s", 1, false, 32 },
548 { AArch64::LD2Twov2d_POST, "ld2", ".2d", 1, false, 32 },
549 { AArch64::LD2Twov8b_POST, "ld2", ".8b", 1, false, 16 },
550 { AArch64::LD2Twov4h_POST, "ld2", ".4h", 1, false, 16 },
551 { AArch64::LD2Twov2s_POST, "ld2", ".2s", 1, false, 16 },
552 { AArch64::LD3i8, "ld3", ".b", 1, true, 0 },
553 { AArch64::LD3i16, "ld3", ".h", 1, true, 0 },
554 { AArch64::LD3i32, "ld3", ".s", 1, true, 0 },
555 { AArch64::LD3i64, "ld3", ".d", 1, true, 0 },
556 { AArch64::LD3i8_POST, "ld3", ".b", 2, true, 3 },
557 { AArch64::LD3i16_POST, "ld3", ".h", 2, true, 6 },
558 { AArch64::LD3i32_POST, "ld3", ".s", 2, true, 12 },
559 { AArch64::LD3i64_POST, "ld3", ".d", 2, true, 24 },
560 { AArch64::LD3Rv16b, "ld3r", ".16b", 0, false, 0 },
561 { AArch64::LD3Rv8h, "ld3r", ".8h", 0, false, 0 },
562 { AArch64::LD3Rv4s, "ld3r", ".4s", 0, false, 0 },
563 { AArch64::LD3Rv2d, "ld3r", ".2d", 0, false, 0 },
564 { AArch64::LD3Rv8b, "ld3r", ".8b", 0, false, 0 },
565 { AArch64::LD3Rv4h, "ld3r", ".4h", 0, false, 0 },
566 { AArch64::LD3Rv2s, "ld3r", ".2s", 0, false, 0 },
567 { AArch64::LD3Rv1d, "ld3r", ".1d", 0, false, 0 },
568 { AArch64::LD3Rv16b_POST, "ld3r", ".16b", 1, false, 3 },
569 { AArch64::LD3Rv8h_POST, "ld3r", ".8h", 1, false, 6 },
570 { AArch64::LD3Rv4s_POST, "ld3r", ".4s", 1, false, 12 },
571 { AArch64::LD3Rv2d_POST, "ld3r", ".2d", 1, false, 24 },
572 { AArch64::LD3Rv8b_POST, "ld3r", ".8b", 1, false, 3 },
573 { AArch64::LD3Rv4h_POST, "ld3r", ".4h", 1, false, 6 },
574 { AArch64::LD3Rv2s_POST, "ld3r", ".2s", 1, false, 12 },
575 { AArch64::LD3Rv1d_POST, "ld3r", ".1d", 1, false, 24 },
576 { AArch64::LD3Threev16b, "ld3", ".16b", 0, false, 0 },
577 { AArch64::LD3Threev8h, "ld3", ".8h", 0, false, 0 },
578 { AArch64::LD3Threev4s, "ld3", ".4s", 0, false, 0 },
579 { AArch64::LD3Threev2d, "ld3", ".2d", 0, false, 0 },
580 { AArch64::LD3Threev8b, "ld3", ".8b", 0, false, 0 },
581 { AArch64::LD3Threev4h, "ld3", ".4h", 0, false, 0 },
582 { AArch64::LD3Threev2s, "ld3", ".2s", 0, false, 0 },
583 { AArch64::LD3Threev16b_POST, "ld3", ".16b", 1, false, 48 },
584 { AArch64::LD3Threev8h_POST, "ld3", ".8h", 1, false, 48 },
585 { AArch64::LD3Threev4s_POST, "ld3", ".4s", 1, false, 48 },
586 { AArch64::LD3Threev2d_POST, "ld3", ".2d", 1, false, 48 },
587 { AArch64::LD3Threev8b_POST, "ld3", ".8b", 1, false, 24 },
588 { AArch64::LD3Threev4h_POST, "ld3", ".4h", 1, false, 24 },
589 { AArch64::LD3Threev2s_POST, "ld3", ".2s", 1, false, 24 },
590 { AArch64::LD4i8, "ld4", ".b", 1, true, 0 },
591 { AArch64::LD4i16, "ld4", ".h", 1, true, 0 },
592 { AArch64::LD4i32, "ld4", ".s", 1, true, 0 },
593 { AArch64::LD4i64, "ld4", ".d", 1, true, 0 },
594 { AArch64::LD4i8_POST, "ld4", ".b", 2, true, 4 },
595 { AArch64::LD4i16_POST, "ld4", ".h", 2, true, 8 },
596 { AArch64::LD4i32_POST, "ld4", ".s", 2, true, 16 },
597 { AArch64::LD4i64_POST, "ld4", ".d", 2, true, 32 },
598 { AArch64::LD4Rv16b, "ld4r", ".16b", 0, false, 0 },
599 { AArch64::LD4Rv8h, "ld4r", ".8h", 0, false, 0 },
600 { AArch64::LD4Rv4s, "ld4r", ".4s", 0, false, 0 },
601 { AArch64::LD4Rv2d, "ld4r", ".2d", 0, false, 0 },
602 { AArch64::LD4Rv8b, "ld4r", ".8b", 0, false, 0 },
603 { AArch64::LD4Rv4h, "ld4r", ".4h", 0, false, 0 },
604 { AArch64::LD4Rv2s, "ld4r", ".2s", 0, false, 0 },
605 { AArch64::LD4Rv1d, "ld4r", ".1d", 0, false, 0 },
606 { AArch64::LD4Rv16b_POST, "ld4r", ".16b", 1, false, 4 },
607 { AArch64::LD4Rv8h_POST, "ld4r", ".8h", 1, false, 8 },
608 { AArch64::LD4Rv4s_POST, "ld4r", ".4s", 1, false, 16 },
609 { AArch64::LD4Rv2d_POST, "ld4r", ".2d", 1, false, 32 },
610 { AArch64::LD4Rv8b_POST, "ld4r", ".8b", 1, false, 4 },
611 { AArch64::LD4Rv4h_POST, "ld4r", ".4h", 1, false, 8 },
612 { AArch64::LD4Rv2s_POST, "ld4r", ".2s", 1, false, 16 },
613 { AArch64::LD4Rv1d_POST, "ld4r", ".1d", 1, false, 32 },
614 { AArch64::LD4Fourv16b, "ld4", ".16b", 0, false, 0 },
615 { AArch64::LD4Fourv8h, "ld4", ".8h", 0, false, 0 },
616 { AArch64::LD4Fourv4s, "ld4", ".4s", 0, false, 0 },
617 { AArch64::LD4Fourv2d, "ld4", ".2d", 0, false, 0 },
618 { AArch64::LD4Fourv8b, "ld4", ".8b", 0, false, 0 },
619 { AArch64::LD4Fourv4h, "ld4", ".4h", 0, false, 0 },
620 { AArch64::LD4Fourv2s, "ld4", ".2s", 0, false, 0 },
621 { AArch64::LD4Fourv16b_POST, "ld4", ".16b", 1, false, 64 },
622 { AArch64::LD4Fourv8h_POST, "ld4", ".8h", 1, false, 64 },
623 { AArch64::LD4Fourv4s_POST, "ld4", ".4s", 1, false, 64 },
624 { AArch64::LD4Fourv2d_POST, "ld4", ".2d", 1, false, 64 },
625 { AArch64::LD4Fourv8b_POST, "ld4", ".8b", 1, false, 32 },
626 { AArch64::LD4Fourv4h_POST, "ld4", ".4h", 1, false, 32 },
627 { AArch64::LD4Fourv2s_POST, "ld4", ".2s", 1, false, 32 },
628 { AArch64::ST1i8, "st1", ".b", 0, true, 0 },
629 { AArch64::ST1i16, "st1", ".h", 0, true, 0 },
630 { AArch64::ST1i32, "st1", ".s", 0, true, 0 },
631 { AArch64::ST1i64, "st1", ".d", 0, true, 0 },
632 { AArch64::ST1i8_POST, "st1", ".b", 1, true, 1 },
633 { AArch64::ST1i16_POST, "st1", ".h", 1, true, 2 },
634 { AArch64::ST1i32_POST, "st1", ".s", 1, true, 4 },
635 { AArch64::ST1i64_POST, "st1", ".d", 1, true, 8 },
636 { AArch64::ST1Onev16b, "st1", ".16b", 0, false, 0 },
637 { AArch64::ST1Onev8h, "st1", ".8h", 0, false, 0 },
638 { AArch64::ST1Onev4s, "st1", ".4s", 0, false, 0 },
639 { AArch64::ST1Onev2d, "st1", ".2d", 0, false, 0 },
640 { AArch64::ST1Onev8b, "st1", ".8b", 0, false, 0 },
641 { AArch64::ST1Onev4h, "st1", ".4h", 0, false, 0 },
642 { AArch64::ST1Onev2s, "st1", ".2s", 0, false, 0 },
643 { AArch64::ST1Onev1d, "st1", ".1d", 0, false, 0 },
644 { AArch64::ST1Onev16b_POST, "st1", ".16b", 1, false, 16 },
645 { AArch64::ST1Onev8h_POST, "st1", ".8h", 1, false, 16 },
646 { AArch64::ST1Onev4s_POST, "st1", ".4s", 1, false, 16 },
647 { AArch64::ST1Onev2d_POST, "st1", ".2d", 1, false, 16 },
648 { AArch64::ST1Onev8b_POST, "st1", ".8b", 1, false, 8 },
649 { AArch64::ST1Onev4h_POST, "st1", ".4h", 1, false, 8 },
650 { AArch64::ST1Onev2s_POST, "st1", ".2s", 1, false, 8 },
651 { AArch64::ST1Onev1d_POST, "st1", ".1d", 1, false, 8 },
652 { AArch64::ST1Twov16b, "st1", ".16b", 0, false, 0 },
653 { AArch64::ST1Twov8h, "st1", ".8h", 0, false, 0 },
654 { AArch64::ST1Twov4s, "st1", ".4s", 0, false, 0 },
655 { AArch64::ST1Twov2d, "st1", ".2d", 0, false, 0 },
656 { AArch64::ST1Twov8b, "st1", ".8b", 0, false, 0 },
657 { AArch64::ST1Twov4h, "st1", ".4h", 0, false, 0 },
658 { AArch64::ST1Twov2s, "st1", ".2s", 0, false, 0 },
659 { AArch64::ST1Twov1d, "st1", ".1d", 0, false, 0 },
660 { AArch64::ST1Twov16b_POST, "st1", ".16b", 1, false, 32 },
661 { AArch64::ST1Twov8h_POST, "st1", ".8h", 1, false, 32 },
662 { AArch64::ST1Twov4s_POST, "st1", ".4s", 1, false, 32 },
663 { AArch64::ST1Twov2d_POST, "st1", ".2d", 1, false, 32 },
664 { AArch64::ST1Twov8b_POST, "st1", ".8b", 1, false, 16 },
665 { AArch64::ST1Twov4h_POST, "st1", ".4h", 1, false, 16 },
666 { AArch64::ST1Twov2s_POST, "st1", ".2s", 1, false, 16 },
667 { AArch64::ST1Twov1d_POST, "st1", ".1d", 1, false, 16 },
668 { AArch64::ST1Threev16b, "st1", ".16b", 0, false, 0 },
669 { AArch64::ST1Threev8h, "st1", ".8h", 0, false, 0 },
670 { AArch64::ST1Threev4s, "st1", ".4s", 0, false, 0 },
671 { AArch64::ST1Threev2d, "st1", ".2d", 0, false, 0 },
672 { AArch64::ST1Threev8b, "st1", ".8b", 0, false, 0 },
673 { AArch64::ST1Threev4h, "st1", ".4h", 0, false, 0 },
674 { AArch64::ST1Threev2s, "st1", ".2s", 0, false, 0 },
675 { AArch64::ST1Threev1d, "st1", ".1d", 0, false, 0 },
676 { AArch64::ST1Threev16b_POST, "st1", ".16b", 1, false, 48 },
677 { AArch64::ST1Threev8h_POST, "st1", ".8h", 1, false, 48 },
678 { AArch64::ST1Threev4s_POST, "st1", ".4s", 1, false, 48 },
679 { AArch64::ST1Threev2d_POST, "st1", ".2d", 1, false, 48 },
680 { AArch64::ST1Threev8b_POST, "st1", ".8b", 1, false, 24 },
681 { AArch64::ST1Threev4h_POST, "st1", ".4h", 1, false, 24 },
682 { AArch64::ST1Threev2s_POST, "st1", ".2s", 1, false, 24 },
683 { AArch64::ST1Threev1d_POST, "st1", ".1d", 1, false, 24 },
684 { AArch64::ST1Fourv16b, "st1", ".16b", 0, false, 0 },
685 { AArch64::ST1Fourv8h, "st1", ".8h", 0, false, 0 },
686 { AArch64::ST1Fourv4s, "st1", ".4s", 0, false, 0 },
687 { AArch64::ST1Fourv2d, "st1", ".2d", 0, false, 0 },
688 { AArch64::ST1Fourv8b, "st1", ".8b", 0, false, 0 },
689 { AArch64::ST1Fourv4h, "st1", ".4h", 0, false, 0 },
690 { AArch64::ST1Fourv2s, "st1", ".2s", 0, false, 0 },
691 { AArch64::ST1Fourv1d, "st1", ".1d", 0, false, 0 },
692 { AArch64::ST1Fourv16b_POST, "st1", ".16b", 1, false, 64 },
693 { AArch64::ST1Fourv8h_POST, "st1", ".8h", 1, false, 64 },
694 { AArch64::ST1Fourv4s_POST, "st1", ".4s", 1, false, 64 },
695 { AArch64::ST1Fourv2d_POST, "st1", ".2d", 1, false, 64 },
696 { AArch64::ST1Fourv8b_POST, "st1", ".8b", 1, false, 32 },
697 { AArch64::ST1Fourv4h_POST, "st1", ".4h", 1, false, 32 },
698 { AArch64::ST1Fourv2s_POST, "st1", ".2s", 1, false, 32 },
699 { AArch64::ST1Fourv1d_POST, "st1", ".1d", 1, false, 32 },
700 { AArch64::ST2i8, "st2", ".b", 0, true, 0 },
701 { AArch64::ST2i16, "st2", ".h", 0, true, 0 },
702 { AArch64::ST2i32, "st2", ".s", 0, true, 0 },
703 { AArch64::ST2i64, "st2", ".d", 0, true, 0 },
704 { AArch64::ST2i8_POST, "st2", ".b", 1, true, 2 },
705 { AArch64::ST2i16_POST, "st2", ".h", 1, true, 4 },
706 { AArch64::ST2i32_POST, "st2", ".s", 1, true, 8 },
707 { AArch64::ST2i64_POST, "st2", ".d", 1, true, 16 },
708 { AArch64::ST2Twov16b, "st2", ".16b", 0, false, 0 },
709 { AArch64::ST2Twov8h, "st2", ".8h", 0, false, 0 },
710 { AArch64::ST2Twov4s, "st2", ".4s", 0, false, 0 },
711 { AArch64::ST2Twov2d, "st2", ".2d", 0, false, 0 },
712 { AArch64::ST2Twov8b, "st2", ".8b", 0, false, 0 },
713 { AArch64::ST2Twov4h, "st2", ".4h", 0, false, 0 },
714 { AArch64::ST2Twov2s, "st2", ".2s", 0, false, 0 },
715 { AArch64::ST2Twov16b_POST, "st2", ".16b", 1, false, 32 },
716 { AArch64::ST2Twov8h_POST, "st2", ".8h", 1, false, 32 },
717 { AArch64::ST2Twov4s_POST, "st2", ".4s", 1, false, 32 },
718 { AArch64::ST2Twov2d_POST, "st2", ".2d", 1, false, 32 },
719 { AArch64::ST2Twov8b_POST, "st2", ".8b", 1, false, 16 },
720 { AArch64::ST2Twov4h_POST, "st2", ".4h", 1, false, 16 },
721 { AArch64::ST2Twov2s_POST, "st2", ".2s", 1, false, 16 },
722 { AArch64::ST3i8, "st3", ".b", 0, true, 0 },
723 { AArch64::ST3i16, "st3", ".h", 0, true, 0 },
724 { AArch64::ST3i32, "st3", ".s", 0, true, 0 },
725 { AArch64::ST3i64, "st3", ".d", 0, true, 0 },
726 { AArch64::ST3i8_POST, "st3", ".b", 1, true, 3 },
727 { AArch64::ST3i16_POST, "st3", ".h", 1, true, 6 },
728 { AArch64::ST3i32_POST, "st3", ".s", 1, true, 12 },
729 { AArch64::ST3i64_POST, "st3", ".d", 1, true, 24 },
730 { AArch64::ST3Threev16b, "st3", ".16b", 0, false, 0 },
731 { AArch64::ST3Threev8h, "st3", ".8h", 0, false, 0 },
732 { AArch64::ST3Threev4s, "st3", ".4s", 0, false, 0 },
733 { AArch64::ST3Threev2d, "st3", ".2d", 0, false, 0 },
734 { AArch64::ST3Threev8b, "st3", ".8b", 0, false, 0 },
735 { AArch64::ST3Threev4h, "st3", ".4h", 0, false, 0 },
736 { AArch64::ST3Threev2s, "st3", ".2s", 0, false, 0 },
737 { AArch64::ST3Threev16b_POST, "st3", ".16b", 1, false, 48 },
738 { AArch64::ST3Threev8h_POST, "st3", ".8h", 1, false, 48 },
739 { AArch64::ST3Threev4s_POST, "st3", ".4s", 1, false, 48 },
740 { AArch64::ST3Threev2d_POST, "st3", ".2d", 1, false, 48 },
741 { AArch64::ST3Threev8b_POST, "st3", ".8b", 1, false, 24 },
742 { AArch64::ST3Threev4h_POST, "st3", ".4h", 1, false, 24 },
743 { AArch64::ST3Threev2s_POST, "st3", ".2s", 1, false, 24 },
744 { AArch64::ST4i8, "st4", ".b", 0, true, 0 },
745 { AArch64::ST4i16, "st4", ".h", 0, true, 0 },
746 { AArch64::ST4i32, "st4", ".s", 0, true, 0 },
747 { AArch64::ST4i64, "st4", ".d", 0, true, 0 },
748 { AArch64::ST4i8_POST, "st4", ".b", 1, true, 4 },
749 { AArch64::ST4i16_POST, "st4", ".h", 1, true, 8 },
750 { AArch64::ST4i32_POST, "st4", ".s", 1, true, 16 },
751 { AArch64::ST4i64_POST, "st4", ".d", 1, true, 32 },
752 { AArch64::ST4Fourv16b, "st4", ".16b", 0, false, 0 },
753 { AArch64::ST4Fourv8h, "st4", ".8h", 0, false, 0 },
754 { AArch64::ST4Fourv4s, "st4", ".4s", 0, false, 0 },
755 { AArch64::ST4Fourv2d, "st4", ".2d", 0, false, 0 },
756 { AArch64::ST4Fourv8b, "st4", ".8b", 0, false, 0 },
757 { AArch64::ST4Fourv4h, "st4", ".4h", 0, false, 0 },
758 { AArch64::ST4Fourv2s, "st4", ".2s", 0, false, 0 },
759 { AArch64::ST4Fourv16b_POST, "st4", ".16b", 1, false, 64 },
760 { AArch64::ST4Fourv8h_POST, "st4", ".8h", 1, false, 64 },
761 { AArch64::ST4Fourv4s_POST, "st4", ".4s", 1, false, 64 },
762 { AArch64::ST4Fourv2d_POST, "st4", ".2d", 1, false, 64 },
763 { AArch64::ST4Fourv8b_POST, "st4", ".8b", 1, false, 32 },
764 { AArch64::ST4Fourv4h_POST, "st4", ".4h", 1, false, 32 },
765 { AArch64::ST4Fourv2s_POST, "st4", ".2s", 1, false, 32 },
766};
767
768static const LdStNInstrDesc *getLdStNInstrDesc(unsigned Opcode) {
769 for (const auto &Info : LdStNInstInfo)
770 if (Info.Opcode == Opcode)
771 return &Info;
772
773 return nullptr;
774}
775
776void AArch64AppleInstPrinter::printInst(const MCInst *MI, uint64_t Address,
777 StringRef Annot,
778 const MCSubtargetInfo &STI,
779 raw_ostream &O) {
780 unsigned Opcode = MI->getOpcode();
781 StringRef Layout;
782
783 bool IsTbx;
784 if (isTblTbxInstruction(MI->getOpcode(), Layout, IsTbx)) {
785 O << "\t" << (IsTbx ? "tbx" : "tbl") << Layout << '\t';
786 printRegName(O, MI->getOperand(0).getReg(), AArch64::vreg);
787 O << ", ";
788
789 unsigned ListOpNum = IsTbx ? 2 : 1;
790 printVectorList(MI, ListOpNum, STI, O, "");
791
792 O << ", ";
793 printRegName(O, MI->getOperand(ListOpNum + 1).getReg(), AArch64::vreg);
794 printAnnotation(O, Annot);
795 return;
796 }
797
798 if (const LdStNInstrDesc *LdStDesc = getLdStNInstrDesc(Opcode)) {
799 O << "\t" << LdStDesc->Mnemonic << LdStDesc->Layout << '\t';
800
801 // Now onto the operands: first a vector list with possible lane
802 // specifier. E.g. { v0 }[2]
803 int OpNum = LdStDesc->ListOperand;
804 printVectorList(MI, OpNum++, STI, O, "");
805
806 if (LdStDesc->HasLane)
807 O << '[' << MI->getOperand(OpNum++).getImm() << ']';
808
809 // Next the address: [xN]
810 MCRegister AddrReg = MI->getOperand(OpNum++).getReg();
811 O << ", [";
812 printRegName(O, AddrReg);
813 O << ']';
814
815 // Finally, there might be a post-indexed offset.
816 if (LdStDesc->NaturalOffset != 0) {
817 MCRegister Reg = MI->getOperand(OpNum++).getReg();
818 if (Reg != AArch64::XZR) {
819 O << ", ";
820 printRegName(O, Reg);
821 } else {
822 assert(LdStDesc->NaturalOffset && "no offset on post-inc instruction?");
823 O << ", ";
824 markup(O, Markup::Immediate) << "#" << LdStDesc->NaturalOffset;
825 }
826 }
827
828 printAnnotation(O, Annot);
829 return;
830 }
831
832 AArch64InstPrinter::printInst(MI, Address, Annot, STI, O);
833}
834
838
839bool AArch64InstPrinter::printRangePrefetchAlias(const MCInst *MI,
840 const MCSubtargetInfo &STI,
841 raw_ostream &O,
842 StringRef Annot) {
843 unsigned Opcode = MI->getOpcode();
844
845#ifndef NDEBUG
846 assert(((Opcode == AArch64::PRFMroX) || (Opcode == AArch64::PRFMroW)) &&
847 "Invalid opcode for RPRFM alias!");
848#endif
849
850 unsigned PRFOp = MI->getOperand(0).getImm();
851 unsigned Mask = 0x18; // 0b11000
852 if ((PRFOp & Mask) != Mask)
853 return false; // Rt != '11xxx', it's a PRFM instruction.
854
855 MCRegister Rm = MI->getOperand(2).getReg();
856
857 // "Rm" must be a 64-bit GPR for RPRFM.
858 if (MRI.getRegClass(AArch64::GPR32RegClassID).contains(Rm))
859 Rm = MRI.getMatchingSuperReg(Rm, AArch64::sub_32,
860 &MRI.getRegClass(AArch64::GPR64RegClassID));
861
862 unsigned SignExtend = MI->getOperand(3).getImm(); // encoded in "option<2>".
863 unsigned Shift = MI->getOperand(4).getImm(); // encoded in "S".
864
865 assert((SignExtend <= 1) && "sign extend should be a single bit!");
866 assert((Shift <= 1) && "Shift should be a single bit!");
867
868 unsigned Option0 = (Opcode == AArch64::PRFMroX) ? 1 : 0;
869
870 // encoded in "option<2>:option<0>:S:Rt<2:0>".
871 unsigned RPRFOp =
872 (SignExtend << 5) | (Option0 << 4) | (Shift << 3) | (PRFOp & 0x7);
873
874 O << "\trprfm ";
875 if (auto RPRFM = AArch64RPRFM::lookupRPRFMByEncoding(RPRFOp))
876 O << RPRFM->Name << ", ";
877 else
878 O << "#" << formatImm(RPRFOp) << ", ";
879 O << getRegisterName(Rm);
880 O << ", [";
881 printOperand(MI, 1, STI, O); // "Rn".
882 O << "]";
883
884 printAnnotation(O, Annot);
885
886 return true;
887}
888
889bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
890 const MCSubtargetInfo &STI,
891 raw_ostream &O) {
892#ifndef NDEBUG
893 unsigned Opcode = MI->getOpcode();
894 assert(Opcode == AArch64::SYSxt && "Invalid opcode for SYS alias!");
895#endif
896
897 const MCOperand &Op1 = MI->getOperand(0);
898 const MCOperand &Cn = MI->getOperand(1);
899 const MCOperand &Cm = MI->getOperand(2);
900 const MCOperand &Op2 = MI->getOperand(3);
901
902 unsigned Op1Val = Op1.getImm();
903 unsigned CnVal = Cn.getImm();
904 unsigned CmVal = Cm.getImm();
905 unsigned Op2Val = Op2.getImm();
906
907 uint16_t Encoding = Op2Val;
908 Encoding |= CmVal << 3;
909 Encoding |= CnVal << 7;
910 Encoding |= Op1Val << 11;
911
912 bool NeedsReg;
913 std::string Ins;
914 std::string Name;
915
916 if (CnVal == 7) {
917 switch (CmVal) {
918 default: return false;
919 // Maybe IC, maybe Prediction Restriction
920 case 1:
921 switch (Op1Val) {
922 default: return false;
923 case 0: goto Search_IC;
924 case 3: goto Search_PRCTX;
925 }
926 // Prediction Restriction aliases
927 case 3: {
928 Search_PRCTX:
929 if (Op1Val != 3 || CnVal != 7 || CmVal != 3)
930 return false;
931
932 const auto Requires =
933 Op2Val == 6 ? AArch64::FeatureSPECRES2 : AArch64::FeaturePredRes;
934 if (!(STI.hasFeature(AArch64::FeatureAll) || STI.hasFeature(Requires)))
935 return false;
936
937 NeedsReg = true;
938 switch (Op2Val) {
939 default: return false;
940 case 4: Ins = "cfp\t"; break;
941 case 5: Ins = "dvp\t"; break;
942 case 6: Ins = "cosp\t"; break;
943 case 7: Ins = "cpp\t"; break;
944 }
945 Name = "RCTX";
946 }
947 break;
948 // IC aliases
949 case 5: {
950 Search_IC:
951 const AArch64IC::IC *IC = AArch64IC::lookupICByEncoding(Encoding);
952 if (!IC || !IC->haveFeatures(STI.getFeatureBits()))
953 return false;
954
955 NeedsReg = IC->NeedsReg;
956 Ins = "ic\t";
957 Name = std::string(IC->Name);
958 }
959 break;
960 // DC aliases
961 case 4: case 6: case 10: case 11: case 12: case 13: case 14:
962 {
963 const AArch64DC::DC *DC = AArch64DC::lookupDCByEncoding(Encoding);
964 if (!DC || !DC->haveFeatures(STI.getFeatureBits()))
965 return false;
966
967 NeedsReg = true;
968 Ins = "dc\t";
969 Name = std::string(DC->Name);
970 }
971 break;
972 // AT aliases
973 case 8: case 9: {
974 const AArch64AT::AT *AT = AArch64AT::lookupATByEncoding(Encoding);
975 if (!AT || !AT->haveFeatures(STI.getFeatureBits()))
976 return false;
977
978 NeedsReg = true;
979 Ins = "at\t";
980 Name = std::string(AT->Name);
981 }
982 break;
983 // Overlaps with AT and DC
984 case 15: {
985 const AArch64AT::AT *AT = AArch64AT::lookupATByEncoding(Encoding);
986 const AArch64DC::DC *DC = AArch64DC::lookupDCByEncoding(Encoding);
987 if (AT && AT->haveFeatures(STI.getFeatureBits())) {
988 NeedsReg = true;
989 Ins = "at\t";
990 Name = std::string(AT->Name);
991 } else if (DC && DC->haveFeatures(STI.getFeatureBits())) {
992 NeedsReg = true;
993 Ins = "dc\t";
994 Name = std::string(DC->Name);
995 } else {
996 return false;
997 }
998 } break;
999 }
1000 } else if (CnVal == 8 || CnVal == 9) {
1001 // TLBI aliases
1002 const AArch64TLBI::TLBI *TLBI = AArch64TLBI::lookupTLBIByEncoding(Encoding);
1003 if (!TLBI || !TLBI->haveFeatures(STI.getFeatureBits()))
1004 return false;
1005
1006 NeedsReg = TLBI->NeedsReg;
1007 Ins = "tlbi\t";
1008 Name = std::string(TLBI->Name);
1009 }
1010 else
1011 return false;
1012
1013 StringRef Reg = getRegisterName(MI->getOperand(4).getReg());
1014 bool NotXZR = Reg != "xzr";
1015
1016 // If a mandatory is not specified in the TableGen
1017 // (i.e. no register operand should be present), and the register value
1018 // is not xzr/x31, then disassemble to a SYS alias instead.
1019 if (NotXZR && !NeedsReg)
1020 return false;
1021
1022 std::string Str = Ins + Name;
1023 llvm::transform(Str, Str.begin(), ::tolower);
1024
1025 O << '\t' << Str;
1026
1027 if (NeedsReg)
1028 O << ", " << Reg;
1029
1030 return true;
1031}
1032
1033bool AArch64InstPrinter::printSyspAlias(const MCInst *MI,
1034 const MCSubtargetInfo &STI,
1035 raw_ostream &O) {
1036#ifndef NDEBUG
1037 unsigned Opcode = MI->getOpcode();
1038 assert((Opcode == AArch64::SYSPxt || Opcode == AArch64::SYSPxt_XZR) &&
1039 "Invalid opcode for SYSP alias!");
1040#endif
1041
1042 const MCOperand &Op1 = MI->getOperand(0);
1043 const MCOperand &Cn = MI->getOperand(1);
1044 const MCOperand &Cm = MI->getOperand(2);
1045 const MCOperand &Op2 = MI->getOperand(3);
1046
1047 unsigned Op1Val = Op1.getImm();
1048 unsigned CnVal = Cn.getImm();
1049 unsigned CmVal = Cm.getImm();
1050 unsigned Op2Val = Op2.getImm();
1051
1052 uint16_t Encoding = Op2Val;
1053 Encoding |= CmVal << 3;
1054 Encoding |= CnVal << 7;
1055 Encoding |= Op1Val << 11;
1056
1057 std::string Ins;
1058 std::string Name;
1059
1060 if (CnVal == 8 || CnVal == 9) {
1061 // TLBIP aliases
1062
1063 if (CnVal == 9) {
1064 if (!STI.hasFeature(AArch64::FeatureXS))
1065 return false;
1066 Encoding &= ~(1 << 7);
1067 }
1068
1069 const AArch64TLBI::TLBI *TLBI = AArch64TLBI::lookupTLBIByEncoding(Encoding);
1070 if (!TLBI || !TLBI->haveFeatures(STI.getFeatureBits()))
1071 return false;
1072
1073 Ins = "tlbip\t";
1074 Name = std::string(TLBI->Name);
1075 if (CnVal == 9)
1076 Name += "nXS";
1077 } else
1078 return false;
1079
1080 std::string Str = Ins + Name;
1081 llvm::transform(Str, Str.begin(), ::tolower);
1082
1083 O << '\t' << Str;
1084 O << ", ";
1085 if (MI->getOperand(4).getReg() == AArch64::XZR)
1086 printSyspXzrPair(MI, 4, STI, O);
1087 else
1088 printGPRSeqPairsClassOperand<64>(MI, 4, STI, O);
1089
1090 return true;
1091}
1092
1093template <int EltSize>
1094void AArch64InstPrinter::printMatrix(const MCInst *MI, unsigned OpNum,
1095 const MCSubtargetInfo &STI,
1096 raw_ostream &O) {
1097 const MCOperand &RegOp = MI->getOperand(OpNum);
1098 assert(RegOp.isReg() && "Unexpected operand type!");
1099
1100 printRegName(O, RegOp.getReg());
1101 switch (EltSize) {
1102 case 0:
1103 break;
1104 case 8:
1105 O << ".b";
1106 break;
1107 case 16:
1108 O << ".h";
1109 break;
1110 case 32:
1111 O << ".s";
1112 break;
1113 case 64:
1114 O << ".d";
1115 break;
1116 case 128:
1117 O << ".q";
1118 break;
1119 default:
1120 llvm_unreachable("Unsupported element size");
1121 }
1122}
1123
1124template <bool IsVertical>
1125void AArch64InstPrinter::printMatrixTileVector(const MCInst *MI, unsigned OpNum,
1126 const MCSubtargetInfo &STI,
1127 raw_ostream &O) {
1128 const MCOperand &RegOp = MI->getOperand(OpNum);
1129 assert(RegOp.isReg() && "Unexpected operand type!");
1130 StringRef RegName = getRegisterName(RegOp.getReg());
1131
1132 // Insert the horizontal/vertical flag before the suffix.
1133 StringRef Base, Suffix;
1134 std::tie(Base, Suffix) = RegName.split('.');
1135 O << Base << (IsVertical ? "v" : "h") << '.' << Suffix;
1136}
1137
1138void AArch64InstPrinter::printMatrixTile(const MCInst *MI, unsigned OpNum,
1139 const MCSubtargetInfo &STI,
1140 raw_ostream &O) {
1141 const MCOperand &RegOp = MI->getOperand(OpNum);
1142 assert(RegOp.isReg() && "Unexpected operand type!");
1143 printRegName(O, RegOp.getReg());
1144}
1145
1146void AArch64InstPrinter::printSVCROp(const MCInst *MI, unsigned OpNum,
1147 const MCSubtargetInfo &STI,
1148 raw_ostream &O) {
1149 const MCOperand &MO = MI->getOperand(OpNum);
1150 assert(MO.isImm() && "Unexpected operand type!");
1151 unsigned svcrop = MO.getImm();
1152 const auto *SVCR = AArch64SVCR::lookupSVCRByEncoding(svcrop);
1153 assert(SVCR && "Unexpected SVCR operand!");
1154 O << SVCR->Name;
1155}
1156
1157void AArch64InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
1158 const MCSubtargetInfo &STI,
1159 raw_ostream &O) {
1160 const MCOperand &Op = MI->getOperand(OpNo);
1161 if (Op.isReg()) {
1162 printRegName(O, Op.getReg());
1163 } else if (Op.isImm()) {
1164 printImm(MI, OpNo, STI, O);
1165 } else {
1166 assert(Op.isExpr() && "unknown operand kind in printOperand");
1167 MAI.printExpr(O, *Op.getExpr());
1168 }
1169}
1170
1171void AArch64InstPrinter::printImm(const MCInst *MI, unsigned OpNo,
1172 const MCSubtargetInfo &STI,
1173 raw_ostream &O) {
1174 const MCOperand &Op = MI->getOperand(OpNo);
1175 markup(O, Markup::Immediate) << "#" << formatImm(Op.getImm());
1176}
1177
1178void AArch64InstPrinter::printImmHex(const MCInst *MI, unsigned OpNo,
1179 const MCSubtargetInfo &STI,
1180 raw_ostream &O) {
1181 const MCOperand &Op = MI->getOperand(OpNo);
1182 markup(O, Markup::Immediate) << format("#%#llx", Op.getImm());
1183}
1184
1185template<int Size>
1186void AArch64InstPrinter::printSImm(const MCInst *MI, unsigned OpNo,
1187 const MCSubtargetInfo &STI,
1188 raw_ostream &O) {
1189 const MCOperand &Op = MI->getOperand(OpNo);
1190 if (Size == 8)
1191 markup(O, Markup::Immediate) << "#" << formatImm((signed char)Op.getImm());
1192 else if (Size == 16)
1193 markup(O, Markup::Immediate) << "#" << formatImm((signed short)Op.getImm());
1194 else
1195 markup(O, Markup::Immediate) << "#" << formatImm(Op.getImm());
1196}
1197
1198void AArch64InstPrinter::printPostIncOperand(const MCInst *MI, unsigned OpNo,
1199 unsigned Imm, raw_ostream &O) {
1200 const MCOperand &Op = MI->getOperand(OpNo);
1201 if (Op.isReg()) {
1202 MCRegister Reg = Op.getReg();
1203 if (Reg == AArch64::XZR)
1204 markup(O, Markup::Immediate) << "#" << Imm;
1205 else
1206 printRegName(O, Reg);
1207 } else
1208 llvm_unreachable("unknown operand kind in printPostIncOperand64");
1209}
1210
1211void AArch64InstPrinter::printVRegOperand(const MCInst *MI, unsigned OpNo,
1212 const MCSubtargetInfo &STI,
1213 raw_ostream &O) {
1214 const MCOperand &Op = MI->getOperand(OpNo);
1215 assert(Op.isReg() && "Non-register vreg operand!");
1216 printRegName(O, Op.getReg(), AArch64::vreg);
1217}
1218
1219void AArch64InstPrinter::printSysCROperand(const MCInst *MI, unsigned OpNo,
1220 const MCSubtargetInfo &STI,
1221 raw_ostream &O) {
1222 const MCOperand &Op = MI->getOperand(OpNo);
1223 assert(Op.isImm() && "System instruction C[nm] operands must be immediates!");
1224 O << "c" << Op.getImm();
1225}
1226
1227void AArch64InstPrinter::printAddSubImm(const MCInst *MI, unsigned OpNum,
1228 const MCSubtargetInfo &STI,
1229 raw_ostream &O) {
1230 const MCOperand &MO = MI->getOperand(OpNum);
1231 if (MO.isImm()) {
1232 unsigned Val = (MO.getImm() & 0xfff);
1233 assert(Val == MO.getImm() && "Add/sub immediate out of range!");
1234 unsigned Shift =
1235 AArch64_AM::getShiftValue(MI->getOperand(OpNum + 1).getImm());
1236 markup(O, Markup::Immediate) << '#' << formatImm(Val);
1237 if (Shift != 0) {
1238 printShifter(MI, OpNum + 1, STI, O);
1239 if (CommentStream)
1240 *CommentStream << '=' << formatImm(Val << Shift) << '\n';
1241 }
1242 } else {
1243 assert(MO.isExpr() && "Unexpected operand type!");
1244 MAI.printExpr(O, *MO.getExpr());
1245 printShifter(MI, OpNum + 1, STI, O);
1246 }
1247}
1248
1249template <typename T>
1250void AArch64InstPrinter::printLogicalImm(const MCInst *MI, unsigned OpNum,
1251 const MCSubtargetInfo &STI,
1252 raw_ostream &O) {
1253 uint64_t Val = MI->getOperand(OpNum).getImm();
1254 WithMarkup M = markup(O, Markup::Immediate);
1255 O << "#0x";
1256 O.write_hex(AArch64_AM::decodeLogicalImmediate(Val, 8 * sizeof(T)));
1257}
1258
1259void AArch64InstPrinter::printShifter(const MCInst *MI, unsigned OpNum,
1260 const MCSubtargetInfo &STI,
1261 raw_ostream &O) {
1262 unsigned Val = MI->getOperand(OpNum).getImm();
1263 // LSL #0 should not be printed.
1264 if (AArch64_AM::getShiftType(Val) == AArch64_AM::LSL &&
1265 AArch64_AM::getShiftValue(Val) == 0)
1266 return;
1267 O << ", " << AArch64_AM::getShiftExtendName(AArch64_AM::getShiftType(Val))
1268 << " ";
1269 markup(O, Markup::Immediate) << "#" << AArch64_AM::getShiftValue(Val);
1270}
1271
1272void AArch64InstPrinter::printShiftedRegister(const MCInst *MI, unsigned OpNum,
1273 const MCSubtargetInfo &STI,
1274 raw_ostream &O) {
1275 printRegName(O, MI->getOperand(OpNum).getReg());
1276 printShifter(MI, OpNum + 1, STI, O);
1277}
1278
1279void AArch64InstPrinter::printExtendedRegister(const MCInst *MI, unsigned OpNum,
1280 const MCSubtargetInfo &STI,
1281 raw_ostream &O) {
1282 printRegName(O, MI->getOperand(OpNum).getReg());
1283 printArithExtend(MI, OpNum + 1, STI, O);
1284}
1285
1286void AArch64InstPrinter::printArithExtend(const MCInst *MI, unsigned OpNum,
1287 const MCSubtargetInfo &STI,
1288 raw_ostream &O) {
1289 unsigned Val = MI->getOperand(OpNum).getImm();
1290 AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getArithExtendType(Val);
1291 unsigned ShiftVal = AArch64_AM::getArithShiftValue(Val);
1292
1293 // If the destination or first source register operand is [W]SP, print
1294 // UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing at
1295 // all.
1296 if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) {
1297 MCRegister Dest = MI->getOperand(0).getReg();
1298 MCRegister Src1 = MI->getOperand(1).getReg();
1299 if ( ((Dest == AArch64::SP || Src1 == AArch64::SP) &&
1300 ExtType == AArch64_AM::UXTX) ||
1301 ((Dest == AArch64::WSP || Src1 == AArch64::WSP) &&
1302 ExtType == AArch64_AM::UXTW) ) {
1303 if (ShiftVal != 0) {
1304 O << ", lsl ";
1305 markup(O, Markup::Immediate) << "#" << ShiftVal;
1306 }
1307 return;
1308 }
1309 }
1310 O << ", " << AArch64_AM::getShiftExtendName(ExtType);
1311 if (ShiftVal != 0) {
1312 O << " ";
1313 markup(O, Markup::Immediate) << "#" << ShiftVal;
1314 }
1315}
1316
1317void AArch64InstPrinter::printMemExtendImpl(bool SignExtend, bool DoShift,
1318 unsigned Width, char SrcRegKind,
1319 raw_ostream &O) {
1320 // sxtw, sxtx, uxtw or lsl (== uxtx)
1321 bool IsLSL = !SignExtend && SrcRegKind == 'x';
1322 if (IsLSL)
1323 O << "lsl";
1324 else
1325 O << (SignExtend ? 's' : 'u') << "xt" << SrcRegKind;
1326
1327 if (DoShift || IsLSL) {
1328 O << " ";
1329 markup(O, Markup::Immediate) << "#" << Log2_32(Width / 8);
1330 }
1331}
1332
1333void AArch64InstPrinter::printMemExtend(const MCInst *MI, unsigned OpNum,
1334 raw_ostream &O, char SrcRegKind,
1335 unsigned Width) {
1336 bool SignExtend = MI->getOperand(OpNum).getImm();
1337 bool DoShift = MI->getOperand(OpNum + 1).getImm();
1338 printMemExtendImpl(SignExtend, DoShift, Width, SrcRegKind, O);
1339}
1340
1341template <bool SignExtend, int ExtWidth, char SrcRegKind, char Suffix>
1342void AArch64InstPrinter::printRegWithShiftExtend(const MCInst *MI,
1343 unsigned OpNum,
1344 const MCSubtargetInfo &STI,
1345 raw_ostream &O) {
1346 printOperand(MI, OpNum, STI, O);
1347 if (Suffix == 's' || Suffix == 'd')
1348 O << '.' << Suffix;
1349 else
1350 assert(Suffix == 0 && "Unsupported suffix size");
1351
1352 bool DoShift = ExtWidth != 8;
1353 if (SignExtend || DoShift || SrcRegKind == 'w') {
1354 O << ", ";
1355 printMemExtendImpl(SignExtend, DoShift, ExtWidth, SrcRegKind, O);
1356 }
1357}
1358
1359template <int EltSize>
1360void AArch64InstPrinter::printPredicateAsCounter(const MCInst *MI,
1361 unsigned OpNum,
1362 const MCSubtargetInfo &STI,
1363 raw_ostream &O) {
1364 MCRegister Reg = MI->getOperand(OpNum).getReg();
1365 if (Reg < AArch64::PN0 || Reg > AArch64::PN15)
1366 llvm_unreachable("Unsupported predicate-as-counter register");
1367 O << "pn" << Reg - AArch64::PN0;
1368
1369 switch (EltSize) {
1370 case 0:
1371 break;
1372 case 8:
1373 O << ".b";
1374 break;
1375 case 16:
1376 O << ".h";
1377 break;
1378 case 32:
1379 O << ".s";
1380 break;
1381 case 64:
1382 O << ".d";
1383 break;
1384 default:
1385 llvm_unreachable("Unsupported element size");
1386 }
1387}
1388
1389void AArch64InstPrinter::printCondCode(const MCInst *MI, unsigned OpNum,
1390 const MCSubtargetInfo &STI,
1391 raw_ostream &O) {
1392 AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm();
1393 O << AArch64CC::getCondCodeName(CC);
1394}
1395
1396void AArch64InstPrinter::printInverseCondCode(const MCInst *MI, unsigned OpNum,
1397 const MCSubtargetInfo &STI,
1398 raw_ostream &O) {
1399 AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm();
1400 O << AArch64CC::getCondCodeName(AArch64CC::getInvertedCondCode(CC));
1401}
1402
1403void AArch64InstPrinter::printAMNoIndex(const MCInst *MI, unsigned OpNum,
1404 const MCSubtargetInfo &STI,
1405 raw_ostream &O) {
1406 O << '[';
1407 printRegName(O, MI->getOperand(OpNum).getReg());
1408 O << ']';
1409}
1410
1411template <int Scale>
1412void AArch64InstPrinter::printImmScale(const MCInst *MI, unsigned OpNum,
1413 const MCSubtargetInfo &STI,
1414 raw_ostream &O) {
1415 markup(O, Markup::Immediate)
1416 << '#' << formatImm(Scale * MI->getOperand(OpNum).getImm());
1417}
1418
1419template <int Scale, int Offset>
1420void AArch64InstPrinter::printImmRangeScale(const MCInst *MI, unsigned OpNum,
1421 const MCSubtargetInfo &STI,
1422 raw_ostream &O) {
1423 unsigned FirstImm = Scale * MI->getOperand(OpNum).getImm();
1424 O << formatImm(FirstImm);
1425 O << ":" << formatImm(FirstImm + Offset);
1426}
1427
1428void AArch64InstPrinter::printUImm12Offset(const MCInst *MI, unsigned OpNum,
1429 unsigned Scale, raw_ostream &O) {
1430 const MCOperand MO = MI->getOperand(OpNum);
1431 if (MO.isImm()) {
1432 markup(O, Markup::Immediate) << '#' << formatImm(MO.getImm() * Scale);
1433 } else {
1434 assert(MO.isExpr() && "Unexpected operand type!");
1435 MAI.printExpr(O, *MO.getExpr());
1436 }
1437}
1438
1439void AArch64InstPrinter::printAMIndexedWB(const MCInst *MI, unsigned OpNum,
1440 unsigned Scale, raw_ostream &O) {
1441 const MCOperand MO1 = MI->getOperand(OpNum + 1);
1442 O << '[';
1443 printRegName(O, MI->getOperand(OpNum).getReg());
1444 if (MO1.isImm()) {
1445 O << ", ";
1446 markup(O, Markup::Immediate) << "#" << formatImm(MO1.getImm() * Scale);
1447 } else {
1448 assert(MO1.isExpr() && "Unexpected operand type!");
1449 O << ", ";
1450 MAI.printExpr(O, *MO1.getExpr());
1451 }
1452 O << ']';
1453}
1454
1455void AArch64InstPrinter::printRPRFMOperand(const MCInst *MI, unsigned OpNum,
1456 const MCSubtargetInfo &STI,
1457 raw_ostream &O) {
1458 unsigned prfop = MI->getOperand(OpNum).getImm();
1459 if (auto PRFM = AArch64RPRFM::lookupRPRFMByEncoding(prfop)) {
1460 O << PRFM->Name;
1461 return;
1462 }
1463
1464 O << '#' << formatImm(prfop);
1465}
1466
1467template <bool IsSVEPrefetch>
1468void AArch64InstPrinter::printPrefetchOp(const MCInst *MI, unsigned OpNum,
1469 const MCSubtargetInfo &STI,
1470 raw_ostream &O) {
1471 unsigned prfop = MI->getOperand(OpNum).getImm();
1472 if (IsSVEPrefetch) {
1473 if (auto PRFM = AArch64SVEPRFM::lookupSVEPRFMByEncoding(prfop)) {
1474 O << PRFM->Name;
1475 return;
1476 }
1477 } else {
1478 auto PRFM = AArch64PRFM::lookupPRFMByEncoding(prfop);
1479 if (PRFM && PRFM->haveFeatures(STI.getFeatureBits())) {
1480 O << PRFM->Name;
1481 return;
1482 }
1483 }
1484
1485 markup(O, Markup::Immediate) << '#' << formatImm(prfop);
1486}
1487
1488void AArch64InstPrinter::printPSBHintOp(const MCInst *MI, unsigned OpNum,
1489 const MCSubtargetInfo &STI,
1490 raw_ostream &O) {
1491 unsigned psbhintop = MI->getOperand(OpNum).getImm();
1492 auto PSB = AArch64PSBHint::lookupPSBByEncoding(psbhintop);
1493 if (PSB)
1494 O << PSB->Name;
1495 else
1496 markup(O, Markup::Immediate) << '#' << formatImm(psbhintop);
1497}
1498
1499void AArch64InstPrinter::printBTIHintOp(const MCInst *MI, unsigned OpNum,
1500 const MCSubtargetInfo &STI,
1501 raw_ostream &O) {
1502 unsigned btihintop = MI->getOperand(OpNum).getImm() ^ 32;
1503 auto BTI = AArch64BTIHint::lookupBTIByEncoding(btihintop);
1504 if (BTI)
1505 O << BTI->Name;
1506 else
1507 markup(O, Markup::Immediate) << '#' << formatImm(btihintop);
1508}
1509
1510void AArch64InstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1511 const MCSubtargetInfo &STI,
1512 raw_ostream &O) {
1513 const MCOperand &MO = MI->getOperand(OpNum);
1514 float FPImm = MO.isDFPImm() ? bit_cast<double>(MO.getDFPImm())
1515 : AArch64_AM::getFPImmFloat(MO.getImm());
1516
1517 // 8 decimal places are enough to perfectly represent permitted floats.
1518 markup(O, Markup::Immediate) << format("#%.8f", FPImm);
1519}
1520
1521static MCRegister getNextVectorRegister(MCRegister Reg, unsigned Stride = 1) {
1522 while (Stride--) {
1523 switch (Reg.id()) {
1524 default:
1525 llvm_unreachable("Vector register expected!");
1526 case AArch64::Q0: Reg = AArch64::Q1; break;
1527 case AArch64::Q1: Reg = AArch64::Q2; break;
1528 case AArch64::Q2: Reg = AArch64::Q3; break;
1529 case AArch64::Q3: Reg = AArch64::Q4; break;
1530 case AArch64::Q4: Reg = AArch64::Q5; break;
1531 case AArch64::Q5: Reg = AArch64::Q6; break;
1532 case AArch64::Q6: Reg = AArch64::Q7; break;
1533 case AArch64::Q7: Reg = AArch64::Q8; break;
1534 case AArch64::Q8: Reg = AArch64::Q9; break;
1535 case AArch64::Q9: Reg = AArch64::Q10; break;
1536 case AArch64::Q10: Reg = AArch64::Q11; break;
1537 case AArch64::Q11: Reg = AArch64::Q12; break;
1538 case AArch64::Q12: Reg = AArch64::Q13; break;
1539 case AArch64::Q13: Reg = AArch64::Q14; break;
1540 case AArch64::Q14: Reg = AArch64::Q15; break;
1541 case AArch64::Q15: Reg = AArch64::Q16; break;
1542 case AArch64::Q16: Reg = AArch64::Q17; break;
1543 case AArch64::Q17: Reg = AArch64::Q18; break;
1544 case AArch64::Q18: Reg = AArch64::Q19; break;
1545 case AArch64::Q19: Reg = AArch64::Q20; break;
1546 case AArch64::Q20: Reg = AArch64::Q21; break;
1547 case AArch64::Q21: Reg = AArch64::Q22; break;
1548 case AArch64::Q22: Reg = AArch64::Q23; break;
1549 case AArch64::Q23: Reg = AArch64::Q24; break;
1550 case AArch64::Q24: Reg = AArch64::Q25; break;
1551 case AArch64::Q25: Reg = AArch64::Q26; break;
1552 case AArch64::Q26: Reg = AArch64::Q27; break;
1553 case AArch64::Q27: Reg = AArch64::Q28; break;
1554 case AArch64::Q28: Reg = AArch64::Q29; break;
1555 case AArch64::Q29: Reg = AArch64::Q30; break;
1556 case AArch64::Q30: Reg = AArch64::Q31; break;
1557 // Vector lists can wrap around.
1558 case AArch64::Q31:
1559 Reg = AArch64::Q0;
1560 break;
1561 case AArch64::Z0: Reg = AArch64::Z1; break;
1562 case AArch64::Z1: Reg = AArch64::Z2; break;
1563 case AArch64::Z2: Reg = AArch64::Z3; break;
1564 case AArch64::Z3: Reg = AArch64::Z4; break;
1565 case AArch64::Z4: Reg = AArch64::Z5; break;
1566 case AArch64::Z5: Reg = AArch64::Z6; break;
1567 case AArch64::Z6: Reg = AArch64::Z7; break;
1568 case AArch64::Z7: Reg = AArch64::Z8; break;
1569 case AArch64::Z8: Reg = AArch64::Z9; break;
1570 case AArch64::Z9: Reg = AArch64::Z10; break;
1571 case AArch64::Z10: Reg = AArch64::Z11; break;
1572 case AArch64::Z11: Reg = AArch64::Z12; break;
1573 case AArch64::Z12: Reg = AArch64::Z13; break;
1574 case AArch64::Z13: Reg = AArch64::Z14; break;
1575 case AArch64::Z14: Reg = AArch64::Z15; break;
1576 case AArch64::Z15: Reg = AArch64::Z16; break;
1577 case AArch64::Z16: Reg = AArch64::Z17; break;
1578 case AArch64::Z17: Reg = AArch64::Z18; break;
1579 case AArch64::Z18: Reg = AArch64::Z19; break;
1580 case AArch64::Z19: Reg = AArch64::Z20; break;
1581 case AArch64::Z20: Reg = AArch64::Z21; break;
1582 case AArch64::Z21: Reg = AArch64::Z22; break;
1583 case AArch64::Z22: Reg = AArch64::Z23; break;
1584 case AArch64::Z23: Reg = AArch64::Z24; break;
1585 case AArch64::Z24: Reg = AArch64::Z25; break;
1586 case AArch64::Z25: Reg = AArch64::Z26; break;
1587 case AArch64::Z26: Reg = AArch64::Z27; break;
1588 case AArch64::Z27: Reg = AArch64::Z28; break;
1589 case AArch64::Z28: Reg = AArch64::Z29; break;
1590 case AArch64::Z29: Reg = AArch64::Z30; break;
1591 case AArch64::Z30: Reg = AArch64::Z31; break;
1592 // Vector lists can wrap around.
1593 case AArch64::Z31:
1594 Reg = AArch64::Z0;
1595 break;
1596 case AArch64::P0: Reg = AArch64::P1; break;
1597 case AArch64::P1: Reg = AArch64::P2; break;
1598 case AArch64::P2: Reg = AArch64::P3; break;
1599 case AArch64::P3: Reg = AArch64::P4; break;
1600 case AArch64::P4: Reg = AArch64::P5; break;
1601 case AArch64::P5: Reg = AArch64::P6; break;
1602 case AArch64::P6: Reg = AArch64::P7; break;
1603 case AArch64::P7: Reg = AArch64::P8; break;
1604 case AArch64::P8: Reg = AArch64::P9; break;
1605 case AArch64::P9: Reg = AArch64::P10; break;
1606 case AArch64::P10: Reg = AArch64::P11; break;
1607 case AArch64::P11: Reg = AArch64::P12; break;
1608 case AArch64::P12: Reg = AArch64::P13; break;
1609 case AArch64::P13: Reg = AArch64::P14; break;
1610 case AArch64::P14: Reg = AArch64::P15; break;
1611 // Vector lists can wrap around.
1612 case AArch64::P15: Reg = AArch64::P0; break;
1613 }
1614 }
1615 return Reg;
1616}
1617
1618template<unsigned size>
1619void AArch64InstPrinter::printGPRSeqPairsClassOperand(const MCInst *MI,
1620 unsigned OpNum,
1621 const MCSubtargetInfo &STI,
1622 raw_ostream &O) {
1623 static_assert(size == 64 || size == 32,
1624 "Template parameter must be either 32 or 64");
1625 MCRegister Reg = MI->getOperand(OpNum).getReg();
1626
1627 unsigned Sube = (size == 32) ? AArch64::sube32 : AArch64::sube64;
1628 unsigned Subo = (size == 32) ? AArch64::subo32 : AArch64::subo64;
1629
1630 MCRegister Even = MRI.getSubReg(Reg, Sube);
1631 MCRegister Odd = MRI.getSubReg(Reg, Subo);
1632 printRegName(O, Even);
1633 O << ", ";
1634 printRegName(O, Odd);
1635}
1636
1637void AArch64InstPrinter::printMatrixTileList(const MCInst *MI, unsigned OpNum,
1638 const MCSubtargetInfo &STI,
1639 raw_ostream &O) {
1640 unsigned MaxRegs = 8;
1641 unsigned RegMask = MI->getOperand(OpNum).getImm();
1642
1643 unsigned NumRegs = 0;
1644 for (unsigned I = 0; I < MaxRegs; ++I)
1645 if ((RegMask & (1 << I)) != 0)
1646 ++NumRegs;
1647
1648 O << "{";
1649 unsigned Printed = 0;
1650 for (unsigned I = 0; I < MaxRegs; ++I) {
1651 unsigned Reg = RegMask & (1 << I);
1652 if (Reg == 0)
1653 continue;
1654 printRegName(O, AArch64::ZAD0 + I);
1655 if (Printed + 1 != NumRegs)
1656 O << ", ";
1657 ++Printed;
1658 }
1659 O << "}";
1660}
1661
1662void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
1663 const MCSubtargetInfo &STI,
1664 raw_ostream &O,
1665 StringRef LayoutSuffix) {
1666 MCRegister Reg = MI->getOperand(OpNum).getReg();
1667
1668 O << "{ ";
1669
1670 // Work out how many registers there are in the list (if there is an actual
1671 // list).
1672 unsigned NumRegs = 1;
1673 if (MRI.getRegClass(AArch64::DDRegClassID).contains(Reg) ||
1674 MRI.getRegClass(AArch64::ZPR2RegClassID).contains(Reg) ||
1675 MRI.getRegClass(AArch64::QQRegClassID).contains(Reg) ||
1676 MRI.getRegClass(AArch64::PPR2RegClassID).contains(Reg) ||
1677 MRI.getRegClass(AArch64::ZPR2StridedRegClassID).contains(Reg))
1678 NumRegs = 2;
1679 else if (MRI.getRegClass(AArch64::DDDRegClassID).contains(Reg) ||
1680 MRI.getRegClass(AArch64::ZPR3RegClassID).contains(Reg) ||
1681 MRI.getRegClass(AArch64::QQQRegClassID).contains(Reg))
1682 NumRegs = 3;
1683 else if (MRI.getRegClass(AArch64::DDDDRegClassID).contains(Reg) ||
1684 MRI.getRegClass(AArch64::ZPR4RegClassID).contains(Reg) ||
1685 MRI.getRegClass(AArch64::QQQQRegClassID).contains(Reg) ||
1686 MRI.getRegClass(AArch64::ZPR4StridedRegClassID).contains(Reg))
1687 NumRegs = 4;
1688
1689 unsigned Stride = 1;
1690 if (MRI.getRegClass(AArch64::ZPR2StridedRegClassID).contains(Reg))
1691 Stride = 8;
1692 else if (MRI.getRegClass(AArch64::ZPR4StridedRegClassID).contains(Reg))
1693 Stride = 4;
1694
1695 // Now forget about the list and find out what the first register is.
1696 if (MCRegister FirstReg = MRI.getSubReg(Reg, AArch64::dsub0))
1697 Reg = FirstReg;
1698 else if (MCRegister FirstReg = MRI.getSubReg(Reg, AArch64::qsub0))
1699 Reg = FirstReg;
1700 else if (MCRegister FirstReg = MRI.getSubReg(Reg, AArch64::zsub0))
1701 Reg = FirstReg;
1702 else if (MCRegister FirstReg = MRI.getSubReg(Reg, AArch64::psub0))
1703 Reg = FirstReg;
1704
1705 // If it's a D-reg, we need to promote it to the equivalent Q-reg before
1706 // printing (otherwise getRegisterName fails).
1707 if (MRI.getRegClass(AArch64::FPR64RegClassID).contains(Reg)) {
1708 const MCRegisterClass &FPR128RC =
1709 MRI.getRegClass(AArch64::FPR128RegClassID);
1710 Reg = MRI.getMatchingSuperReg(Reg, AArch64::dsub, &FPR128RC);
1711 }
1712
1713 if ((MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg) ||
1714 MRI.getRegClass(AArch64::PPRRegClassID).contains(Reg)) &&
1715 NumRegs > 1 && Stride == 1 &&
1716 // Do not print the range when the last register is lower than the first.
1717 // Because it is a wrap-around register.
1718 Reg < getNextVectorRegister(Reg, NumRegs - 1)) {
1719 printRegName(O, Reg);
1720 O << LayoutSuffix;
1721 if (NumRegs > 1) {
1722 // Set of two sve registers should be separated by ','
1723 StringRef split_char = NumRegs == 2 ? ", " : " - ";
1724 O << split_char;
1725 printRegName(O, (getNextVectorRegister(Reg, NumRegs - 1)));
1726 O << LayoutSuffix;
1727 }
1728 } else {
1729 for (unsigned i = 0; i < NumRegs;
1730 ++i, Reg = getNextVectorRegister(Reg, Stride)) {
1731 // wrap-around sve register
1732 if (MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg) ||
1733 MRI.getRegClass(AArch64::PPRRegClassID).contains(Reg))
1734 printRegName(O, Reg);
1735 else
1736 printRegName(O, Reg, AArch64::vreg);
1737 O << LayoutSuffix;
1738 if (i + 1 != NumRegs)
1739 O << ", ";
1740 }
1741 }
1742 O << " }";
1743}
1744
1745void
1746AArch64InstPrinter::printImplicitlyTypedVectorList(const MCInst *MI,
1747 unsigned OpNum,
1748 const MCSubtargetInfo &STI,
1749 raw_ostream &O) {
1750 printVectorList(MI, OpNum, STI, O, "");
1751}
1752
1753template <unsigned NumLanes, char LaneKind>
1754void AArch64InstPrinter::printTypedVectorList(const MCInst *MI, unsigned OpNum,
1755 const MCSubtargetInfo &STI,
1756 raw_ostream &O) {
1757 if (LaneKind == 0) {
1758 printVectorList(MI, OpNum, STI, O, "");
1759 return;
1760 }
1761 std::string Suffix(".");
1762 if (NumLanes)
1763 Suffix += itostr(NumLanes) + LaneKind;
1764 else
1765 Suffix += LaneKind;
1766
1767 printVectorList(MI, OpNum, STI, O, Suffix);
1768}
1769
1770template <unsigned Scale>
1771void AArch64InstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1772 const MCSubtargetInfo &STI,
1773 raw_ostream &O) {
1774 O << "[" << Scale * MI->getOperand(OpNum).getImm() << "]";
1775}
1776
1777template <unsigned Scale>
1778void AArch64InstPrinter::printMatrixIndex(const MCInst *MI, unsigned OpNum,
1779 const MCSubtargetInfo &STI,
1780 raw_ostream &O) {
1781 O << Scale * MI->getOperand(OpNum).getImm();
1782}
1783
1784void AArch64InstPrinter::printAlignedLabel(const MCInst *MI, uint64_t Address,
1785 unsigned OpNum,
1786 const MCSubtargetInfo &STI,
1787 raw_ostream &O) {
1788 // Do not print the numeric target address when symbolizing.
1789 if (SymbolizeOperands)
1790 return;
1791
1792 const MCOperand &Op = MI->getOperand(OpNum);
1793
1794 // If the label has already been resolved to an immediate offset (say, when
1795 // we're running the disassembler), just print the immediate.
1796 if (Op.isImm()) {
1797 int64_t Offset = Op.getImm() * 4;
1798 if (PrintBranchImmAsAddress)
1799 markup(O, Markup::Target) << formatHex(Address + Offset);
1800 else
1801 markup(O, Markup::Immediate) << "#" << formatImm(Offset);
1802 return;
1803 }
1804
1805 // If the branch target is simply an address then print it in hex.
1806 const MCConstantExpr *BranchTarget =
1807 dyn_cast<MCConstantExpr>(MI->getOperand(OpNum).getExpr());
1808 int64_t TargetAddress;
1809 if (BranchTarget && BranchTarget->evaluateAsAbsolute(TargetAddress)) {
1810 markup(O, Markup::Target) << formatHex((uint64_t)TargetAddress);
1811 } else {
1812 // Otherwise, just print the expression.
1813 MAI.printExpr(O, *MI->getOperand(OpNum).getExpr());
1814 }
1815}
1816
1817void AArch64InstPrinter::printAdrAdrpLabel(const MCInst *MI, uint64_t Address,
1818 unsigned OpNum,
1819 const MCSubtargetInfo &STI,
1820 raw_ostream &O) {
1821 // Do not print the numeric target address when symbolizing.
1822 // However, do print for ADRP, as this is typically used together with an ADD
1823 // or an immediate-offset ldr/str and the label is likely at the wrong point.
1824 if (SymbolizeOperands && MI->getOpcode() != AArch64::ADRP)
1825 return;
1826
1827 const MCOperand &Op = MI->getOperand(OpNum);
1828
1829 // If the label has already been resolved to an immediate offset (say, when
1830 // we're running the disassembler), just print the immediate.
1831 if (Op.isImm()) {
1832 int64_t Offset = Op.getImm();
1833 if (MI->getOpcode() == AArch64::ADRP) {
1834 Offset = Offset * 4096;
1835 Address = Address & -4096;
1836 }
1837 WithMarkup M = markup(O, Markup::Immediate);
1838 if (PrintBranchImmAsAddress)
1839 markup(O, Markup::Target) << formatHex(Address + Offset);
1840 else
1841 markup(O, Markup::Immediate) << "#" << Offset;
1842 return;
1843 }
1844
1845 // Otherwise, just print the expression.
1846 MAI.printExpr(O, *MI->getOperand(OpNum).getExpr());
1847}
1848
1849void AArch64InstPrinter::printBarrierOption(const MCInst *MI, unsigned OpNo,
1850 const MCSubtargetInfo &STI,
1851 raw_ostream &O) {
1852 unsigned Val = MI->getOperand(OpNo).getImm();
1853 unsigned Opcode = MI->getOpcode();
1854
1855 StringRef Name;
1856 if (Opcode == AArch64::ISB) {
1857 auto ISB = AArch64ISB::lookupISBByEncoding(Val);
1858 Name = ISB ? ISB->Name : "";
1859 } else if (Opcode == AArch64::TSB) {
1860 auto TSB = AArch64TSB::lookupTSBByEncoding(Val);
1861 Name = TSB ? TSB->Name : "";
1862 } else {
1863 auto DB = AArch64DB::lookupDBByEncoding(Val);
1864 Name = DB ? DB->Name : "";
1865 }
1866 if (!Name.empty())
1867 O << Name;
1868 else
1869 markup(O, Markup::Immediate) << "#" << Val;
1870}
1871
1872void AArch64InstPrinter::printBarriernXSOption(const MCInst *MI, unsigned OpNo,
1873 const MCSubtargetInfo &STI,
1874 raw_ostream &O) {
1875 unsigned Val = MI->getOperand(OpNo).getImm();
1876 assert(MI->getOpcode() == AArch64::DSBnXS);
1877
1878 StringRef Name;
1879 auto DB = AArch64DBnXS::lookupDBnXSByEncoding(Val);
1880 Name = DB ? DB->Name : "";
1881
1882 if (!Name.empty())
1883 O << Name;
1884 else
1885 markup(O, Markup::Immediate) << "#" << Val;
1886}
1887
1888static bool isValidSysReg(const AArch64SysReg::SysReg &Reg, bool Read,
1889 const MCSubtargetInfo &STI) {
1890 return (Read ? Reg.Readable : Reg.Writeable) &&
1891 Reg.haveFeatures(STI.getFeatureBits());
1892}
1893
1894// Looks up a system register either by encoding. Some system
1895// registers share the same encoding between different architectures,
1896// to work around this tablegen will return a range of registers with the same
1897// encodings. We need to check each register in the range to see if it valid.
1898static const AArch64SysReg::SysReg *lookupSysReg(unsigned Val, bool Read,
1899 const MCSubtargetInfo &STI) {
1900 auto Range = AArch64SysReg::lookupSysRegByEncoding(Val);
1901 for (auto &Reg : Range) {
1902 if (isValidSysReg(Reg, Read, STI))
1903 return &Reg;
1904 }
1905
1906 return nullptr;
1907}
1908
1909void AArch64InstPrinter::printMRSSystemRegister(const MCInst *MI, unsigned OpNo,
1910 const MCSubtargetInfo &STI,
1911 raw_ostream &O) {
1912 unsigned Val = MI->getOperand(OpNo).getImm();
1913
1914 // Horrible hack for the one register that has identical encodings but
1915 // different names in MSR and MRS. Because of this, one of MRS and MSR is
1916 // going to get the wrong entry
1917 if (Val == AArch64SysReg::DBGDTRRX_EL0) {
1918 O << "DBGDTRRX_EL0";
1919 return;
1920 }
1921
1922 // Horrible hack for two different registers having the same encoding.
1923 if (Val == AArch64SysReg::TRCEXTINSELR) {
1924 O << "TRCEXTINSELR";
1925 return;
1926 }
1927
1928 const AArch64SysReg::SysReg *Reg = lookupSysReg(Val, true /*Read*/, STI);
1929
1930 if (Reg)
1931 O << Reg->Name;
1932 else
1933 O << AArch64SysReg::genericRegisterString(Val);
1934}
1935
1936void AArch64InstPrinter::printMSRSystemRegister(const MCInst *MI, unsigned OpNo,
1937 const MCSubtargetInfo &STI,
1938 raw_ostream &O) {
1939 unsigned Val = MI->getOperand(OpNo).getImm();
1940
1941 // Horrible hack for the one register that has identical encodings but
1942 // different names in MSR and MRS. Because of this, one of MRS and MSR is
1943 // going to get the wrong entry
1944 if (Val == AArch64SysReg::DBGDTRTX_EL0) {
1945 O << "DBGDTRTX_EL0";
1946 return;
1947 }
1948
1949 // Horrible hack for two different registers having the same encoding.
1950 if (Val == AArch64SysReg::TRCEXTINSELR) {
1951 O << "TRCEXTINSELR";
1952 return;
1953 }
1954
1955 const AArch64SysReg::SysReg *Reg = lookupSysReg(Val, false /*Read*/, STI);
1956
1957 if (Reg)
1958 O << Reg->Name;
1959 else
1960 O << AArch64SysReg::genericRegisterString(Val);
1961}
1962
1963void AArch64InstPrinter::printSystemPStateField(const MCInst *MI, unsigned OpNo,
1964 const MCSubtargetInfo &STI,
1965 raw_ostream &O) {
1966 unsigned Val = MI->getOperand(OpNo).getImm();
1967
1968 auto PStateImm15 = AArch64PState::lookupPStateImm0_15ByEncoding(Val);
1969 auto PStateImm1 = AArch64PState::lookupPStateImm0_1ByEncoding(Val);
1970 if (PStateImm15 && PStateImm15->haveFeatures(STI.getFeatureBits()))
1971 O << PStateImm15->Name;
1972 else if (PStateImm1 && PStateImm1->haveFeatures(STI.getFeatureBits()))
1973 O << PStateImm1->Name;
1974 else
1975 O << "#" << formatImm(Val);
1976}
1977
1978void AArch64InstPrinter::printSIMDType10Operand(const MCInst *MI, unsigned OpNo,
1979 const MCSubtargetInfo &STI,
1980 raw_ostream &O) {
1981 unsigned RawVal = MI->getOperand(OpNo).getImm();
1982 uint64_t Val = AArch64_AM::decodeAdvSIMDModImmType10(RawVal);
1983 markup(O, Markup::Immediate) << format("#%#016llx", Val);
1984}
1985
1986template<int64_t Angle, int64_t Remainder>
1987void AArch64InstPrinter::printComplexRotationOp(const MCInst *MI, unsigned OpNo,
1988 const MCSubtargetInfo &STI,
1989 raw_ostream &O) {
1990 unsigned Val = MI->getOperand(OpNo).getImm();
1991 markup(O, Markup::Immediate) << "#" << (Val * Angle) + Remainder;
1992}
1993
1994void AArch64InstPrinter::printSVEPattern(const MCInst *MI, unsigned OpNum,
1995 const MCSubtargetInfo &STI,
1996 raw_ostream &O) {
1997 unsigned Val = MI->getOperand(OpNum).getImm();
1998 if (auto Pat = AArch64SVEPredPattern::lookupSVEPREDPATByEncoding(Val))
1999 O << Pat->Name;
2000 else
2001 markup(O, Markup::Immediate) << '#' << formatImm(Val);
2002}
2003
2004void AArch64InstPrinter::printSVEVecLenSpecifier(const MCInst *MI,
2005 unsigned OpNum,
2006 const MCSubtargetInfo &STI,
2007 raw_ostream &O) {
2008 unsigned Val = MI->getOperand(OpNum).getImm();
2009 // Pattern has only 1 bit
2010 if (Val > 1)
2011 llvm_unreachable("Invalid vector length specifier");
2012 if (auto Pat =
2013 AArch64SVEVecLenSpecifier::lookupSVEVECLENSPECIFIERByEncoding(Val))
2014 O << Pat->Name;
2015 else
2016 llvm_unreachable("Invalid vector length specifier");
2017}
2018
2019template <char suffix>
2020void AArch64InstPrinter::printSVERegOp(const MCInst *MI, unsigned OpNum,
2021 const MCSubtargetInfo &STI,
2022 raw_ostream &O) {
2023 switch (suffix) {
2024 case 0:
2025 case 'b':
2026 case 'h':
2027 case 's':
2028 case 'd':
2029 case 'q':
2030 break;
2031 default: llvm_unreachable("Invalid kind specifier.");
2032 }
2033
2034 MCRegister Reg = MI->getOperand(OpNum).getReg();
2035 printRegName(O, Reg);
2036 if (suffix != 0)
2037 O << '.' << suffix;
2038}
2039
2040template <typename T>
2041void AArch64InstPrinter::printImmSVE(T Value, raw_ostream &O) {
2042 std::make_unsigned_t<T> HexValue = Value;
2043
2044 if (getPrintImmHex())
2045 markup(O, Markup::Immediate) << '#' << formatHex((uint64_t)HexValue);
2046 else
2047 markup(O, Markup::Immediate) << '#' << formatDec(Value);
2048
2049 if (CommentStream) {
2050 // Do the opposite to that used for instruction operands.
2051 if (getPrintImmHex())
2052 *CommentStream << '=' << formatDec(HexValue) << '\n';
2053 else
2054 *CommentStream << '=' << formatHex((uint64_t)Value) << '\n';
2055 }
2056}
2057
2058template <typename T>
2059void AArch64InstPrinter::printImm8OptLsl(const MCInst *MI, unsigned OpNum,
2060 const MCSubtargetInfo &STI,
2061 raw_ostream &O) {
2062 unsigned UnscaledVal = MI->getOperand(OpNum).getImm();
2063 unsigned Shift = MI->getOperand(OpNum + 1).getImm();
2064 assert(AArch64_AM::getShiftType(Shift) == AArch64_AM::LSL &&
2065 "Unexpected shift type!");
2066
2067 // #0 lsl #8 is never pretty printed
2068 if ((UnscaledVal == 0) && (AArch64_AM::getShiftValue(Shift) != 0)) {
2069 markup(O, Markup::Immediate) << '#' << formatImm(UnscaledVal);
2070 printShifter(MI, OpNum + 1, STI, O);
2071 return;
2072 }
2073
2074 T Val;
2075 if (std::is_signed<T>())
2076 Val = (int8_t)UnscaledVal * (1 << AArch64_AM::getShiftValue(Shift));
2077 else
2078 Val = (uint8_t)UnscaledVal * (1 << AArch64_AM::getShiftValue(Shift));
2079
2080 printImmSVE(Val, O);
2081}
2082
2083template <typename T>
2084void AArch64InstPrinter::printSVELogicalImm(const MCInst *MI, unsigned OpNum,
2085 const MCSubtargetInfo &STI,
2086 raw_ostream &O) {
2087 typedef std::make_signed_t<T> SignedT;
2088 typedef std::make_unsigned_t<T> UnsignedT;
2089
2090 uint64_t Val = MI->getOperand(OpNum).getImm();
2091 UnsignedT PrintVal = AArch64_AM::decodeLogicalImmediate(Val, 64);
2092
2093 // Prefer the default format for 16bit values, hex otherwise.
2094 if ((int16_t)PrintVal == (SignedT)PrintVal)
2095 printImmSVE((T)PrintVal, O);
2096 else if ((uint16_t)PrintVal == PrintVal)
2097 printImmSVE(PrintVal, O);
2098 else
2099 markup(O, Markup::Immediate) << '#' << formatHex((uint64_t)PrintVal);
2100}
2101
2102template <int Width>
2103void AArch64InstPrinter::printZPRasFPR(const MCInst *MI, unsigned OpNum,
2104 const MCSubtargetInfo &STI,
2105 raw_ostream &O) {
2106 unsigned Base;
2107 switch (Width) {
2108 case 8: Base = AArch64::B0; break;
2109 case 16: Base = AArch64::H0; break;
2110 case 32: Base = AArch64::S0; break;
2111 case 64: Base = AArch64::D0; break;
2112 case 128: Base = AArch64::Q0; break;
2113 default:
2114 llvm_unreachable("Unsupported width");
2115 }
2116 MCRegister Reg = MI->getOperand(OpNum).getReg();
2117 printRegName(O, Reg - AArch64::Z0 + Base);
2118}
2119
2120template <unsigned ImmIs0, unsigned ImmIs1>
2121void AArch64InstPrinter::printExactFPImm(const MCInst *MI, unsigned OpNum,
2122 const MCSubtargetInfo &STI,
2123 raw_ostream &O) {
2124 auto *Imm0Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmIs0);
2125 auto *Imm1Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmIs1);
2126 unsigned Val = MI->getOperand(OpNum).getImm();
2127 markup(O, Markup::Immediate)
2128 << "#" << (Val ? Imm1Desc->Repr : Imm0Desc->Repr);
2129}
2130
2131void AArch64InstPrinter::printGPR64as32(const MCInst *MI, unsigned OpNum,
2132 const MCSubtargetInfo &STI,
2133 raw_ostream &O) {
2134 MCRegister Reg = MI->getOperand(OpNum).getReg();
2135 printRegName(O, getWRegFromXReg(Reg));
2136}
2137
2138void AArch64InstPrinter::printGPR64x8(const MCInst *MI, unsigned OpNum,
2139 const MCSubtargetInfo &STI,
2140 raw_ostream &O) {
2141 MCRegister Reg = MI->getOperand(OpNum).getReg();
2142 printRegName(O, MRI.getSubReg(Reg, AArch64::x8sub_0));
2143}
2144
2145void AArch64InstPrinter::printSyspXzrPair(const MCInst *MI, unsigned OpNum,
2146 const MCSubtargetInfo &STI,
2147 raw_ostream &O) {
2148 MCRegister Reg = MI->getOperand(OpNum).getReg();
2149 assert(Reg == AArch64::XZR &&
2150 "MC representation of SyspXzrPair should be XZR");
2151 O << getRegisterName(Reg) << ", " << getRegisterName(Reg);
2152}
2153
2154void AArch64InstPrinter::printPHintOp(const MCInst *MI, unsigned OpNum,
2155 const MCSubtargetInfo &STI,
2156 raw_ostream &O) {
2157 unsigned Op = MI->getOperand(OpNum).getImm();
2158 auto PH = AArch64PHint::lookupPHintByEncoding(Op);
2159 if (PH)
2160 O << PH->Name;
2161 else
2162 markup(O, Markup::Immediate) << '#' << formatImm(Op);
2163}
getNextVectorRegister
static MCRegister getNextVectorRegister(MCRegister Reg, unsigned Stride=1)
Definition AArch64InstPrinter.cpp:1521
lookupSysReg
static const AArch64SysReg::SysReg * lookupSysReg(unsigned Val, bool Read, const MCSubtargetInfo &STI)
Definition AArch64InstPrinter.cpp:1898
getLdStNInstrDesc
static const LdStNInstrDesc * getLdStNInstrDesc(unsigned Opcode)
Definition AArch64InstPrinter.cpp:768
LdStNInstInfo
static const LdStNInstrDesc LdStNInstInfo[]
Definition AArch64InstPrinter.cpp:425
isValidSysReg
static bool isValidSysReg(const AArch64SysReg::SysReg &Reg, bool Read, const MCSubtargetInfo &STI)
Definition AArch64InstPrinter.cpp:1888
isTblTbxInstruction
static bool isTblTbxInstruction(unsigned Opcode, StringRef &Layout, bool &IsTbx)
Definition AArch64InstPrinter.cpp:380
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
Info
Analysis containing CSE Info
Definition CSEInfo.cpp:27
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:110
RegName
#define RegName(no)
I
#define I(x, y, z)
Definition MD5.cpp:58
Reg
Register Reg
Definition MachineSink.cpp:2117
T
#define T
Definition Mips16ISelLowering.cpp:353
Range
ConstantRange Range(APInt(BitWidth, Low), APInt(BitWidth, High))
StringExtras.h
This file contains some functions that are useful when dealing with strings.
llvm::AArch64AppleInstPrinter::printInst
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
Definition AArch64InstPrinter.cpp:776
llvm::AArch64AppleInstPrinter::AArch64AppleInstPrinter
AArch64AppleInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
Definition AArch64InstPrinter.cpp:48
llvm::AArch64AppleInstPrinter::getRegisterName
static const char * getRegisterName(MCRegister Reg, unsigned AltIdx=AArch64::NoRegAltName)
llvm::AArch64AppleInstPrinter::getRegName
StringRef getRegName(MCRegister Reg) const override
Definition AArch64InstPrinter.cpp:835
llvm::AArch64InstPrinter::printMRSSystemRegister
void printMRSSystemRegister(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1909
llvm::AArch64InstPrinter::printImm
void printImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1171
llvm::AArch64InstPrinter::printAlignedLabel
void printAlignedLabel(const MCInst *MI, uint64_t Address, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1784
llvm::AArch64InstPrinter::printAMIndexedWB
void printAMIndexedWB(const MCInst *MI, unsigned OpNum, unsigned Scale, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1439
llvm::AArch64InstPrinter::printMatrix
void printMatrix(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1094
llvm::AArch64InstPrinter::printAdrAdrpLabel
void printAdrAdrpLabel(const MCInst *MI, uint64_t Address, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1817
llvm::AArch64InstPrinter::printPrefetchOp
void printPrefetchOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1468
llvm::AArch64InstPrinter::printZPRasFPR
void printZPRasFPR(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:2103
llvm::AArch64InstPrinter::printInstruction
virtual void printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
llvm::AArch64InstPrinter::printAMNoIndex
void printAMNoIndex(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1403
llvm::AArch64InstPrinter::printUImm12Offset
void printUImm12Offset(const MCInst *MI, unsigned OpNum, unsigned Scale, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1428
llvm::AArch64InstPrinter::printSVCROp
void printSVCROp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1146
llvm::AArch64InstPrinter::AArch64InstPrinter
AArch64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
Definition AArch64InstPrinter.cpp:43
llvm::AArch64InstPrinter::printCondCode
void printCondCode(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1389
llvm::AArch64InstPrinter::printBarriernXSOption
void printBarriernXSOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1872
llvm::AArch64InstPrinter::printSystemPStateField
void printSystemPStateField(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1963
llvm::AArch64InstPrinter::printShifter
void printShifter(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1259
llvm::AArch64InstPrinter::printPSBHintOp
void printPSBHintOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1488
llvm::AArch64InstPrinter::printGPR64x8
void printGPR64x8(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:2138
llvm::AArch64InstPrinter::printSIMDType10Operand
void printSIMDType10Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1978
llvm::AArch64InstPrinter::getRegName
virtual StringRef getRegName(MCRegister Reg) const
Definition AArch64InstPrinter.cpp:70
llvm::AArch64InstPrinter::printMemExtend
void printMemExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O, char SrcRegKind, unsigned Width)
Definition AArch64InstPrinter.cpp:1333
llvm::AArch64InstPrinter::printMatrixTileVector
void printMatrixTileVector(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1125
llvm::AArch64InstPrinter::printSysAlias
bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:889
llvm::AArch64InstPrinter::printSysCROperand
void printSysCROperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1219
llvm::AArch64InstPrinter::applyTargetSpecificCLOption
bool applyTargetSpecificCLOption(StringRef Opt) override
Customize the printer according to a command line option.
Definition AArch64InstPrinter.cpp:53
llvm::AArch64InstPrinter::printRPRFMOperand
void printRPRFMOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1455
llvm::AArch64InstPrinter::printVectorList
void printVectorList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O, StringRef LayoutSuffix)
Definition AArch64InstPrinter.cpp:1662
llvm::AArch64InstPrinter::printImplicitlyTypedVectorList
void printImplicitlyTypedVectorList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Print a list of vector registers where the type suffix is implicit (i.e.
Definition AArch64InstPrinter.cpp:1746
llvm::AArch64InstPrinter::printGPRSeqPairsClassOperand
void printGPRSeqPairsClassOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1619
llvm::AArch64InstPrinter::printExtendedRegister
void printExtendedRegister(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1279
llvm::AArch64InstPrinter::printRangePrefetchAlias
bool printRangePrefetchAlias(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O, StringRef Annot)
Definition AArch64InstPrinter.cpp:839
llvm::AArch64InstPrinter::printMSRSystemRegister
void printMSRSystemRegister(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1936
llvm::AArch64InstPrinter::printSVERegOp
void printSVERegOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:2020
llvm::AArch64InstPrinter::printPHintOp
void printPHintOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:2154
llvm::AArch64InstPrinter::printMatrixTile
void printMatrixTile(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1138
llvm::AArch64InstPrinter::printFPImmOperand
void printFPImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1510
llvm::AArch64InstPrinter::printMemExtendImpl
void printMemExtendImpl(bool SignExtend, bool DoShift, unsigned Width, char SrcRegKind, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1317
llvm::AArch64InstPrinter::printSVEVecLenSpecifier
void printSVEVecLenSpecifier(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:2004
llvm::AArch64InstPrinter::printBTIHintOp
void printBTIHintOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1499
llvm::AArch64InstPrinter::printSyspXzrPair
void printSyspXzrPair(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:2145
llvm::AArch64InstPrinter::printArithExtend
void printArithExtend(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1286
llvm::AArch64InstPrinter::printOperand
void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1157
llvm::AArch64InstPrinter::printAliasInstr
virtual bool printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
llvm::AArch64InstPrinter::printImmScale
void printImmScale(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1412
llvm::AArch64InstPrinter::printSImm
void printSImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1186
llvm::AArch64InstPrinter::printAddSubImm
void printAddSubImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1227
llvm::AArch64InstPrinter::printImmSVE
void printImmSVE(T Value, raw_ostream &O)
Definition AArch64InstPrinter.cpp:2041
llvm::AArch64InstPrinter::printShiftedRegister
void printShiftedRegister(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1272
llvm::AArch64InstPrinter::printComplexRotationOp
void printComplexRotationOp(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1987
llvm::AArch64InstPrinter::printGPR64as32
void printGPR64as32(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:2131
llvm::AArch64InstPrinter::printSyspAlias
bool printSyspAlias(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1033
llvm::AArch64InstPrinter::printRegName
void printRegName(raw_ostream &OS, MCRegister Reg) override
Print the assembler register name.
Definition AArch64InstPrinter.cpp:61
llvm::AArch64InstPrinter::printMatrixTileList
void printMatrixTileList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1637
llvm::AArch64InstPrinter::printMatrixIndex
void printMatrixIndex(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1778
llvm::AArch64InstPrinter::printImmRangeScale
void printImmRangeScale(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1420
llvm::AArch64InstPrinter::printTypedVectorList
void printTypedVectorList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1754
llvm::AArch64InstPrinter::printInst
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
Definition AArch64InstPrinter.cpp:74
llvm::AArch64InstPrinter::printLogicalImm
void printLogicalImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1250
llvm::AArch64InstPrinter::printSVEPattern
void printSVEPattern(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1994
llvm::AArch64InstPrinter::getRegisterName
static const char * getRegisterName(MCRegister Reg, unsigned AltIdx=AArch64::NoRegAltName)
llvm::AArch64InstPrinter::printVRegOperand
void printVRegOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1211
llvm::AArch64InstPrinter::printPostIncOperand
void printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1198
llvm::AArch64InstPrinter::printPredicateAsCounter
void printPredicateAsCounter(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1360
llvm::AArch64InstPrinter::printVectorIndex
void printVectorIndex(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1771
llvm::AArch64InstPrinter::printImm8OptLsl
void printImm8OptLsl(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:2059
llvm::AArch64InstPrinter::printRegWithShiftExtend
void printRegWithShiftExtend(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1342
llvm::AArch64InstPrinter::printImmHex
void printImmHex(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1178
llvm::AArch64InstPrinter::printInverseCondCode
void printInverseCondCode(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1396
llvm::AArch64InstPrinter::printExactFPImm
void printExactFPImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:2121
llvm::AArch64InstPrinter::printBarrierOption
void printBarrierOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1849
llvm::AArch64InstPrinter::printSVELogicalImm
void printSVELogicalImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:2084
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition MCAsmInfo.h:64
llvm::MCInstPrinter::markup
WithMarkup markup(raw_ostream &OS, Markup M)
Definition MCInstPrinter.cpp:227
llvm::MCInstPrinter::formatHex
format_object< int64_t > formatHex(int64_t Value) const
Definition MCInstPrinter.cpp:190
llvm::MCInstPrinter::MII
const MCInstrInfo & MII
Definition MCInstPrinter.h:53
llvm::MCInstPrinter::CommentStream
raw_ostream * CommentStream
A stream that comments can be emitted to if desired.
Definition MCInstPrinter.h:51
llvm::MCInstPrinter::getPrintImmHex
bool getPrintImmHex() const
Definition MCInstPrinter.h:163
llvm::MCInstPrinter::SymbolizeOperands
bool SymbolizeOperands
If true, symbolize branch target and memory reference operands.
Definition MCInstPrinter.h:78
llvm::MCInstPrinter::formatDec
format_object< int64_t > formatDec(int64_t Value) const
Utility functions to print decimal/hexadecimal values.
Definition MCInstPrinter.cpp:186
llvm::MCInstPrinter::MRI
const MCRegisterInfo & MRI
Definition MCInstPrinter.h:54
llvm::MCInstPrinter::printAnnotation
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
Definition MCInstPrinter.cpp:50
llvm::MCInstPrinter::MAI
const MCAsmInfo & MAI
Definition MCInstPrinter.h:52
llvm::MCInstPrinter::formatImm
format_object< int64_t > formatImm(int64_t Value) const
Utility function to print immediates in decimal or hex.
Definition MCInstPrinter.h:176
llvm::MCInstPrinter::PrintBranchImmAsAddress
bool PrintBranchImmAsAddress
If true, a branch immediate (e.g.
Definition MCInstPrinter.h:75
llvm::MCInstPrinter::MCInstPrinter
MCInstPrinter(const MCAsmInfo &mai, const MCInstrInfo &mii, const MCRegisterInfo &mri)
Definition MCInstPrinter.h:90
llvm::MCInstPrinter::PrintAliases
bool PrintAliases
True if we prefer aliases (e.g. nop) to raw mnemonics.
Definition MCInstPrinter.h:64
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition MCInst.h:188
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition MCInstrInfo.h:27
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition MCInst.h:40
llvm::MCOperand::getImm
int64_t getImm() const
Definition MCInst.h:84
llvm::MCOperand::isImm
bool isImm() const
Definition MCInst.h:66
llvm::MCOperand::isReg
bool isReg() const
Definition MCInst.h:65
llvm::MCOperand::getReg
MCRegister getReg() const
Returns the register number.
Definition MCInst.h:73
llvm::MCOperand::isDFPImm
bool isDFPImm() const
Definition MCInst.h:68
llvm::MCOperand::getExpr
const MCExpr * getExpr() const
Definition MCInst.h:118
llvm::MCOperand::getDFPImm
uint64_t getDFPImm() const
Definition MCInst.h:104
llvm::MCOperand::isExpr
bool isExpr() const
Definition MCInst.h:69
llvm::MCRegisterClass
MCRegisterClass - Base class of TargetRegisterClass.
Definition MCRegisterInfo.h:36
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition MCRegisterInfo.h:150
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition MCRegister.h:33
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition MCSubtargetInfo.h:77
llvm::MCSubtargetInfo::hasFeature
bool hasFeature(unsigned Feature) const
Definition MCSubtargetInfo.h:122
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition MCSubtargetInfo.h:115
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition StringRef.h:55
llvm::Value
LLVM Value Representation.
Definition Value.h:75
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition raw_ostream.h:53
uint16_t
uint64_t
uint8_t
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition ErrorHandling.h:164
llvm::AArch64CC::getCondCodeName
static const char * getCondCodeName(CondCode Code)
Definition AArch64BaseInfo.h:281
llvm::AArch64CC::getInvertedCondCode
static CondCode getInvertedCondCode(CondCode Code)
Definition AArch64BaseInfo.h:303
llvm::AArch64PHint::lookupPHintByEncoding
const PHint * lookupPHintByEncoding(uint16_t)
llvm::AArch64SysReg::genericRegisterString
std::string genericRegisterString(uint32_t Bits)
Definition AArch64BaseInfo.cpp:169
llvm::AArch64_AM::isMOVNMovAlias
static bool isMOVNMovAlias(uint64_t Value, int Shift, int RegWidth)
Definition AArch64AddressingModes.h:850
llvm::AArch64_AM::decodeLogicalImmediate
static uint64_t decodeLogicalImmediate(uint64_t val, unsigned regSize)
decodeLogicalImmediate - Decode a logical immediate value in the form "N:immr:imms" (where the immr a...
Definition AArch64AddressingModes.h:293
llvm::AArch64_AM::getShiftValue
static unsigned getShiftValue(unsigned Imm)
getShiftValue - Extract the shift value.
Definition AArch64AddressingModes.h:85
llvm::AArch64_AM::isAnyMOVWMovAlias
static bool isAnyMOVWMovAlias(uint64_t Value, int RegWidth)
Definition AArch64AddressingModes.h:862
llvm::AArch64_AM::getArithShiftValue
static unsigned getArithShiftValue(unsigned Imm)
getArithShiftValue - get the arithmetic shift value.
Definition AArch64AddressingModes.h:118
llvm::AArch64_AM::getFPImmFloat
static float getFPImmFloat(unsigned Imm)
Definition AArch64AddressingModes.h:343
llvm::AArch64_AM::isMOVZMovAlias
static bool isMOVZMovAlias(uint64_t Value, int Shift, int RegWidth)
Definition AArch64AddressingModes.h:839
llvm::AArch64_AM::ShiftExtendType
ShiftExtendType
Definition AArch64AddressingModes.h:32
llvm::AArch64_AM::LSL
@ LSL
Definition AArch64AddressingModes.h:34
llvm::AArch64_AM::UXTW
@ UXTW
Definition AArch64AddressingModes.h:42
llvm::AArch64_AM::UXTX
@ UXTX
Definition AArch64AddressingModes.h:43
llvm::AArch64_AM::getShiftExtendName
static const char * getShiftExtendName(AArch64_AM::ShiftExtendType ST)
getShiftName - Get the string encoding for the shift type.
Definition AArch64AddressingModes.h:52
llvm::AArch64_AM::decodeAdvSIMDModImmType10
static uint64_t decodeAdvSIMDModImmType10(uint8_t Imm)
Definition AArch64AddressingModes.h:663
llvm::AArch64_AM::getArithExtendType
static AArch64_AM::ShiftExtendType getArithExtendType(unsigned Imm)
Definition AArch64AddressingModes.h:138
llvm::AArch64_AM::getShiftType
static AArch64_AM::ShiftExtendType getShiftType(unsigned Imm)
getShiftType - Extract the shift type.
Definition AArch64AddressingModes.h:73
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition AddressRanges.h:18
llvm::Offset
@ Offset
Definition DWP.cpp:477
llvm::size
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition STLExtras.h:1685
llvm::dyn_cast
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
Definition Casting.h:649
llvm::transform
OutputIt transform(R &&Range, OutputIt d_first, UnaryFunction F)
Wrapper function around std::transform to apply a function to a range and store the result elsewhere.
Definition STLExtras.h:1970
llvm::Log2_32
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition MathExtras.h:336
llvm::getImm
MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)
Definition SPIRVUtils.cpp:976
llvm::atomicBarrierDroppedOnZero
static bool atomicBarrierDroppedOnZero(unsigned Opcode)
Definition AArch64BaseInfo.h:207
llvm::format
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition Format.h:126
llvm::bit_cast
To bit_cast(const From &from) noexcept
Definition bit.h:90
llvm::Op
DWARFExpression::Operation Op
Definition DWARFExpressionPrinter.cpp:22
llvm::getWRegFromXReg
static MCRegister getWRegFromXReg(MCRegister Reg)
Definition AArch64BaseInfo.h:30
llvm::BitWidth
constexpr unsigned BitWidth
Definition BitmaskEnum.h:223
llvm::SignExtend64
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition MathExtras.h:577
llvm::maskTrailingOnes
constexpr T maskTrailingOnes(unsigned N)
Create a bitmask with the N right-most bits set to 1, and all other bits set to 0.
Definition MathExtras.h:86
llvm::itostr
std::string itostr(int64_t X)
Definition StringExtras.h:337
raw_ostream.h
llvm::SysAlias::haveFeatures
bool haveFeatures(FeatureBitset ActiveFeatures) const
Definition AArch64BaseInfo.h:396
llvm::SysAlias::Name
const char * Name
Definition AArch64BaseInfo.h:388
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