LLVM 22.0.0git
AMDGPUELFObjectWriter.cpp
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1//===- AMDGPUELFObjectWriter.cpp - AMDGPU ELF Writer ----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "AMDGPUFixupKinds.h"
10#include "AMDGPUMCTargetDesc.h"
12#include "llvm/MC/MCContext.h"
14#include "llvm/MC/MCValue.h"
15
16using namespace llvm;
17
18namespace {
19
20class AMDGPUELFObjectWriter : public MCELFObjectTargetWriter {
21public:
22 AMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI, bool HasRelocationAddend);
23
24protected:
25 unsigned getRelocType(const MCFixup &, const MCValue &,
26 bool IsPCRel) const override;
27};
28
29
30} // end anonymous namespace
31
32AMDGPUELFObjectWriter::AMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI,
33 bool HasRelocationAddend)
34 : MCELFObjectTargetWriter(Is64Bit, OSABI, ELF::EM_AMDGPU,
35 HasRelocationAddend) {}
36
37unsigned AMDGPUELFObjectWriter::getRelocType(const MCFixup &Fixup,
38 const MCValue &Target,
39 bool IsPCRel) const {
40 if (const auto *SymA = Target.getAddSym()) {
41 // SCRATCH_RSRC_DWORD[01] is a special global variable that represents
42 // the scratch buffer.
43 if (SymA->getName() == "SCRATCH_RSRC_DWORD0" ||
44 SymA->getName() == "SCRATCH_RSRC_DWORD1")
45 return ELF::R_AMDGPU_ABS32_LO;
46 }
47
48 switch (AMDGPUMCExpr::Specifier(Target.getSpecifier())) {
49 default:
50 break;
52 return ELF::R_AMDGPU_GOTPCREL;
54 return ELF::R_AMDGPU_GOTPCREL32_LO;
56 return ELF::R_AMDGPU_GOTPCREL32_HI;
58 return ELF::R_AMDGPU_REL32_LO;
60 return ELF::R_AMDGPU_REL32_HI;
62 return ELF::R_AMDGPU_REL64;
64 return ELF::R_AMDGPU_ABS32_LO;
66 return ELF::R_AMDGPU_ABS32_HI;
68 return ELF::R_AMDGPU_ABS64;
69 }
70
71 MCFixupKind Kind = Fixup.getKind();
72 switch (Kind) {
73 default: break;
74 case FK_Data_4:
75 case FK_SecRel_4:
76 return IsPCRel ? ELF::R_AMDGPU_REL32 : ELF::R_AMDGPU_ABS32;
77 case FK_Data_8:
78 return IsPCRel ? ELF::R_AMDGPU_REL64 : ELF::R_AMDGPU_ABS64;
79 }
80
81 if (Fixup.getKind() == AMDGPU::fixup_si_sopp_br) {
82 const auto *SymA = Target.getAddSym();
83 assert(SymA);
84
85 if (SymA->isUndefined()) {
86 reportError(Fixup.getLoc(),
87 Twine("undefined label '") + SymA->getName() + "'");
88 return ELF::R_AMDGPU_NONE;
89 }
90 return ELF::R_AMDGPU_REL16;
91 }
92
93 llvm_unreachable("unhandled relocation type");
94}
95
96std::unique_ptr<MCObjectTargetWriter>
98 bool HasRelocationAddend) {
99 return std::make_unique<AMDGPUELFObjectWriter>(Is64Bit, OSABI,
100 HasRelocationAddend);
101}
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
Provides AMDGPU specific target descriptions.
static Error reportError(StringRef Message)
PowerPC TLS Dynamic Call Fixup
virtual unsigned getRelocType(const MCFixup &Fixup, const MCValue &Target, bool IsPCRel) const =0
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:61
Target - Wrapper for Target specific information.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:82
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ fixup_si_sopp_br
16-bit PC relative fixup for SOPP branch instructions.
@ EM_AMDGPU
Definition: ELF.h:321
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ FK_Data_8
A eight-byte fixup.
Definition: MCFixup.h:37
@ FK_Data_4
A four-byte fixup.
Definition: MCFixup.h:36
@ FK_SecRel_4
A four-byte section relative fixup.
Definition: MCFixup.h:41
std::unique_ptr< MCObjectTargetWriter > createAMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI, bool HasRelocationAddend)