AMDGPULegalizerInfo.cpp File Reference

This file implements the targeting of the Machinelegalizer class for AMDGPU. More...

#include "AMDGPULegalizerInfo.h"
#include "AMDGPU.h"
#include "AMDGPUGlobalISelUtils.h"
#include "AMDGPUInstrInfo.h"
#include "AMDGPUMemoryUtils.h"
#include "AMDGPUTargetMachine.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "SIInstrInfo.h"
#include "SIMachineFunctionInfo.h"
#include "SIRegisterInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
#include "llvm/ADT/ScopeExit.h"
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/GlobalISel/Utils.h"
#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "llvm/IR/IntrinsicsR600.h"

Go to the source code of this file.

Macros
#define	DEBUG_TYPE   "amdgpu-legalinfo"

Functions
static LLT	getPow2VectorType (LLT Ty)
static LLT	getPow2ScalarType (LLT Ty)
static LegalityPredicate	isSmallOddVector (unsigned TypeIdx)
static LegalityPredicate	sizeIsMultipleOf32 (unsigned TypeIdx)
static LegalityPredicate	isWideVec16 (unsigned TypeIdx)
static LegalizeMutation	oneMoreElement (unsigned TypeIdx)
static LegalizeMutation	fewerEltsToSize64Vector (unsigned TypeIdx)
static LegalizeMutation	moreEltsToNext32Bit (unsigned TypeIdx)
static LegalizeMutation	getScalarTypeFromMemDesc (unsigned TypeIdx)
static LegalizeMutation	moreElementsToNextExistingRegClass (unsigned TypeIdx)
static LLT	getBufferRsrcScalarType (const LLT Ty)
static LLT	getBufferRsrcRegisterType (const LLT Ty)
static LLT	getBitcastRegisterType (const LLT Ty)
static LegalizeMutation	bitcastToRegisterType (unsigned TypeIdx)
static LegalizeMutation	bitcastToVectorElement32 (unsigned TypeIdx)
static LegalityPredicate	vectorSmallerThan (unsigned TypeIdx, unsigned Size)
static LegalityPredicate	vectorWiderThan (unsigned TypeIdx, unsigned Size)
static LegalityPredicate	numElementsNotEven (unsigned TypeIdx)
static bool	isRegisterSize (const GCNSubtarget &ST, unsigned Size)
static bool	isRegisterVectorElementType (LLT EltTy)
static bool	isRegisterVectorType (LLT Ty)
static bool	isRegisterType (const GCNSubtarget &ST, LLT Ty)
static LegalityPredicate	isRegisterType (const GCNSubtarget &ST, unsigned TypeIdx)
static LegalityPredicate	isIllegalRegisterType (const GCNSubtarget &ST, unsigned TypeIdx)
static LegalityPredicate	elementTypeIsLegal (unsigned TypeIdx)
static bool	isRegisterClassType (const GCNSubtarget &ST, LLT Ty)
static LegalityPredicate	isRegisterClassType (const GCNSubtarget &ST, unsigned TypeIdx)
static LegalityPredicate	isWideScalarExtLoadTruncStore (unsigned TypeIdx)
static LegalityPredicate	isTruncStoreToSizePowerOf2 (unsigned TypeIdx)
static unsigned	maxSizeForAddrSpace (const GCNSubtarget &ST, unsigned AS, bool IsLoad, bool IsAtomic)
static bool	isLoadStoreSizeLegal (const GCNSubtarget &ST, const LegalityQuery &Query)
static bool	hasBufferRsrcWorkaround (const LLT Ty)
static bool	loadStoreBitcastWorkaround (const LLT Ty)
static bool	isLoadStoreLegal (const GCNSubtarget &ST, const LegalityQuery &Query)
static bool	shouldBitcastLoadStoreType (const GCNSubtarget &ST, const LLT Ty, const LLT MemTy)
	Return true if a load or store of the type should be lowered with a bitcast to a different type.
static bool	shouldWidenLoad (const GCNSubtarget &ST, LLT MemoryTy, uint64_t AlignInBits, unsigned AddrSpace, unsigned Opcode)
	Return true if we should legalize a load by widening an odd sized memory access up to the alignment.
static bool	shouldWidenLoad (const GCNSubtarget &ST, const LegalityQuery &Query, unsigned Opcode)
static LLT	castBufferRsrcFromV4I32 (MachineInstr &MI, MachineIRBuilder &B, MachineRegisterInfo &MRI, unsigned Idx)
	Mutates IR (typicaly a load instruction) to use a <4 x s32> as the initial type of the operand idx and then to transform it to a p8 via bitcasts and inttoptr.
static Register	castBufferRsrcToV4I32 (Register Pointer, MachineIRBuilder &B)
	Cast a buffer resource (an address space 8 pointer) into a 4xi32, which is the form in which the value must be in order to be passed to the low-level representations used for MUBUF/MTBUF intrinsics.
static void	castBufferRsrcArgToV4I32 (MachineInstr &MI, MachineIRBuilder &B, unsigned Idx)
static bool	isKnownNonNull (Register Val, MachineRegisterInfo &MRI, const AMDGPUTargetMachine &TM, unsigned AddrSpace)
	Return true if the value is a known valid address, such that a null check is not necessary.
static MachineInstrBuilder	extractF64Exponent (Register Hi, MachineIRBuilder &B)
static LLT	widenToNextPowerOf2 (LLT Ty)
static bool	valueIsKnownNeverF32Denorm (const MachineRegisterInfo &MRI, Register Src)
	Return true if it's known that Src can never be an f32 denormal value.
static bool	allowApproxFunc (const MachineFunction &MF, unsigned Flags)
static bool	needsDenormHandlingF32 (const MachineFunction &MF, Register Src, unsigned Flags)
static Register	getMad (MachineIRBuilder &B, LLT Ty, Register X, Register Y, Register Z, unsigned Flags)
static Register	stripAnySourceMods (Register OrigSrc, MachineRegisterInfo &MRI)
static bool	isNot (const MachineRegisterInfo &MRI, const MachineInstr &MI)
static MachineInstr *	verifyCFIntrinsic (MachineInstr &MI, MachineRegisterInfo &MRI, MachineInstr *&Br, MachineBasicBlock *&UncondBrTarget, bool &Negated)
static bool	replaceWithConstant (MachineIRBuilder &B, MachineInstr &MI, int64_t C)
static std::pair< Register, Register >	emitReciprocalU64 (MachineIRBuilder &B, Register Val)
static void	toggleSPDenormMode (bool Enable, MachineIRBuilder &B, const GCNSubtarget &ST, SIModeRegisterDefaults Mode)
static void	buildBufferLoad (unsigned Opc, Register LoadDstReg, Register RSrc, Register VIndex, Register VOffset, Register SOffset, unsigned ImmOffset, unsigned Format, unsigned AuxiliaryData, MachineMemOperand *MMO, bool IsTyped, bool HasVIndex, MachineIRBuilder &B)
static unsigned	getBufferAtomicPseudo (Intrinsic::ID IntrID)
static void	packImage16bitOpsToDwords (MachineIRBuilder &B, MachineInstr &MI, SmallVectorImpl< Register > &PackedAddrs, unsigned ArgOffset, const AMDGPU::ImageDimIntrinsicInfo *Intr, bool IsA16, bool IsG16)
	Turn a set of s16 typed registers in AddrRegs into a dword sized vector with s16 typed elements.
static void	convertImageAddrToPacked (MachineIRBuilder &B, MachineInstr &MI, int DimIdx, int NumVAddrs)
	Convert from separate vaddr components to a single vector address register, and replace the remaining operands with $noreg.

Variables
static cl::opt< bool >	EnableNewLegality ("amdgpu-global-isel-new-legality", cl::desc("Use GlobalISel desired legality, rather than try to use" "rules compatible with selection patterns"), cl::init(false), cl::ReallyHidden)
static constexpr unsigned	MaxRegisterSize = 1024
constexpr LLT	S1 = LLT::scalar(1)
constexpr LLT	S8 = LLT::scalar(8)
constexpr LLT	S16 = LLT::scalar(16)
constexpr LLT	S32 = LLT::scalar(32)
constexpr LLT	F32 = LLT::float32()
constexpr LLT	S64 = LLT::scalar(64)
constexpr LLT	F64 = LLT::float64()
constexpr LLT	S96 = LLT::scalar(96)
constexpr LLT	S128 = LLT::scalar(128)
constexpr LLT	S160 = LLT::scalar(160)
constexpr LLT	S192 = LLT::scalar(192)
constexpr LLT	S224 = LLT::scalar(224)
constexpr LLT	S256 = LLT::scalar(256)
constexpr LLT	S512 = LLT::scalar(512)
constexpr LLT	S1024 = LLT::scalar(1024)
constexpr LLT	MaxScalar = LLT::scalar(MaxRegisterSize)
constexpr LLT	V2S8 = LLT::fixed_vector(2, 8)
constexpr LLT	V2S16 = LLT::fixed_vector(2, 16)
constexpr LLT	V4S16 = LLT::fixed_vector(4, 16)
constexpr LLT	V6S16 = LLT::fixed_vector(6, 16)
constexpr LLT	V8S16 = LLT::fixed_vector(8, 16)
constexpr LLT	V10S16 = LLT::fixed_vector(10, 16)
constexpr LLT	V12S16 = LLT::fixed_vector(12, 16)
constexpr LLT	V16S16 = LLT::fixed_vector(16, 16)
constexpr LLT	V2F16 = LLT::fixed_vector(2, LLT::float16())
constexpr LLT	V2BF16 = V2F16
constexpr LLT	V2S32 = LLT::fixed_vector(2, 32)
constexpr LLT	V3S32 = LLT::fixed_vector(3, 32)
constexpr LLT	V4S32 = LLT::fixed_vector(4, 32)
constexpr LLT	V5S32 = LLT::fixed_vector(5, 32)
constexpr LLT	V6S32 = LLT::fixed_vector(6, 32)
constexpr LLT	V7S32 = LLT::fixed_vector(7, 32)
constexpr LLT	V8S32 = LLT::fixed_vector(8, 32)
constexpr LLT	V9S32 = LLT::fixed_vector(9, 32)
constexpr LLT	V10S32 = LLT::fixed_vector(10, 32)
constexpr LLT	V11S32 = LLT::fixed_vector(11, 32)
constexpr LLT	V12S32 = LLT::fixed_vector(12, 32)
constexpr LLT	V16S32 = LLT::fixed_vector(16, 32)
constexpr LLT	V32S32 = LLT::fixed_vector(32, 32)
constexpr LLT	V2S64 = LLT::fixed_vector(2, 64)
constexpr LLT	V3S64 = LLT::fixed_vector(3, 64)
constexpr LLT	V4S64 = LLT::fixed_vector(4, 64)
constexpr LLT	V5S64 = LLT::fixed_vector(5, 64)
constexpr LLT	V6S64 = LLT::fixed_vector(6, 64)
constexpr LLT	V7S64 = LLT::fixed_vector(7, 64)
constexpr LLT	V8S64 = LLT::fixed_vector(8, 64)
constexpr LLT	V16S64 = LLT::fixed_vector(16, 64)
constexpr LLT	V2S128 = LLT::fixed_vector(2, 128)
constexpr LLT	V4S128 = LLT::fixed_vector(4, 128)
constexpr std::initializer_list< LLT >	AllScalarTypes
constexpr std::initializer_list< LLT >	AllS16Vectors
constexpr std::initializer_list< LLT >	AllS32Vectors
constexpr std::initializer_list< LLT >	AllS64Vectors
constexpr std::initializer_list< LLT >	AllVectors
static constexpr unsigned	SPDenormModeBitField
static constexpr unsigned	FPEnvModeBitField
static constexpr unsigned	FPEnvTrapBitField

Detailed Description

This file implements the targeting of the Machinelegalizer class for AMDGPU.

Todo:

This should be generated by TableGen.

Definition in file AMDGPULegalizerInfo.cpp.

Macro Definition Documentation

DEBUG_TYPE

#define DEBUG_TYPE   "amdgpu-legalinfo"

Definition at line 38 of file AMDGPULegalizerInfo.cpp.

Function Documentation

allowApproxFunc()

static bool allowApproxFunc ( const MachineFunction &  MF, unsigned  Flags  )

static

Definition at line 3416 of file AMDGPULegalizerInfo.cpp.

References llvm::MachineInstr::FmAfn.

Referenced by llvm::AMDGPULegalizerInfo::legalizeFExp(), and llvm::AMDGPULegalizerInfo::legalizeFSQRTF32().

bitcastToRegisterType()

static LegalizeMutation bitcastToRegisterType ( unsigned  TypeIdx )

static

Definition at line 197 of file AMDGPULegalizerInfo.cpp.

References getBitcastRegisterType().

bitcastToVectorElement32()

static LegalizeMutation bitcastToVectorElement32 ( unsigned  TypeIdx )

static

Definition at line 204 of file AMDGPULegalizerInfo.cpp.

References assert(), llvm::ElementCount::getFixed(), llvm::LLT::getSizeInBits(), llvm::LLT::scalarOrVector(), and Size.

buildBufferLoad()

static void buildBufferLoad ( unsigned  Opc, Register  LoadDstReg, Register  RSrc, Register  VIndex, Register  VOffset, Register  SOffset, unsigned  ImmOffset, unsigned  Format, unsigned  AuxiliaryData, MachineMemOperand *  MMO, bool  IsTyped, bool  HasVIndex, MachineIRBuilder &  B  )

static

Definition at line 6126 of file AMDGPULegalizerInfo.cpp.

References B, llvm::Format, and Opc.

Referenced by llvm::AMDGPULegalizerInfo::legalizeBufferLoad().

castBufferRsrcArgToV4I32()

static void castBufferRsrcArgToV4I32 ( MachineInstr &  MI, MachineIRBuilder &  B, unsigned  Idx  )

static

Definition at line 676 of file AMDGPULegalizerInfo.cpp.

References B, castBufferRsrcToV4I32(), llvm::MachineOperand::getReg(), hasBufferRsrcWorkaround(), Idx, MI, and llvm::MachineOperand::setReg().

Referenced by llvm::AMDGPULegalizerInfo::legalizeBufferAtomic(), llvm::AMDGPULegalizerInfo::legalizeBufferLoad(), llvm::AMDGPULegalizerInfo::legalizeBufferStore(), llvm::AMDGPULegalizerInfo::legalizeSBufferPrefetch(), and llvm::AMDGPULegalizerInfo::legalizeStore().

castBufferRsrcFromV4I32()

static LLT castBufferRsrcFromV4I32 ( MachineInstr &  MI, MachineIRBuilder &  B, MachineRegisterInfo &  MRI, unsigned  Idx  )

static

Mutates IR (typicaly a load instruction) to use a <4 x s32> as the initial type of the operand idx and then to transform it to a p8 via bitcasts and inttoptr.

In addition, handle vectors of p8. Returns the new type.

Definition at line 616 of file AMDGPULegalizerInfo.cpp.

References B, getBufferRsrcRegisterType(), getBufferRsrcScalarType(), llvm::MachineOperand::getReg(), hasBufferRsrcWorkaround(), I, Idx, MI, MRI, S32, llvm::LLT::scalar(), and llvm::MachineOperand::setReg().

Referenced by llvm::AMDGPULegalizerInfo::legalizeBufferLoad(), llvm::AMDGPULegalizerInfo::legalizeLoad(), and llvm::AMDGPULegalizerInfo::legalizeSBufferLoad().

castBufferRsrcToV4I32()

static Register castBufferRsrcToV4I32 ( Register  Pointer, MachineIRBuilder &  B  )

static

Cast a buffer resource (an address space 8 pointer) into a 4xi32, which is the form in which the value must be in order to be passed to the low-level representations used for MUBUF/MTBUF intrinsics.

This is a hack, which is needed in order to account for the fact that we can't define a register class for s128 without breaking SelectionDAG.

Definition at line 657 of file AMDGPULegalizerInfo.cpp.

References B, getBufferRsrcRegisterType(), getBufferRsrcScalarType(), I, MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::LLT::scalar().

Referenced by castBufferRsrcArgToV4I32(), and llvm::AMDGPULegalizerInfo::fixStoreSourceType().

convertImageAddrToPacked()

static void convertImageAddrToPacked ( MachineIRBuilder &  B, MachineInstr &  MI, int  DimIdx, int  NumVAddrs  )

static

Convert from separate vaddr components to a single vector address register, and replace the remaining operands with $noreg.

Definition at line 6526 of file AMDGPULegalizerInfo.cpp.

References assert(), B, llvm::LLT::fixed_vector(), llvm::SrcOp::getReg(), I, MI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), S32, llvm::LLT::scalar(), and llvm::SmallVectorBase< Size_T >::size().

Referenced by llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic().

elementTypeIsLegal()

static LegalityPredicate elementTypeIsLegal ( unsigned  TypeIdx )

static

Definition at line 284 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getElementType(), llvm::LLT::getSizeInBits(), llvm::LLT::isVector(), and llvm::LLT::scalar().

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().

emitReciprocalU64()

static std::pair< Register, Register > emitReciprocalU64 ( MachineIRBuilder &  B, Register  Val  )

static

Definition at line 4688 of file AMDGPULegalizerInfo.cpp.

References B, S32, and llvm::LLT::scalar().

Referenced by llvm::AMDGPULegalizerInfo::legalizeUnsignedDIV_REM64Impl().

extractF64Exponent()

static MachineInstrBuilder extractF64Exponent ( Register  Hi, MachineIRBuilder &  B  )

static

Definition at line 2634 of file AMDGPULegalizerInfo.cpp.

References B, llvm::Hi, S32, and llvm::LLT::scalar().

fewerEltsToSize64Vector()

static LegalizeMutation fewerEltsToSize64Vector ( unsigned  TypeIdx )

static

Definition at line 111 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getElementType(), llvm::ElementCount::getFixed(), llvm::LLT::getNumElements(), llvm::LLT::getSizeInBits(), llvm::LLT::scalarOrVector(), and Size.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().

getBitcastRegisterType()

static LLT getBitcastRegisterType ( const LLT  Ty )

static

Definition at line 185 of file AMDGPULegalizerInfo.cpp.

References llvm::ElementCount::getFixed(), llvm::LLT::getSizeInBits(), llvm::LLT::scalar(), llvm::LLT::scalarOrVector(), and Size.

Referenced by bitcastToRegisterType(), llvm::AMDGPULegalizerInfo::fixStoreSourceType(), llvm::AMDGPULegalizerInfo::legalizeBufferLoad(), and llvm::AMDGPULegalizerInfo::legalizeSBufferLoad().

getBufferAtomicPseudo()

static unsigned getBufferAtomicPseudo ( Intrinsic::ID  IntrID )

static

Definition at line 6308 of file AMDGPULegalizerInfo.cpp.

References llvm_unreachable.

Referenced by llvm::AMDGPULegalizerInfo::legalizeBufferAtomic().

getBufferRsrcRegisterType()

static LLT getBufferRsrcRegisterType ( const LLT  Ty )

static

Definition at line 178 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::fixed_vector(), llvm::LLT::getElementCount(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), llvm::LLT::isVector(), and llvm::LLT::scalar().

Referenced by castBufferRsrcFromV4I32(), and castBufferRsrcToV4I32().

getBufferRsrcScalarType()

static LLT getBufferRsrcScalarType ( const LLT  Ty )

static

Definition at line 171 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getElementCount(), llvm::LLT::isVector(), llvm::LLT::scalar(), and llvm::LLT::vector().

Referenced by castBufferRsrcFromV4I32(), and castBufferRsrcToV4I32().

getMad()

static Register getMad ( MachineIRBuilder &  B, LLT  Ty, Register  X, Register  Y, Register  Z, unsigned  Flags  )

static

Definition at line 3498 of file AMDGPULegalizerInfo.cpp.

References B, llvm::FMul, X, and Y.

getPow2ScalarType()

static LLT getPow2ScalarType ( LLT  Ty )

static

Definition at line 64 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getSizeInBits(), llvm::Log2_32_Ceil(), and llvm::LLT::scalar().

Referenced by llvm::AMDGPULegalizerInfo::legalizeSBufferLoad().

getPow2VectorType()

static LLT getPow2VectorType ( LLT  Ty )

static

Definition at line 57 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::changeElementCount(), llvm::ElementCount::getFixed(), llvm::LLT::getNumElements(), and llvm::Log2_32_Ceil().

Referenced by llvm::AMDGPULegalizerInfo::legalizeSBufferLoad().

getScalarTypeFromMemDesc()

static LegalizeMutation getScalarTypeFromMemDesc ( unsigned  TypeIdx )

static

Definition at line 142 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::scalar().

hasBufferRsrcWorkaround()

static bool hasBufferRsrcWorkaround ( const LLT  Ty )

static

Definition at line 509 of file AMDGPULegalizerInfo.cpp.

References llvm::AMDGPUAS::BUFFER_RESOURCE, llvm::LLT::getAddressSpace(), llvm::LLT::getElementType(), hasBufferRsrcWorkaround(), llvm::LLT::isPointer(), and llvm::LLT::isVector().

Referenced by castBufferRsrcArgToV4I32(), castBufferRsrcFromV4I32(), llvm::AMDGPULegalizerInfo::fixStoreSourceType(), hasBufferRsrcWorkaround(), isLoadStoreLegal(), llvm::AMDGPULegalizerInfo::legalizeBufferLoad(), llvm::AMDGPULegalizerInfo::legalizeLoad(), llvm::AMDGPULegalizerInfo::legalizeSBufferLoad(), llvm::AMDGPULegalizerInfo::legalizeStore(), and loadStoreBitcastWorkaround().

isIllegalRegisterType()

static LegalityPredicate isIllegalRegisterType ( const GCNSubtarget &  ST, unsigned  TypeIdx  )

static

Definition at line 275 of file AMDGPULegalizerInfo.cpp.

References llvm::SIRegisterInfo::getSGPRClassForBitWidth(), llvm::LLT::getSizeInBits(), and isRegisterType().

isKnownNonNull()

static bool isKnownNonNull ( Register  Val, MachineRegisterInfo &  MRI, const AMDGPUTargetMachine &  TM, unsigned  AddrSpace  )

static

Return true if the value is a known valid address, such that a null check is not necessary.

Definition at line 2368 of file AMDGPULegalizerInfo.cpp.

References llvm::ConstantInt::getSExtValue(), and MRI.

Referenced by llvm::AMDGPULegalizerInfo::legalizeAddrSpaceCast().

isLoadStoreLegal()

static bool isLoadStoreLegal ( const GCNSubtarget &  ST, const LegalityQuery &  Query  )

static

Definition at line 542 of file AMDGPULegalizerInfo.cpp.

References hasBufferRsrcWorkaround(), isLoadStoreSizeLegal(), isRegisterType(), loadStoreBitcastWorkaround(), and llvm::LegalityQuery::Types.

isLoadStoreSizeLegal()

static bool isLoadStoreSizeLegal ( const GCNSubtarget &  ST, const LegalityQuery &  Query  )

static

Definition at line 436 of file AMDGPULegalizerInfo.cpp.

References llvm::SITargetLowering::allowsMisalignedMemoryAccessesImpl(), assert(), llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT, llvm::LLT::getSizeInBits(), llvm::LLT::isVector(), maxSizeForAddrSpace(), llvm::LegalityQuery::MMODescrs, llvm::LegalityQuery::Opcode, RegSize, Size, and llvm::LegalityQuery::Types.

Referenced by isLoadStoreLegal().

isNot()

static bool isNot ( const MachineRegisterInfo &  MRI, const MachineInstr &  MI  )

static

Definition at line 4374 of file AMDGPULegalizerInfo.cpp.

References llvm::getIConstantVRegSExtVal(), MI, and MRI.

Referenced by llvm::MCAsmParser::parseAtSpecifier(), llvm::MCAsmParserExtension::parseDirectiveCGProfile(), and verifyCFIntrinsic().

isRegisterClassType() [1/2]

static bool isRegisterClassType ( const GCNSubtarget &  ST, LLT  Ty  )

static

Definition at line 369 of file AMDGPULegalizerInfo.cpp.

References AllS16Vectors, AllS32Vectors, AllS64Vectors, AllScalarTypes, llvm::LLT::changeElementType(), llvm::LLT::getScalarSizeInBits(), llvm::is_contained(), llvm::LLT::isPointerOrPointerVector(), S16, and llvm::LLT::scalar().

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), and isRegisterClassType().

isRegisterClassType() [2/2]

static LegalityPredicate isRegisterClassType ( const GCNSubtarget &  ST, unsigned  TypeIdx  )

static

Definition at line 379 of file AMDGPULegalizerInfo.cpp.

References isRegisterClassType().

isRegisterSize()

static bool isRegisterSize ( const GCNSubtarget &  ST, unsigned  Size  )

static

Definition at line 235 of file AMDGPULegalizerInfo.cpp.

References MaxRegisterSize, and Size.

Referenced by isRegisterType(), and shouldBitcastLoadStoreType().

isRegisterType() [1/2]

static bool isRegisterType ( const GCNSubtarget &  ST, LLT  Ty  )

static

Definition at line 253 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getSizeInBits(), isRegisterSize(), isRegisterVectorType(), and llvm::LLT::isVector().

Referenced by isIllegalRegisterType(), isLoadStoreLegal(), isRegisterType(), llvm::AMDGPULegalizerInfo::legalizeLoad(), llvm::PPCLegalizerInfo::PPCLegalizerInfo(), and shouldBitcastLoadStoreType().

isRegisterType() [2/2]

static LegalityPredicate isRegisterType ( const GCNSubtarget &  ST, unsigned  TypeIdx  )

static

Definition at line 265 of file AMDGPULegalizerInfo.cpp.

References isRegisterType().

isRegisterVectorElementType()

static bool isRegisterVectorElementType ( LLT  EltTy )

static

Definition at line 240 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getSizeInBits().

Referenced by shouldBitcastLoadStoreType().

isRegisterVectorType()

static bool isRegisterVectorType ( LLT  Ty )

static

Definition at line 245 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getElementType(), llvm::LLT::getNumElements(), and llvm::LLT::getSizeInBits().

Referenced by isRegisterType().

isSmallOddVector()

static LegalityPredicate isSmallOddVector ( unsigned  TypeIdx )

static

Returns

true if this is an odd sized vector which should widen by adding an additional element. This is mostly to handle <3 x s16> -> <4 x s16>. This excludes s1 vectors, which should always be scalarized.

Definition at line 73 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getElementType(), llvm::LLT::getNumElements(), llvm::LLT::getSizeInBits(), and llvm::LLT::isVector().

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().

isTruncStoreToSizePowerOf2()

static LegalityPredicate isTruncStoreToSizePowerOf2 ( unsigned  TypeIdx )

static

Definition at line 398 of file AMDGPULegalizerInfo.cpp.

References llvm::isPowerOf2_64(), and isWideScalarExtLoadTruncStore().

isWideScalarExtLoadTruncStore()

static LegalityPredicate isWideScalarExtLoadTruncStore ( unsigned  TypeIdx )

static

Definition at line 388 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getSizeInBits(), and llvm::LLT::isVector().

Referenced by isTruncStoreToSizePowerOf2().

isWideVec16()

static LegalityPredicate isWideVec16 ( unsigned  TypeIdx )

static

Definition at line 94 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getNumElements(), llvm::LLT::getScalarType(), and llvm::LLT::getSizeInBits().

loadStoreBitcastWorkaround()

static bool loadStoreBitcastWorkaround ( const LLT  Ty )

static

Definition at line 523 of file AMDGPULegalizerInfo.cpp.

References EnableNewLegality, llvm::LLT::getScalarSizeInBits(), llvm::LLT::getSizeInBits(), hasBufferRsrcWorkaround(), llvm::LLT::isPointerVector(), llvm::LLT::isVector(), and Size.

Referenced by isLoadStoreLegal(), and shouldBitcastLoadStoreType().

maxSizeForAddrSpace()

static unsigned maxSizeForAddrSpace ( const GCNSubtarget &  ST, unsigned  AS, bool  IsLoad, bool  IsAtomic  )

static

Definition at line 409 of file AMDGPULegalizerInfo.cpp.

References llvm::AMDGPUAS::BUFFER_RESOURCE, llvm::AMDGPUAS::CONSTANT_ADDRESS, llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT, llvm::AMDGPUAS::GLOBAL_ADDRESS, llvm::AMDGPUAS::LOCAL_ADDRESS, and llvm::AMDGPUAS::PRIVATE_ADDRESS.

Referenced by isLoadStoreSizeLegal(), and shouldWidenLoad().

moreElementsToNextExistingRegClass()

static LegalizeMutation moreElementsToNextExistingRegClass ( unsigned  TypeIdx )

static

Definition at line 150 of file AMDGPULegalizerInfo.cpp.

References assert(), llvm::LLT::fixed_vector(), llvm::LLT::getElementType(), llvm::LLT::getNumElements(), llvm::SIRegisterInfo::getSGPRClassForBitWidth(), llvm::LLT::getSizeInBits(), and MaxRegisterSize.

moreEltsToNext32Bit()

static LegalizeMutation moreEltsToNext32Bit ( unsigned  TypeIdx )

static

Definition at line 125 of file AMDGPULegalizerInfo.cpp.

References assert(), llvm::LLT::fixed_vector(), llvm::LLT::getElementType(), llvm::LLT::getSizeInBits(), and Size.

needsDenormHandlingF32()

static bool needsDenormHandlingF32 ( const MachineFunction &  MF, Register  Src, unsigned  Flags  )

static

Definition at line 3420 of file AMDGPULegalizerInfo.cpp.

References llvm::MachineFunction::getDenormalMode(), llvm::MachineFunction::getRegInfo(), llvm::APFloatBase::IEEEsingle(), llvm::DenormalMode::Input, llvm::DenormalMode::PreserveSign, and valueIsKnownNeverF32Denorm().

Referenced by llvm::AMDGPULegalizerInfo::getScaledLogInput(), llvm::AMDGPULegalizerInfo::legalizeFExp2(), llvm::AMDGPULegalizerInfo::legalizeFExpUnsafe(), and llvm::AMDGPULegalizerInfo::legalizeFSQRTF32().

numElementsNotEven()

static LegalityPredicate numElementsNotEven ( unsigned  TypeIdx )

static

Definition at line 228 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getNumElements(), and llvm::LLT::isVector().

oneMoreElement()

static LegalizeMutation oneMoreElement ( unsigned  TypeIdx )

static

Definition at line 102 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::fixed_vector(), llvm::LLT::getElementType(), and llvm::LLT::getNumElements().

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().

packImage16bitOpsToDwords()

static void packImage16bitOpsToDwords ( MachineIRBuilder &  B, MachineInstr &  MI, SmallVectorImpl< Register > &  PackedAddrs, unsigned  ArgOffset, const AMDGPU::ImageDimIntrinsicInfo *  Intr, bool  IsA16, bool  IsG16  )

static

Turn a set of s16 typed registers in AddrRegs into a dword sized vector with s16 typed elements.

Definition at line 6465 of file AMDGPULegalizerInfo.cpp.

References assert(), B, llvm::LLT::fixed_vector(), llvm::SrcOp::getReg(), I, Intr, MI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), S16, llvm::LLT::scalar(), and V2S16.

Referenced by llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic().

replaceWithConstant()

static bool replaceWithConstant ( MachineIRBuilder &  B, MachineInstr &  MI, int64_t  C  )

static

Definition at line 4531 of file AMDGPULegalizerInfo.cpp.

References B, llvm::CallingConv::C, and MI.

Referenced by llvm::AMDGPULegalizerInfo::legalizeWorkitemIDIntrinsic().

shouldBitcastLoadStoreType()

static bool shouldBitcastLoadStoreType ( const GCNSubtarget &  ST, const LLT  Ty, const LLT  MemTy  )

static

Return true if a load or store of the type should be lowered with a bitcast to a different type.

Definition at line 550 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getElementType(), llvm::LLT::getSizeInBits(), isRegisterSize(), isRegisterType(), isRegisterVectorElementType(), llvm::LLT::isVector(), loadStoreBitcastWorkaround(), and Size.

Referenced by llvm::AMDGPULegalizerInfo::fixStoreSourceType(), llvm::AMDGPULegalizerInfo::legalizeBufferLoad(), and llvm::AMDGPULegalizerInfo::legalizeSBufferLoad().

shouldWidenLoad() [1/2]

static bool shouldWidenLoad ( const GCNSubtarget &  ST, const LegalityQuery &  Query, unsigned  Opcode  )

static

Definition at line 603 of file AMDGPULegalizerInfo.cpp.

References llvm::LegalityQuery::MMODescrs, shouldWidenLoad(), and llvm::LegalityQuery::Types.

shouldWidenLoad() [2/2]

static bool shouldWidenLoad ( const GCNSubtarget &  ST, LLT  MemoryTy, uint64_t  AlignInBits, unsigned  AddrSpace, unsigned  Opcode  )

static

Return true if we should legalize a load by widening an odd sized memory access up to the alignment.

Note this case when the memory access itself changes, not the size of the result register.

Definition at line 569 of file AMDGPULegalizerInfo.cpp.

References llvm::SITargetLowering::allowsMisalignedMemoryAccessesImpl(), llvm::CallingConv::Fast, llvm::LLT::getSizeInBits(), llvm::isPowerOf2_32(), maxSizeForAddrSpace(), llvm::MachineMemOperand::MOLoad, and llvm::NextPowerOf2().

Referenced by llvm::AMDGPULegalizerInfo::legalizeLoad(), and shouldWidenLoad().

sizeIsMultipleOf32()

static LegalityPredicate sizeIsMultipleOf32 ( unsigned  TypeIdx )

static

Definition at line 87 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getSizeInBits().

stripAnySourceMods()

static Register stripAnySourceMods ( Register  OrigSrc, MachineRegisterInfo &  MRI  )

static

Definition at line 3927 of file AMDGPULegalizerInfo.cpp.

References llvm::getOpcodeDef(), and MRI.

Referenced by llvm::AMDGPULegalizerInfo::legalizeFFloor().

toggleSPDenormMode()

static void toggleSPDenormMode ( bool  Enable, MachineIRBuilder &  B, const GCNSubtarget &  ST, SIModeRegisterDefaults  Mode  )

static

Definition at line 5099 of file AMDGPULegalizerInfo.cpp.

References B, llvm::Enable, FP_DENORM_FLUSH_NONE, and SPDenormModeBitField.

Referenced by llvm::AMDGPULegalizerInfo::legalizeFDIV32().

valueIsKnownNeverF32Denorm()

static bool valueIsKnownNeverF32Denorm ( const MachineRegisterInfo &  MRI, Register  Src  )

static

Return true if it's known that Src can never be an f32 denormal value.

Definition at line 3387 of file AMDGPULegalizerInfo.cpp.

References DefMI, getIntrinsicID(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), MRI, and llvm::LLT::scalar().

vectorSmallerThan()

static LegalityPredicate vectorSmallerThan ( unsigned  TypeIdx, unsigned  Size  )

static

Definition at line 214 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getSizeInBits(), llvm::LLT::isVector(), and Size.

vectorWiderThan()

static LegalityPredicate vectorWiderThan ( unsigned  TypeIdx, unsigned  Size  )

static

Definition at line 221 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getSizeInBits(), llvm::LLT::isVector(), and Size.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().

verifyCFIntrinsic()

static MachineInstr * verifyCFIntrinsic ( MachineInstr &  MI, MachineRegisterInfo &  MRI, MachineInstr *&  Br, MachineBasicBlock *&  UncondBrTarget, bool &  Negated  )

static

Definition at line 4383 of file AMDGPULegalizerInfo.cpp.

References llvm::MachineBasicBlock::end(), llvm::MachineFunction::end(), llvm::eraseInstr(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), isNot(), MI, MRI, and UseMI.

Referenced by llvm::AMDGPULegalizerInfo::legalizeIntrinsic().

widenToNextPowerOf2()

static LLT widenToNextPowerOf2 ( LLT  Ty )

static

Definition at line 3223 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::changeElementCount(), llvm::ElementCount::getFixed(), llvm::LLT::getNumElements(), llvm::LLT::getSizeInBits(), llvm::LLT::isVector(), llvm::PowerOf2Ceil(), and llvm::LLT::scalar().

Referenced by llvm::AMDGPULegalizerInfo::legalizeLoad().

Variable Documentation

AllS16Vectors

constexpr std::initializer_list<LLT> AllS16Vectors

constexpr

Initial value:

{
    V2S16, V4S16, V6S16, V8S16, V10S16, V12S16, V16S16, V2S128, V4S128}

Definition at line 352 of file AMDGPULegalizerInfo.cpp.

Referenced by isRegisterClassType().

AllS32Vectors

constexpr std::initializer_list<LLT> AllS32Vectors

constexpr

Initial value:

= {
    V2S32, V3S32,  V4S32,  V5S32,  V6S32,  V7S32, V8S32,
    V9S32, V10S32, V11S32, V12S32, V16S32, V32S32}

Definition at line 355 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), and isRegisterClassType().

AllS64Vectors

constexpr std::initializer_list<LLT> AllS64Vectors

constexpr

Initial value:

= {
    V2S64, V3S64, V4S64, V5S64, V6S64, V7S64, V8S64, V16S64}

Definition at line 359 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), and isRegisterClassType().

AllScalarTypes

constexpr std::initializer_list<LLT> AllScalarTypes

constexpr

Initial value:

= {
    S32, S64, S96, S128, S160, S192, S224, S256, S512, S1024}

Definition at line 349 of file AMDGPULegalizerInfo.cpp.

Referenced by isRegisterClassType().

AllVectors

constexpr std::initializer_list<LLT> AllVectors

constexpr

Initial value:

{
    V2S16,  V4S16,  V6S16,  V8S16,  V10S16, V12S16, V16S16, V2S128,
    V4S128, V2S32,  V3S32,  V4S32,  V5S32,  V6S32,  V7S32,  V8S32,
    V9S32,  V10S32, V11S32, V12S32, V16S32, V32S32, V2S64,  V3S64,
    V4S64,  V5S64,  V6S64,  V7S64,  V8S64,  V16S64}

Definition at line 362 of file AMDGPULegalizerInfo.cpp.

EnableNewLegality

cl::opt< bool > EnableNewLegality("amdgpu-global-isel-new-legality", cl::desc("Use GlobalISel desired legality, rather than try to use" "rules compatible with selection patterns"), cl::init(false), cl::ReallyHidden) ( "amdgpu-global-isel-new-legality"  , cl::desc("Use GlobalISel desired legality, rather than try to use" "rules compatible with selection patterns")  , cl::init(false)  , cl::ReallyHidden    )

static

Referenced by loadStoreBitcastWorkaround().

F32

constexpr LLT F32 = LLT::float32()

constexpr

Definition at line 298 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::yaml::ScalarEnumerationTraits< WasmYAML::ValueType >::enumeration(), llvm::TargetLowering::expandFP_ROUND(), llvm::AMDGPULegalizerInfo::getScaledLogInput(), llvm::AMDGPULegalizerInfo::legalizeFExp(), llvm::AMDGPULegalizerInfo::legalizeFExp2(), llvm::AMDGPULegalizerInfo::legalizeFExpUnsafe(), llvm::AMDGPULegalizerInfo::legalizeFlog2(), llvm::AMDGPULegalizerInfo::legalizeFlogCommon(), llvm::AMDGPULegalizerInfo::legalizeFPow(), llvm::AMDGPULegalizerInfo::legalizeFSQRTF16(), and llvm::AMDGPULegalizerInfo::legalizeFSQRTF32().

F64

constexpr LLT F64 = LLT::float64()

constexpr

Definition at line 300 of file AMDGPULegalizerInfo.cpp.

Referenced by combineBitcast(), llvm::yaml::ScalarEnumerationTraits< WasmYAML::ValueType >::enumeration(), llvm::AMDGPULegalizerInfo::legalizeFFloor(), llvm::AMDGPULegalizerInfo::legalizeFSQRTF64(), and PerformExtractEltToVMOVRRD().

FPEnvModeBitField

constexpr unsigned FPEnvModeBitField

staticconstexpr

Initial value:

=
    AMDGPU::Hwreg::HwregEncoding::encode(AMDGPU::Hwreg::ID_MODE, 0, 23)

Definition at line 7419 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::legalizeGetFPEnv(), and llvm::AMDGPULegalizerInfo::legalizeSetFPEnv().

FPEnvTrapBitField

constexpr unsigned FPEnvTrapBitField

staticconstexpr

Initial value:

=
    AMDGPU::Hwreg::HwregEncoding::encode(AMDGPU::Hwreg::ID_TRAPSTS, 0, 5)

Definition at line 7422 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::legalizeGetFPEnv(), and llvm::AMDGPULegalizerInfo::legalizeSetFPEnv().

MaxRegisterSize

constexpr unsigned MaxRegisterSize = 1024

staticconstexpr

Definition at line 54 of file AMDGPULegalizerInfo.cpp.

Referenced by isRegisterSize(), and moreElementsToNextExistingRegClass().

MaxScalar

constexpr LLT MaxScalar = LLT::scalar(MaxRegisterSize)

constexpr

Definition at line 309 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().

S1

constexpr LLT S1 = LLT::scalar(1)

constexpr

Definition at line 294 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), llvm::HexagonSubtarget::BankConflictMutation::apply(), llvm::AMDGPURegisterBankInfo::applyMappingMAD_64_32(), llvm::BinaryOperator::BinaryOperator(), llvm::AMDGPULegalizerInfo::buildMultiply(), llvm::StringSwitch< T, R >::Cases(), llvm::StringSwitch< T, R >::CasesLower(), llvm::BinaryOperator::Create(), llvm::CmpInst::Create(), llvm::sandboxir::CmpInst::create(), llvm::SelectInst::Create(), CreateAdd(), CreateMul(), CreateNeg(), llvm::CmpInst::CreateWithCopiedFlags(), llvm::PMDataManager::dumpPassInfo(), llvm::AMDGPURegisterBankInfo::executeInWaterfallLoop(), foldShuffleOfUnaryOps(), getAnySgprS1(), getNearestMatchingScope(), getPRMTSelector(), gsiRecordCmp(), INITIALIZE_PASS(), llvm::isEqual(), llvm::Mips::isGpOff(), llvm::Instruction::isIdenticalTo(), isMemOPCandidate(), llvm::AMDGPULegalizerInfo::legalizeFceil(), llvm::AMDGPULegalizerInfo::legalizeFDIV32(), llvm::AMDGPULegalizerInfo::legalizeFDIV64(), llvm::AMDGPULegalizerInfo::legalizeFDIVFastIntrin(), llvm::AMDGPULegalizerInfo::legalizeFFloor(), llvm::AMDGPULegalizerInfo::legalizeFSQRTF32(), llvm::AMDGPULegalizerInfo::legalizeFSQRTF64(), llvm::AMDGPULegalizerInfo::legalizeIntrinsicTrunc(), llvm::AMDGPULegalizerInfo::legalizeUnsignedDIV_REM32Impl(), llvm::AMDGPULegalizerInfo::legalizeUnsignedDIV_REM64Impl(), llvm::LegalizerHelper::lowerFPTOSI(), llvm::LegalizerHelper::lowerFPTOUI(), llvm::LegalizerHelper::lowerFPTRUNC_F64_TO_F16(), llvm::LegalizerHelper::lowerSITOFP(), llvm::LegalizerHelper::lowerU64ToF32BitOps(), llvm::LegalizerHelper::lowerU64ToF32WithSITOFP(), matchBinaryPermuteShuffle(), llvm::CombinerHelper::matchCommuteShift(), llvm::ARMTargetLowering::PerformMVETruncCombine(), performVectorExtCombine(), llvm::PPCLegalizerInfo::PPCLegalizerInfo(), runImpl(), llvm::set_difference(), llvm::set_intersect(), llvm::set_intersection(), llvm::set_intersection_impl(), llvm::set_intersects(), llvm::detail::set_intersects_impl(), llvm::set_is_subset(), llvm::set_subtract(), llvm::set_union(), simplifyLoopInst(), and llvm::GISelCSEInfo::verify().

S1024

constexpr LLT S1024 = LLT::scalar(1024)

constexpr

Definition at line 308 of file AMDGPULegalizerInfo.cpp.

S128

constexpr LLT S128 = LLT::scalar(128)

constexpr

Definition at line 302 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().

S16

constexpr LLT S16 = LLT::scalar(16)

constexpr

Definition at line 296 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), llvm::AMDGPULegalizerInfo::fixStoreSourceType(), llvm::AMDGPURegisterBankInfo::handleD16VData(), llvm::AMDGPULegalizerInfo::handleD16VData(), llvm::HexagonAsmPrinter::HexagonProcessInstruction(), isRegisterClassType(), llvm::AMDGPULegalizerInfo::legalizeBuildVector(), llvm::AMDGPULegalizerInfo::legalizeBVHIntersectRayIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeFDIV(), llvm::AMDGPULegalizerInfo::legalizeFDIV16(), llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic(), llvm::LegalizerHelper::lowerFPTRUNC(), packImage16bitOpsToDwords(), and llvm::PPCLegalizerInfo::PPCLegalizerInfo().

S160

constexpr LLT S160 = LLT::scalar(160)

constexpr

Definition at line 303 of file AMDGPULegalizerInfo.cpp.

S192

constexpr LLT S192 = LLT::scalar(192)

constexpr

Definition at line 304 of file AMDGPULegalizerInfo.cpp.

S224

constexpr LLT S224 = LLT::scalar(224)

constexpr

Definition at line 305 of file AMDGPULegalizerInfo.cpp.

S256

constexpr LLT S256 = LLT::scalar(256)

constexpr

Definition at line 306 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().

S32

constexpr LLT S32 = LLT::scalar(32)

constexpr

Definition at line 297 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::SITargetLowering::allocateSpecialEntryInputVGPRs(), llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), llvm::AMDGPURegisterBankInfo::applyMappingBFE(), llvm::AMDGPURegisterBankInfo::applyMappingImpl(), llvm::AMDGPURegisterBankInfo::applyMappingLoad(), llvm::AMDGPURegisterBankInfo::applyMappingMAD_64_32(), llvm::AMDGPURegisterBankInfo::applyMappingSBufferLoad(), llvm::AMDGPULegalizerInfo::buildAbsGlobalAddress(), llvm::AMDGPULegalizerInfo::buildLoadInputValue(), llvm::AMDGPULegalizerInfo::buildMultiply(), llvm::AMDGPURegisterBankInfo::buildReadFirstLane(), castBufferRsrcFromV4I32(), convertImageAddrToPacked(), emitReciprocalU64(), extractF64Exponent(), llvm::AMDGPULegalizerInfo::getSegmentAperture(), llvm::AMDGPURegisterBankInfo::handleD16VData(), llvm::AMDGPULegalizerInfo::handleD16VData(), llvm::AMDGPULegalizerInfo::legalizeAddrSpaceCast(), llvm::AMDGPULegalizerInfo::legalizeBufferLoad(), llvm::AMDGPULegalizerInfo::legalizeBufferStore(), llvm::AMDGPULegalizerInfo::legalizeBuildVector(), llvm::AMDGPULegalizerInfo::legalizeBVHDualOrBVH8IntersectRayIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeBVHIntersectRayIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeCTLZ_ZERO_UNDEF(), llvm::AMDGPULegalizerInfo::legalizeFDIV(), llvm::AMDGPULegalizerInfo::legalizeFDIV16(), llvm::AMDGPULegalizerInfo::legalizeFDIV32(), llvm::AMDGPULegalizerInfo::legalizeFDIV64(), llvm::AMDGPULegalizerInfo::legalizeFDIVFastIntrin(), llvm::AMDGPULegalizerInfo::legalizeFPTOI(), llvm::AMDGPULegalizerInfo::legalizeFSQRTF64(), llvm::AMDGPULegalizerInfo::legalizeGetFPEnv(), llvm::AMDGPULegalizerInfo::legalizeGlobalValue(), llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeIntrinsicTrunc(), llvm::AMDGPULegalizerInfo::legalizeIsAddrSpace(), llvm::AMDGPULegalizerInfo::legalizeITOFP(), llvm::AMDGPULegalizerInfo::legalizeLaneOp(), llvm::AMDGPULegalizerInfo::legalizeMul(), llvm::AMDGPULegalizerInfo::legalizePointerAsRsrcIntrin(), llvm::AMDGPULegalizerInfo::legalizeSetFPEnv(), llvm::AMDGPULegalizerInfo::legalizeSignedDIV_REM(), llvm::AMDGPULegalizerInfo::legalizeUnsignedDIV_REM(), llvm::AMDGPULegalizerInfo::legalizeUnsignedDIV_REM32Impl(), llvm::AMDGPULegalizerInfo::legalizeUnsignedDIV_REM64Impl(), llvm::AMDGPULegalizerInfo::legalizeWaveID(), llvm::LegalizerHelper::lowerFPTOSI(), llvm::LegalizerHelper::lowerFPTOUI(), llvm::LegalizerHelper::lowerFPTRUNC_F64_TO_F16(), llvm::LegalizerHelper::lowerSITOFP(), llvm::LegalizerHelper::lowerU64ToF32BitOps(), llvm::LegalizerHelper::lowerU64ToF32WithSITOFP(), llvm::LegalizerHelper::lowerU64ToF64BitFloatOps(), llvm::AMDGPUCallLowering::passSpecialInputs(), llvm::PPCLegalizerInfo::PPCLegalizerInfo(), reinsertVectorIndexAdd(), llvm::AMDGPURegisterBankInfo::setBufferOffsets(), llvm::AMDGPURegisterBankInfo::splitBufferOffsets(), llvm::AMDGPULegalizerInfo::splitBufferOffsets(), and unpackV2S16ToS32().

S512

constexpr LLT S512 = LLT::scalar(512)

constexpr

Definition at line 307 of file AMDGPULegalizerInfo.cpp.

S64

constexpr LLT S64 = LLT::scalar(64)

constexpr

Definition at line 299 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), llvm::AMDGPURegisterBankInfo::applyMappingBFE(), llvm::AMDGPURegisterBankInfo::applyMappingImpl(), llvm::AMDGPULegalizerInfo::buildMultiply(), llvm::AMDGPULegalizerInfo::getSegmentAperture(), llvm::AMDGPULegalizerInfo::legalizeAddrSpaceCast(), llvm::AMDGPULegalizerInfo::legalizeFceil(), llvm::AMDGPULegalizerInfo::legalizeFDIV(), llvm::AMDGPULegalizerInfo::legalizeFDIV64(), llvm::AMDGPULegalizerInfo::legalizeFPTOI(), llvm::AMDGPULegalizerInfo::legalizeGetFPEnv(), llvm::AMDGPULegalizerInfo::legalizeIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeIntrinsicTrunc(), llvm::AMDGPULegalizerInfo::legalizeITOFP(), llvm::AMDGPULegalizerInfo::legalizeSetFPEnv(), llvm::AMDGPULegalizerInfo::legalizeSignedDIV_REM(), llvm::AMDGPULegalizerInfo::legalizeTrapHsaQueuePtr(), llvm::AMDGPULegalizerInfo::legalizeUnsignedDIV_REM(), llvm::AMDGPULegalizerInfo::legalizeUnsignedDIV_REM64Impl(), llvm::LegalizerHelper::lowerFPTOSI(), llvm::LegalizerHelper::lowerFPTOUI(), llvm::LegalizerHelper::lowerFPTRUNC(), llvm::LegalizerHelper::lowerSITOFP(), llvm::LegalizerHelper::lowerU64ToF32BitOps(), llvm::LegalizerHelper::lowerU64ToF32WithSITOFP(), llvm::LegalizerHelper::lowerU64ToF64BitFloatOps(), and llvm::PPCLegalizerInfo::PPCLegalizerInfo().

S8

constexpr LLT S8 = LLT::scalar(8)

constexpr

Definition at line 295 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), llvm::StringSwitch< T, R >::Cases(), and llvm::PPCLegalizerInfo::PPCLegalizerInfo().

S96

constexpr LLT S96 = LLT::scalar(96)

constexpr

Definition at line 301 of file AMDGPULegalizerInfo.cpp.

SPDenormModeBitField

constexpr unsigned SPDenormModeBitField

staticconstexpr

Initial value:

=
    AMDGPU::Hwreg::HwregEncoding::encode(AMDGPU::Hwreg::ID_MODE, 4, 2)

Definition at line 5094 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::legalizeFDIV32(), and toggleSPDenormMode().

V10S16

constexpr LLT V10S16 = LLT::fixed_vector(10, 16)

constexpr

Definition at line 316 of file AMDGPULegalizerInfo.cpp.

V10S32

constexpr LLT V10S32 = LLT::fixed_vector(10, 32)

constexpr

Definition at line 331 of file AMDGPULegalizerInfo.cpp.

V11S32

constexpr LLT V11S32 = LLT::fixed_vector(11, 32)

constexpr

Definition at line 332 of file AMDGPULegalizerInfo.cpp.

V12S16

constexpr LLT V12S16 = LLT::fixed_vector(12, 16)

constexpr

Definition at line 317 of file AMDGPULegalizerInfo.cpp.

V12S32

constexpr LLT V12S32 = LLT::fixed_vector(12, 32)

constexpr

Definition at line 333 of file AMDGPULegalizerInfo.cpp.

V16S16

constexpr LLT V16S16 = LLT::fixed_vector(16, 16)

constexpr

Definition at line 318 of file AMDGPULegalizerInfo.cpp.

V16S32

constexpr LLT V16S32 = LLT::fixed_vector(16, 32)

constexpr

Definition at line 334 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().

V16S64

constexpr LLT V16S64 = LLT::fixed_vector(16, 64)

constexpr

Definition at line 344 of file AMDGPULegalizerInfo.cpp.

V2BF16

constexpr LLT V2BF16 = V2F16

constexpr

Definition at line 321 of file AMDGPULegalizerInfo.cpp.

V2F16

constexpr LLT V2F16 = LLT::fixed_vector(2, LLT::float16())

constexpr

Definition at line 320 of file AMDGPULegalizerInfo.cpp.

V2S128

constexpr LLT V2S128 = LLT::fixed_vector(2, 128)

constexpr

Definition at line 346 of file AMDGPULegalizerInfo.cpp.

V2S16

constexpr LLT V2S16 = LLT::fixed_vector(2, 16)

constexpr

Definition at line 312 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), llvm::AMDGPULegalizerInfo::legalizeBVHIntersectRayIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic(), and packImage16bitOpsToDwords().

V2S32

constexpr LLT V2S32 = LLT::fixed_vector(2, 32)

constexpr

Definition at line 323 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), and llvm::AMDGPULegalizerInfo::legalizeBVHDualOrBVH8IntersectRayIntrinsic().

V2S64

constexpr LLT V2S64 = LLT::fixed_vector(2, 64)

constexpr

Definition at line 337 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::PPCLegalizerInfo::PPCLegalizerInfo().

V2S8

constexpr LLT V2S8 = LLT::fixed_vector(2, 8)

constexpr

Definition at line 311 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().

V32S32

constexpr LLT V32S32 = LLT::fixed_vector(32, 32)

constexpr

Definition at line 335 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().

V3S32

constexpr LLT V3S32 = LLT::fixed_vector(3, 32)

constexpr

Definition at line 324 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::legalizeBVHIntersectRayIntrinsic().

V3S64

constexpr LLT V3S64 = LLT::fixed_vector(3, 64)

constexpr

Definition at line 338 of file AMDGPULegalizerInfo.cpp.

V4S128

constexpr LLT V4S128 = LLT::fixed_vector(4, 128)

constexpr

Definition at line 347 of file AMDGPULegalizerInfo.cpp.

V4S16

constexpr LLT V4S16 = LLT::fixed_vector(4, 16)

constexpr

Definition at line 313 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), and llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic().

V4S32

constexpr LLT V4S32 = LLT::fixed_vector(4, 32)

constexpr

Definition at line 325 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::PPCLegalizerInfo::PPCLegalizerInfo().

V4S64

constexpr LLT V4S64 = LLT::fixed_vector(4, 64)

constexpr

Definition at line 339 of file AMDGPULegalizerInfo.cpp.

V5S32

constexpr LLT V5S32 = LLT::fixed_vector(5, 32)

constexpr

Definition at line 326 of file AMDGPULegalizerInfo.cpp.

V5S64

constexpr LLT V5S64 = LLT::fixed_vector(5, 64)

constexpr

Definition at line 340 of file AMDGPULegalizerInfo.cpp.

V6S16

constexpr LLT V6S16 = LLT::fixed_vector(6, 16)

constexpr

Definition at line 314 of file AMDGPULegalizerInfo.cpp.

V6S32

constexpr LLT V6S32 = LLT::fixed_vector(6, 32)

constexpr

Definition at line 327 of file AMDGPULegalizerInfo.cpp.

V6S64

constexpr LLT V6S64 = LLT::fixed_vector(6, 64)

constexpr

Definition at line 341 of file AMDGPULegalizerInfo.cpp.

V7S32

constexpr LLT V7S32 = LLT::fixed_vector(7, 32)

constexpr

Definition at line 328 of file AMDGPULegalizerInfo.cpp.

V7S64

constexpr LLT V7S64 = LLT::fixed_vector(7, 64)

constexpr

Definition at line 342 of file AMDGPULegalizerInfo.cpp.

V8S16

constexpr LLT V8S16 = LLT::fixed_vector(8, 16)

constexpr

Definition at line 315 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::PPCLegalizerInfo::PPCLegalizerInfo().

V8S32

constexpr LLT V8S32 = LLT::fixed_vector(8, 32)

constexpr

Definition at line 329 of file AMDGPULegalizerInfo.cpp.

V8S64

constexpr LLT V8S64 = LLT::fixed_vector(8, 64)

constexpr

Definition at line 343 of file AMDGPULegalizerInfo.cpp.

V9S32

constexpr LLT V9S32 = LLT::fixed_vector(9, 32)

constexpr

Definition at line 330 of file AMDGPULegalizerInfo.cpp.