LLVM 22.0.0git
CSKYDisassembler.cpp
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1//===-- CSKYDisassembler.cpp - Disassembler for CSKY ----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the CSKYDisassembler class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MCTargetDesc/CSKYBaseInfo.h"
14#include "MCTargetDesc/CSKYMCTargetDesc.h"
15#include "TargetInfo/CSKYTargetInfo.h"
16#include "llvm/ADT/DenseMap.h"
17#include "llvm/MC/MCContext.h"
18#include "llvm/MC/MCDecoder.h"
19#include "llvm/MC/MCDecoderOps.h"
20#include "llvm/MC/MCDisassembler/MCDisassembler.h"
21#include "llvm/MC/MCInst.h"
22#include "llvm/MC/MCInstrInfo.h"
23#include "llvm/MC/MCRegisterInfo.h"
24#include "llvm/MC/MCSubtargetInfo.h"
25#include "llvm/MC/TargetRegistry.h"
26#include "llvm/Support/Endian.h"
27
28using namespace llvm;
29
30#define DEBUG_TYPE "csky-disassembler"
31
32typedef MCDisassembler::DecodeStatus DecodeStatus;
33
34namespace {
35class CSKYDisassembler : public MCDisassembler {
36 std::unique_ptr<MCInstrInfo const> const MCII;
37 mutable StringRef symbolName;
38
39 DecodeStatus handleCROperand(MCInst &Instr) const;
40
41public:
42 CSKYDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
43 MCInstrInfo const *MCII);
44
45 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
46 ArrayRef<uint8_t> Bytes, uint64_t Address,
47 raw_ostream &CStream) const override;
48};
49} // end anonymous namespace
50
51CSKYDisassembler::CSKYDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
52 MCInstrInfo const *MCII)
53 : MCDisassembler(STI, Ctx), MCII(MCII) {}
54
55static MCDisassembler *createCSKYDisassembler(const Target &T,
56 const MCSubtargetInfo &STI,
57 MCContext &Ctx) {
58 return new CSKYDisassembler(STI, Ctx, T.createMCInstrInfo());
59}
60
61extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeCSKYDisassembler() {
62 TargetRegistry::RegisterMCDisassembler(getTheCSKYTarget(),
63 createCSKYDisassembler);
64}
65
66static const uint16_t GPRDecoderTable[] = {
67 CSKY::R0, CSKY::R1, CSKY::R2, CSKY::R3, CSKY::R4, CSKY::R5, CSKY::R6,
68 CSKY::R7, CSKY::R8, CSKY::R9, CSKY::R10, CSKY::R11, CSKY::R12, CSKY::R13,
69 CSKY::R14, CSKY::R15, CSKY::R16, CSKY::R17, CSKY::R18, CSKY::R19, CSKY::R20,
70 CSKY::R21, CSKY::R22, CSKY::R23, CSKY::R24, CSKY::R25, CSKY::R26, CSKY::R27,
71 CSKY::R28, CSKY::R29, CSKY::R30, CSKY::R31};
72
73static const uint16_t GPRPairDecoderTable[] = {
74 CSKY::R0_R1, CSKY::R1_R2, CSKY::R2_R3, CSKY::R3_R4, CSKY::R4_R5,
75 CSKY::R5_R6, CSKY::R6_R7, CSKY::R7_R8, CSKY::R8_R9, CSKY::R9_R10,
76 CSKY::R10_R11, CSKY::R11_R12, CSKY::R12_R13, CSKY::R13_R14, CSKY::R14_R15,
77 CSKY::R15_R16, CSKY::R16_R17, CSKY::R17_R18, CSKY::R18_R19, CSKY::R19_R20,
78 CSKY::R20_R21, CSKY::R21_R22, CSKY::R22_R23, CSKY::R23_R24, CSKY::R24_R25,
79 CSKY::R25_R26, CSKY::R26_R27, CSKY::R27_R28, CSKY::R28_R29, CSKY::R29_R30,
80 CSKY::R30_R31, CSKY::R31_R32};
81
82static const uint16_t FPR32DecoderTable[] = {
83 CSKY::F0_32, CSKY::F1_32, CSKY::F2_32, CSKY::F3_32, CSKY::F4_32,
84 CSKY::F5_32, CSKY::F6_32, CSKY::F7_32, CSKY::F8_32, CSKY::F9_32,
85 CSKY::F10_32, CSKY::F11_32, CSKY::F12_32, CSKY::F13_32, CSKY::F14_32,
86 CSKY::F15_32, CSKY::F16_32, CSKY::F17_32, CSKY::F18_32, CSKY::F19_32,
87 CSKY::F20_32, CSKY::F21_32, CSKY::F22_32, CSKY::F23_32, CSKY::F24_32,
88 CSKY::F25_32, CSKY::F26_32, CSKY::F27_32, CSKY::F28_32, CSKY::F29_32,
89 CSKY::F30_32, CSKY::F31_32};
90
91static const uint16_t FPR64DecoderTable[] = {
92 CSKY::F0_64, CSKY::F1_64, CSKY::F2_64, CSKY::F3_64, CSKY::F4_64,
93 CSKY::F5_64, CSKY::F6_64, CSKY::F7_64, CSKY::F8_64, CSKY::F9_64,
94 CSKY::F10_64, CSKY::F11_64, CSKY::F12_64, CSKY::F13_64, CSKY::F14_64,
95 CSKY::F15_64, CSKY::F16_64, CSKY::F17_64, CSKY::F18_64, CSKY::F19_64,
96 CSKY::F20_64, CSKY::F21_64, CSKY::F22_64, CSKY::F23_64, CSKY::F24_64,
97 CSKY::F25_64, CSKY::F26_64, CSKY::F27_64, CSKY::F28_64, CSKY::F29_64,
98 CSKY::F30_64, CSKY::F31_64};
99
100static const uint16_t FPR128DecoderTable[] = {
101 CSKY::F0_128, CSKY::F1_128, CSKY::F2_128, CSKY::F3_128, CSKY::F4_128,
102 CSKY::F5_128, CSKY::F6_128, CSKY::F7_128, CSKY::F8_128, CSKY::F9_128,
103 CSKY::F10_128, CSKY::F11_128, CSKY::F12_128, CSKY::F13_128, CSKY::F14_128,
104 CSKY::F15_128, CSKY::F16_128, CSKY::F17_128, CSKY::F18_128, CSKY::F19_128,
105 CSKY::F20_128, CSKY::F21_128, CSKY::F22_128, CSKY::F23_128, CSKY::F24_128,
106 CSKY::F25_128, CSKY::F26_128, CSKY::F27_128, CSKY::F28_128, CSKY::F29_128,
107 CSKY::F30_128, CSKY::F31_128};
108
109static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo,
110 uint64_t Address,
111 const MCDisassembler *Decoder) {
112 if (RegNo >= 32)
113 return MCDisassembler::Fail;
114
115 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo]));
116 return MCDisassembler::Success;
117}
118
119static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo,
120 uint64_t Address,
121 const MCDisassembler *Decoder) {
122 if (RegNo >= 32)
123 return MCDisassembler::Fail;
124
125 Inst.addOperand(MCOperand::createReg(FPR32DecoderTable[RegNo]));
126 return MCDisassembler::Success;
127}
128
129static DecodeStatus DecodesFPR32RegisterClass(MCInst &Inst, uint64_t RegNo,
130 uint64_t Address,
131 const MCDisassembler *Decoder) {
132 if (RegNo >= 16)
133 return MCDisassembler::Fail;
134
135 Inst.addOperand(MCOperand::createReg(FPR32DecoderTable[RegNo]));
136 return MCDisassembler::Success;
137}
138
139static DecodeStatus DecodesFPR64RegisterClass(MCInst &Inst, uint64_t RegNo,
140 uint64_t Address,
141 const MCDisassembler *Decoder) {
142 if (RegNo >= 16)
143 return MCDisassembler::Fail;
144
145 Inst.addOperand(MCOperand::createReg(FPR64DecoderTable[RegNo]));
146 return MCDisassembler::Success;
147}
148
149static DecodeStatus DecodesFPR64_VRegisterClass(MCInst &Inst, uint64_t RegNo,
150 uint64_t Address,
151 const MCDisassembler *Decoder) {
152 if (RegNo >= 16)
153 return MCDisassembler::Fail;
154
155 Inst.addOperand(MCOperand::createReg(FPR64DecoderTable[RegNo]));
156 return MCDisassembler::Success;
157}
158
159static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo,
160 uint64_t Address,
161 const MCDisassembler *Decoder) {
162 if (RegNo >= 32)
163 return MCDisassembler::Fail;
164
165 Inst.addOperand(MCOperand::createReg(FPR64DecoderTable[RegNo]));
166 return MCDisassembler::Success;
167}
168
169// TODO
170LLVM_ATTRIBUTE_UNUSED
171static DecodeStatus DecodesFPR128RegisterClass(MCInst &Inst, uint64_t RegNo,
172 uint64_t Address,
173 const MCDisassembler *Decoder) {
174 if (RegNo >= 16)
175 return MCDisassembler::Fail;
176
177 Inst.addOperand(MCOperand::createReg(FPR128DecoderTable[RegNo]));
178 return MCDisassembler::Success;
179}
180
181static DecodeStatus DecodesGPRRegisterClass(MCInst &Inst, uint64_t RegNo,
182 uint64_t Address,
183 const MCDisassembler *Decoder) {
184 if (RegNo >= 16)
185 return MCDisassembler::Fail;
186
187 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo]));
188 return MCDisassembler::Success;
189}
190
191static DecodeStatus DecodemGPRRegisterClass(MCInst &Inst, uint64_t RegNo,
192 uint64_t Address,
193 const MCDisassembler *Decoder) {
194 if (RegNo >= 8)
195 return MCDisassembler::Fail;
196
197 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo]));
198 return MCDisassembler::Success;
199}
200
201// TODO
202LLVM_ATTRIBUTE_UNUSED
203static DecodeStatus DecodeGPRSPRegisterClass(MCInst &Inst, uint64_t RegNo,
204 uint64_t Address,
205 const MCDisassembler *Decoder) {
206 if (RegNo != 14)
207 return MCDisassembler::Fail;
208
209 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo]));
210 return MCDisassembler::Success;
211}
212
213static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, uint64_t RegNo,
214 uint64_t Address,
215 const MCDisassembler *Decoder) {
216 const FeatureBitset &FeatureBits =
217 Decoder->getSubtargetInfo().getFeatureBits();
218 bool hasHighReg = FeatureBits[CSKY::FeatureHighreg];
219
220 if (RegNo >= 32 || (!hasHighReg && RegNo >= 16))
221 return MCDisassembler::Fail;
222
223 Inst.addOperand(MCOperand::createReg(GPRPairDecoderTable[RegNo]));
224 return MCDisassembler::Success;
225}
226
227template <unsigned N, unsigned S>
228static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
229 int64_t Address,
230 const MCDisassembler *Decoder) {
231 assert(isUInt<N>(Imm) && "Invalid immediate");
232 Inst.addOperand(MCOperand::createImm(Imm << S));
233 return MCDisassembler::Success;
234}
235
236template <unsigned N>
237static DecodeStatus decodeOImmOperand(MCInst &Inst, uint64_t Imm,
238 int64_t Address,
239 const MCDisassembler *Decoder) {
240 assert(isUInt<N>(Imm) && "Invalid immediate");
241 Inst.addOperand(MCOperand::createImm(Imm + 1));
242 return MCDisassembler::Success;
243}
244
245static DecodeStatus decodeLRW16Imm8(MCInst &Inst, uint64_t Imm, int64_t Address,
246 const MCDisassembler *Decoder) {
247 assert(isUInt<8>(Imm) && "Invalid immediate");
248 if ((Imm >> 7) & 0x1) {
249 Inst.addOperand(MCOperand::createImm((Imm & 0x7F) << 2));
250 } else {
251 uint64_t V = ((Imm ^ 0xFFFFFFFF) & 0xFF);
252 Inst.addOperand(MCOperand::createImm(V << 2));
253 }
254
255 return MCDisassembler::Success;
256}
257
258static DecodeStatus decodeJMPIXImmOperand(MCInst &Inst, uint64_t Imm,
259 int64_t Address,
260 const MCDisassembler *Decoder) {
261 assert(isUInt<2>(Imm) && "Invalid immediate");
262
263 if (Imm == 0)
264 Inst.addOperand(MCOperand::createImm(16));
265 else if (Imm == 1)
266 Inst.addOperand(MCOperand::createImm(24));
267 else if (Imm == 2)
268 Inst.addOperand(MCOperand::createImm(32));
269 else if (Imm == 3)
270 Inst.addOperand(MCOperand::createImm(40));
271 else
272 return MCDisassembler::Fail;
273
274 return MCDisassembler::Success;
275}
276
277static DecodeStatus DecodeRegSeqOperand(MCInst &Inst, uint64_t Imm,
278 int64_t Address,
279 const MCDisassembler *Decoder) {
280 assert(isUInt<10>(Imm) && "Invalid immediate");
281
282 auto Imm5 = Imm & 0x1f;
283 auto Ry = (Imm >> 5) & 0x1f;
284
285 if (DecodeGPRRegisterClass(Inst, Ry, Address, Decoder) ==
286 MCDisassembler::Fail)
287 return MCDisassembler::Fail;
288
289 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Ry + Imm5]));
290
291 return MCDisassembler::Success;
292}
293
294static DecodeStatus DecodeRegSeqOperandF1(MCInst &Inst, uint64_t Imm,
295 int64_t Address,
296 const MCDisassembler *Decoder) {
297 assert(isUInt<10>(Imm) && "Invalid immediate");
298
299 auto Imm5 = Imm & 0x1f;
300 auto Ry = (Imm >> 5) & 0x1f;
301
302 if (DecodesFPR32RegisterClass(Inst, Ry, Address, Decoder) ==
303 MCDisassembler::Fail)
304 return MCDisassembler::Fail;
305
306 Inst.addOperand(MCOperand::createReg(FPR32DecoderTable[Ry + Imm5]));
307
308 return MCDisassembler::Success;
309}
310
311static DecodeStatus DecodeRegSeqOperandD1(MCInst &Inst, uint64_t Imm,
312 int64_t Address,
313 const MCDisassembler *Decoder) {
314 assert(isUInt<10>(Imm) && "Invalid immediate");
315
316 auto Imm5 = Imm & 0x1f;
317 auto Ry = (Imm >> 5) & 0x1f;
318
319 if (DecodesFPR64RegisterClass(Inst, Ry, Address, Decoder) ==
320 MCDisassembler::Fail)
321 return MCDisassembler::Fail;
322
323 Inst.addOperand(MCOperand::createReg(FPR64DecoderTable[Ry + Imm5]));
324
325 return MCDisassembler::Success;
326}
327
328static DecodeStatus DecodeRegSeqOperandF2(MCInst &Inst, uint64_t Imm,
329 int64_t Address,
330 const MCDisassembler *Decoder) {
331 assert(isUInt<10>(Imm) && "Invalid immediate");
332
333 auto Imm5 = Imm & 0x1f;
334 auto Ry = (Imm >> 5) & 0x1f;
335
336 if (DecodeFPR32RegisterClass(Inst, Ry, Address, Decoder) ==
337 MCDisassembler::Fail)
338 return MCDisassembler::Fail;
339
340 Inst.addOperand(MCOperand::createReg(FPR32DecoderTable[Ry + Imm5]));
341
342 return MCDisassembler::Success;
343}
344
345static DecodeStatus DecodeRegSeqOperandD2(MCInst &Inst, uint64_t Imm,
346 int64_t Address,
347 const MCDisassembler *Decoder) {
348 assert(isUInt<10>(Imm) && "Invalid immediate");
349
350 auto Imm5 = Imm & 0x1f;
351 auto Ry = (Imm >> 5) & 0x1f;
352
353 if (DecodeFPR64RegisterClass(Inst, Ry, Address, Decoder) ==
354 MCDisassembler::Fail)
355 return MCDisassembler::Fail;
356
357 Inst.addOperand(MCOperand::createReg(FPR64DecoderTable[Ry + Imm5]));
358
359 return MCDisassembler::Success;
360}
361
362static DecodeStatus decodeImmShiftOpValue(MCInst &Inst, uint64_t Imm,
363 int64_t Address,
364 const MCDisassembler *Decoder) {
365 Inst.addOperand(MCOperand::createImm(Log2_64(Imm)));
366 return MCDisassembler::Success;
367}
368
369template <unsigned N, unsigned S>
370static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
371 int64_t Address,
372 const MCDisassembler *Decoder) {
373 assert(isUInt<N>(Imm) && "Invalid immediate");
374 // Sign-extend the number in the bottom N bits of Imm
375 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm) << S));
376 return MCDisassembler::Success;
377}
378
379#include "CSKYGenDisassemblerTables.inc"
380
381DecodeStatus CSKYDisassembler::handleCROperand(MCInst &MI) const {
382
383 // FIXME: To query instruction info from td file or a table inc file
384 switch (MI.getOpcode()) {
385 default:
386 return MCDisassembler::Success;
387 case CSKY::LD16WSP:
388 case CSKY::ST16WSP:
389 case CSKY::ADDI16ZSP:
390 MI.insert(std::next(MI.begin()), MCOperand::createReg(CSKY::R14));
391 return MCDisassembler::Success;
392 case CSKY::ADDI16SPSP:
393 case CSKY::SUBI16SPSP:
394 MI.insert(MI.begin(), MCOperand::createReg(CSKY::R14));
395 MI.insert(MI.begin(), MCOperand::createReg(CSKY::R14));
396 return MCDisassembler::Success;
397 case CSKY::FCMPHS_S:
398 case CSKY::FCMPHS_D:
399 case CSKY::FCMPLT_S:
400 case CSKY::FCMPLT_D:
401 case CSKY::FCMPNE_S:
402 case CSKY::FCMPNE_D:
403 case CSKY::FCMPUO_S:
404 case CSKY::FCMPUO_D:
405 case CSKY::FCMPZHS_S:
406 case CSKY::FCMPZHS_D:
407 case CSKY::FCMPZLS_S:
408 case CSKY::FCMPZLS_D:
409 case CSKY::FCMPZNE_S:
410 case CSKY::FCMPZNE_D:
411 case CSKY::FCMPZUO_S:
412 case CSKY::FCMPZUO_D:
413 case CSKY::f2FCMPHS_S:
414 case CSKY::f2FCMPHS_D:
415 case CSKY::f2FCMPLT_S:
416 case CSKY::f2FCMPLT_D:
417 case CSKY::f2FCMPNE_S:
418 case CSKY::f2FCMPNE_D:
419 case CSKY::f2FCMPUO_S:
420 case CSKY::f2FCMPUO_D:
421 case CSKY::f2FCMPHSZ_S:
422 case CSKY::f2FCMPHSZ_D:
423 case CSKY::f2FCMPHZ_S:
424 case CSKY::f2FCMPHZ_D:
425 case CSKY::f2FCMPLSZ_S:
426 case CSKY::f2FCMPLSZ_D:
427 case CSKY::f2FCMPLTZ_S:
428 case CSKY::f2FCMPLTZ_D:
429 case CSKY::f2FCMPNEZ_S:
430 case CSKY::f2FCMPNEZ_D:
431 case CSKY::f2FCMPUOZ_S:
432 case CSKY::f2FCMPUOZ_D:
433
434 case CSKY::BT32:
435 case CSKY::BF32:
436 case CSKY::BT16:
437 case CSKY::BF16:
438 case CSKY::CMPNEI32:
439 case CSKY::CMPNEI16:
440 case CSKY::CMPNE32:
441 case CSKY::CMPNE16:
442 case CSKY::CMPHSI32:
443 case CSKY::CMPHSI16:
444 case CSKY::CMPHS32:
445 case CSKY::CMPHS16:
446 case CSKY::CMPLTI32:
447 case CSKY::CMPLTI16:
448 case CSKY::CMPLT32:
449 case CSKY::CMPLT16:
450 case CSKY::BTSTI32:
451 case CSKY::BTSTI16:
452 case CSKY::TSTNBZ32:
453 case CSKY::TSTNBZ16:
454 case CSKY::TST32:
455 case CSKY::TST16:
456 MI.insert(MI.begin(), MCOperand::createReg(CSKY::C));
457 return MCDisassembler::Success;
458 case CSKY::LSLC32:
459 case CSKY::LSRC32:
460 case CSKY::ASRC32:
461 MI.insert(std::next(MI.begin()), MCOperand::createReg(CSKY::C));
462 return MCDisassembler::Success;
463 case CSKY::MOVF32:
464 case CSKY::MOVT32:
465 case CSKY::MVC32:
466 case CSKY::MVCV32:
467 case CSKY::MVCV16:
468 case CSKY::INCT32:
469 case CSKY::INCF32:
470 case CSKY::DECT32:
471 case CSKY::DECF32:
472 case CSKY::DECGT32:
473 case CSKY::DECLT32:
474 case CSKY::DECNE32:
475 case CSKY::CLRF32:
476 case CSKY::CLRT32:
477 case CSKY::f2FSEL_S:
478 case CSKY::f2FSEL_D:
479 MI.insert(std::next(MI.begin()), MCOperand::createReg(CSKY::C));
480 return MCDisassembler::Success;
481 case CSKY::ADDC32:
482 case CSKY::ADDC16:
483 case CSKY::SUBC32:
484 case CSKY::SUBC16:
485 case CSKY::XSR32:
486 MI.insert(std::next(MI.begin()), MCOperand::createReg(CSKY::C));
487 MI.insert(MI.end(), MCOperand::createReg(CSKY::C));
488 return MCDisassembler::Success;
489 case CSKY::INS32:
490 MI.getOperand(3).setImm(MI.getOperand(3).getImm() +
491 MI.getOperand(4).getImm());
492 return MCDisassembler::Success;
493 }
494}
495
496static bool decodeFPUV3Instruction(MCInst &MI, uint32_t insn, uint64_t Address,
497 const MCDisassembler *DisAsm,
498 const MCSubtargetInfo &STI) {
499 LLVM_DEBUG(dbgs() << "Trying CSKY 32-bit fpuv3 table :\n");
500 if (!STI.hasFeature(CSKY::FeatureFPUV3_HF) &&
501 !STI.hasFeature(CSKY::FeatureFPUV3_SF) &&
502 !STI.hasFeature(CSKY::FeatureFPUV3_DF))
503 return false;
504
505 DecodeStatus Result =
506 decodeInstruction(DecoderTableFPUV332, MI, insn, Address, DisAsm, STI);
507
508 if (Result == MCDisassembler::Fail) {
509 MI.clear();
510 return false;
511 }
512
513 return true;
514}
515
516DecodeStatus CSKYDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
517 ArrayRef<uint8_t> Bytes,
518 uint64_t Address,
519 raw_ostream &CS) const {
520
521 uint32_t Insn;
522 DecodeStatus Result = MCDisassembler::Fail;
523
524 Insn = support::endian::read16le(Bytes.data());
525
526 if ((Insn >> 14) == 0x3) {
527 if (Bytes.size() < 4) {
528 Size = 0;
529 return MCDisassembler::Fail;
530 }
531 Insn = (Insn << 16) | support::endian::read16le(&Bytes[2]);
532
533 if (decodeFPUV3Instruction(MI, Insn, Address, this, STI))
534 Result = MCDisassembler::Success;
535 else {
536 LLVM_DEBUG(dbgs() << "Trying CSKY 32-bit table :\n");
537 Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
538 }
539
540 Size = 4;
541 } else {
542 if (Bytes.size() < 2) {
543 Size = 0;
544 return MCDisassembler::Fail;
545 }
546 LLVM_DEBUG(dbgs() << "Trying CSKY 16-bit table :\n");
547 Result = decodeInstruction(DecoderTable16, MI, Insn, Address, this, STI);
548 Size = 2;
549 }
550
551 handleCROperand(MI);
552
553 return Result;
554}
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
GPRPairDecoderTable
static const uint16_t GPRPairDecoderTable[]
Definition: CSKYDisassembler.cpp:73
DecodesFPR128RegisterClass
static LLVM_ATTRIBUTE_UNUSED DecodeStatus DecodesFPR128RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:171
DecodeGPRPairRegisterClass
static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:213
DecodeStatus
MCDisassembler::DecodeStatus DecodeStatus
Definition: CSKYDisassembler.cpp:32
FPR32DecoderTable
static const uint16_t FPR32DecoderTable[]
Definition: CSKYDisassembler.cpp:82
DecodeRegSeqOperandF2
static DecodeStatus DecodeRegSeqOperandF2(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:328
DecodesFPR32RegisterClass
static DecodeStatus DecodesFPR32RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:129
LLVMInitializeCSKYDisassembler
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeCSKYDisassembler()
Definition: CSKYDisassembler.cpp:61
decodeJMPIXImmOperand
static DecodeStatus decodeJMPIXImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:258
FPR128DecoderTable
static const uint16_t FPR128DecoderTable[]
Definition: CSKYDisassembler.cpp:100
createCSKYDisassembler
static MCDisassembler * createCSKYDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: CSKYDisassembler.cpp:55
DecodeFPR64RegisterClass
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:159
DecodeRegSeqOperand
static DecodeStatus DecodeRegSeqOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:277
decodeLRW16Imm8
static DecodeStatus decodeLRW16Imm8(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:245
decodeUImmOperand
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:228
DecodeRegSeqOperandF1
static DecodeStatus DecodeRegSeqOperandF1(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:294
DecodesGPRRegisterClass
static DecodeStatus DecodesGPRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:181
DecodeRegSeqOperandD2
static DecodeStatus DecodeRegSeqOperandD2(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:345
DecodeGPRSPRegisterClass
static LLVM_ATTRIBUTE_UNUSED DecodeStatus DecodeGPRSPRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:203
DecodeGPRRegisterClass
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:109
decodeOImmOperand
static DecodeStatus decodeOImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:237
DecodeFPR32RegisterClass
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:119
decodeImmShiftOpValue
static DecodeStatus decodeImmShiftOpValue(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:362
DecodesFPR64_VRegisterClass
static DecodeStatus DecodesFPR64_VRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:149
DecodeRegSeqOperandD1
static DecodeStatus DecodeRegSeqOperandD1(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:311
DecodemGPRRegisterClass
static DecodeStatus DecodemGPRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:191
GPRDecoderTable
static const uint16_t GPRDecoderTable[]
Definition: CSKYDisassembler.cpp:66
decodeFPUV3Instruction
static bool decodeFPUV3Instruction(MCInst &MI, uint32_t insn, uint64_t Address, const MCDisassembler *DisAsm, const MCSubtargetInfo &STI)
Definition: CSKYDisassembler.cpp:496
decodeSImmOperand
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:370
FPR64DecoderTable
static const uint16_t FPR64DecoderTable[]
Definition: CSKYDisassembler.cpp:91
DecodesFPR64RegisterClass
static DecodeStatus DecodesFPR64RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:139
LLVM_ATTRIBUTE_UNUSED
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:298
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:132
DenseMap.h
This file defines the DenseMap class.
Size
uint64_t Size
Definition: ELFObjHandler.cpp:81
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:110
LLVM_DEBUG
#define LLVM_DEBUG(...)
Definition: Debug.h:119
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:147
llvm::ArrayRef::data
const T * data() const
Definition: ArrayRef.h:144
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:42
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:83
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:85
llvm::MCDisassembler::getSubtargetInfo
const MCSubtargetInfo & getSubtargetInfo() const
Definition: MCDisassembler.h:230
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:109
llvm::MCDisassembler::getInstruction
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:188
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:215
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:27
llvm::MCOperand::createReg
static MCOperand createReg(MCRegister Reg)
Definition: MCInst.h:138
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:145
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:77
llvm::MCSubtargetInfo::hasFeature
bool hasFeature(unsigned Feature) const
Definition: MCSubtargetInfo.h:122
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:115
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:55
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:146
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
uint16_t
uint32_t
uint64_t
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::support::endian::read16le
uint16_t read16le(const void *P)
Definition: Endian.h:426
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::Log2_64
unsigned Log2_64(uint64_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:342
llvm::dbgs
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:207
llvm::getTheCSKYTarget
Target & getTheCSKYTarget()
Definition: CSKYTargetInfo.cpp:13
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition: TargetRegistry.h:897
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