LLVM 22.0.0git
MipsDisassembler.cpp
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1//===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file is part of the Mips Disassembler.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MCTargetDesc/MipsMCTargetDesc.h"
14#include "TargetInfo/MipsTargetInfo.h"
15#include "llvm/ADT/ArrayRef.h"
16#include "llvm/MC/MCContext.h"
17#include "llvm/MC/MCDecoder.h"
18#include "llvm/MC/MCDecoderOps.h"
19#include "llvm/MC/MCDisassembler/MCDisassembler.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCRegisterInfo.h"
22#include "llvm/MC/MCSubtargetInfo.h"
23#include "llvm/MC/TargetRegistry.h"
24#include "llvm/Support/Compiler.h"
25#include "llvm/Support/Debug.h"
26#include "llvm/Support/ErrorHandling.h"
27#include "llvm/Support/MathExtras.h"
28#include "llvm/Support/raw_ostream.h"
29#include <cassert>
30#include <cstdint>
31
32using namespace llvm;
33using namespace llvm::MCD;
34
35#define DEBUG_TYPE "mips-disassembler"
36
37using DecodeStatus = MCDisassembler::DecodeStatus;
38
39namespace {
40
41class MipsDisassembler : public MCDisassembler {
42 bool IsMicroMips;
43 bool IsBigEndian;
44
45public:
46 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian)
47 : MCDisassembler(STI, Ctx),
48 IsMicroMips(STI.hasFeature(Mips::FeatureMicroMips)),
49 IsBigEndian(IsBigEndian) {}
50
51 bool hasMips2() const { return STI.hasFeature(Mips::FeatureMips2); }
52 bool hasMips3() const { return STI.hasFeature(Mips::FeatureMips3); }
53 bool hasMips32() const { return STI.hasFeature(Mips::FeatureMips32); }
54
55 bool hasMips32r6() const {
56 return STI.hasFeature(Mips::FeatureMips32r6);
57 }
58
59 bool isFP64() const { return STI.hasFeature(Mips::FeatureFP64Bit); }
60
61 bool isGP64() const { return STI.hasFeature(Mips::FeatureGP64Bit); }
62
63 bool isPTR64() const { return STI.hasFeature(Mips::FeaturePTR64Bit); }
64
65 bool hasCnMips() const { return STI.hasFeature(Mips::FeatureCnMips); }
66
67 bool hasCnMipsP() const { return STI.hasFeature(Mips::FeatureCnMipsP); }
68
69 bool hasCOP3() const {
70 // Only present in MIPS-I and MIPS-II
71 return !hasMips32() && !hasMips3();
72 }
73
74 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
75 ArrayRef<uint8_t> Bytes, uint64_t Address,
76 raw_ostream &CStream) const override;
77};
78
79} // end anonymous namespace
80
81static MCDisassembler *createMipsDisassembler(const Target &T,
82 const MCSubtargetInfo &STI,
83 MCContext &Ctx) {
84 return new MipsDisassembler(STI, Ctx, true);
85}
86
87static MCDisassembler *createMipselDisassembler(const Target &T,
88 const MCSubtargetInfo &STI,
89 MCContext &Ctx) {
90 return new MipsDisassembler(STI, Ctx, false);
91}
92
93extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
94LLVMInitializeMipsDisassembler() {
95 // Register the disassembler.
96 TargetRegistry::RegisterMCDisassembler(getTheMipsTarget(),
97 createMipsDisassembler);
98 TargetRegistry::RegisterMCDisassembler(getTheMipselTarget(),
99 createMipselDisassembler);
100 TargetRegistry::RegisterMCDisassembler(getTheMips64Target(),
101 createMipsDisassembler);
102 TargetRegistry::RegisterMCDisassembler(getTheMips64elTarget(),
103 createMipselDisassembler);
104}
105
106static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo) {
107 const MCRegisterInfo *RegInfo = D->getContext().getRegisterInfo();
108 return *(RegInfo->getRegClass(RC).begin() + RegNo);
109}
110static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, unsigned RegNo,
111 uint64_t Address,
112 const MCDisassembler *Decoder) {
113 // Currently only hardware register 29 is supported.
114 if (RegNo != 29)
115 return MCDisassembler::Fail;
116 Inst.addOperand(MCOperand::createReg(Mips::HWR29));
117 return MCDisassembler::Success;
118}
119
120static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo,
121 uint64_t Address,
122 const MCDisassembler *Decoder) {
123 if (RegNo > 30 || RegNo % 2)
124 return MCDisassembler::Fail;
125
126 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo / 2);
127 Inst.addOperand(MCOperand::createReg(Reg));
128 return MCDisassembler::Success;
129}
130
131static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo,
132 uint64_t Address,
133 const MCDisassembler *Decoder) {
134 if (RegNo >= 4)
135 return MCDisassembler::Fail;
136
137 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
138 Inst.addOperand(MCOperand::createReg(Reg));
139 return MCDisassembler::Success;
140}
141
142static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo,
143 uint64_t Address,
144 const MCDisassembler *Decoder) {
145 if (RegNo >= 4)
146 return MCDisassembler::Fail;
147
148 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
149 Inst.addOperand(MCOperand::createReg(Reg));
150 return MCDisassembler::Success;
151}
152
153static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo,
154 uint64_t Address,
155 const MCDisassembler *Decoder) {
156 if (RegNo >= 4)
157 return MCDisassembler::Fail;
158
159 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
160 Inst.addOperand(MCOperand::createReg(Reg));
161 return MCDisassembler::Success;
162}
163
164static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo,
165 uint64_t Address,
166 const MCDisassembler *Decoder) {
167 if (RegNo > 31)
168 return MCDisassembler::Fail;
169
170 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
171 Inst.addOperand(MCOperand::createReg(Reg));
172 return MCDisassembler::Success;
173}
174
175static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo,
176 uint64_t Address,
177 const MCDisassembler *Decoder) {
178 if (RegNo > 31)
179 return MCDisassembler::Fail;
180
181 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
182 Inst.addOperand(MCOperand::createReg(Reg));
183 return MCDisassembler::Success;
184}
185
186static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo,
187 uint64_t Address,
188 const MCDisassembler *Decoder) {
189 if (RegNo > 31)
190 return MCDisassembler::Fail;
191
192 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
193 Inst.addOperand(MCOperand::createReg(Reg));
194 return MCDisassembler::Success;
195}
196
197static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo,
198 uint64_t Address,
199 const MCDisassembler *Decoder) {
200 if (RegNo > 31)
201 return MCDisassembler::Fail;
202
203 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
204 Inst.addOperand(MCOperand::createReg(Reg));
205 return MCDisassembler::Success;
206}
207
208static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo,
209 uint64_t Address,
210 const MCDisassembler *Decoder) {
211 if (RegNo > 7)
212 return MCDisassembler::Fail;
213
214 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
215 Inst.addOperand(MCOperand::createReg(Reg));
216 return MCDisassembler::Success;
217}
218
219static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, unsigned RegNo,
220 uint64_t Address,
221 const MCDisassembler *Decoder) {
222 if (RegNo > 31)
223 return MCDisassembler::Fail;
224
225 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo);
226 Inst.addOperand(MCOperand::createReg(Reg));
227 return MCDisassembler::Success;
228}
229
230static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo,
231 uint64_t Address,
232 const MCDisassembler *Decoder) {
233 if (RegNo > 31)
234 return MCDisassembler::Fail;
235
236 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
237 Inst.addOperand(MCOperand::createReg(Reg));
238 return MCDisassembler::Success;
239}
240
241static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
242 uint64_t Address,
243 const MCDisassembler *Decoder) {
244 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4,
245 Mips::S5, Mips::S6, Mips::S7, Mips::FP};
246 unsigned RegNum;
247
248 unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
249
250 // Empty register lists are not allowed.
251 if (RegLst == 0)
252 return MCDisassembler::Fail;
253
254 RegNum = RegLst & 0xf;
255
256 // RegLst values 10-15, and 26-31 are reserved.
257 if (RegNum > 9)
258 return MCDisassembler::Fail;
259
260 for (unsigned i = 0; i < RegNum; i++)
261 Inst.addOperand(MCOperand::createReg(Regs[i]));
262
263 if (RegLst & 0x10)
264 Inst.addOperand(MCOperand::createReg(Mips::RA));
265
266 return MCDisassembler::Success;
267}
268
269static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
270 uint64_t Address,
271 const MCDisassembler *Decoder) {
272 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
273 unsigned RegLst;
274 switch (Inst.getOpcode()) {
275 default:
276 RegLst = fieldFromInstruction(Insn, 4, 2);
277 break;
278 case Mips::LWM16_MMR6:
279 case Mips::SWM16_MMR6:
280 RegLst = fieldFromInstruction(Insn, 8, 2);
281 break;
282 }
283 unsigned RegNum = RegLst & 0x3;
284
285 for (unsigned i = 0; i <= RegNum; i++)
286 Inst.addOperand(MCOperand::createReg(Regs[i]));
287
288 Inst.addOperand(MCOperand::createReg(Mips::RA));
289
290 return MCDisassembler::Success;
291}
292
293template <typename InsnType>
294static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
295 const MCDisassembler *Decoder) {
296 using DecodeFN =
297 DecodeStatus (*)(MCInst &, unsigned, uint64_t, const MCDisassembler *);
298
299 // The size of the n field depends on the element size
300 // The register class also depends on this.
301 InsnType tmp = fieldFromInstruction(insn, 17, 5);
302 unsigned NSize = 0;
303 DecodeFN RegDecoder = nullptr;
304 if ((tmp & 0x18) == 0x00) { // INSVE_B
305 NSize = 4;
306 RegDecoder = DecodeMSA128BRegisterClass;
307 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
308 NSize = 3;
309 RegDecoder = DecodeMSA128HRegisterClass;
310 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
311 NSize = 2;
312 RegDecoder = DecodeMSA128WRegisterClass;
313 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
314 NSize = 1;
315 RegDecoder = DecodeMSA128DRegisterClass;
316 } else
317 llvm_unreachable("Invalid encoding");
318
319 assert(NSize != 0 && RegDecoder != nullptr);
320
321 // $wd
322 tmp = fieldFromInstruction(insn, 6, 5);
323 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
324 return MCDisassembler::Fail;
325 // $wd_in
326 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
327 return MCDisassembler::Fail;
328 // $n
329 tmp = fieldFromInstruction(insn, 16, NSize);
330 MI.addOperand(MCOperand::createImm(tmp));
331 // $ws
332 tmp = fieldFromInstruction(insn, 11, 5);
333 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
334 return MCDisassembler::Fail;
335 // $n2
336 MI.addOperand(MCOperand::createImm(0));
337
338 return MCDisassembler::Success;
339}
340
341template <typename InsnType>
342static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn,
343 uint64_t Address,
344 const MCDisassembler *Decoder) {
345 InsnType Rs = fieldFromInstruction(insn, 16, 5);
346 InsnType Imm = fieldFromInstruction(insn, 0, 16);
347 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
348 Rs)));
349 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
350 Rs)));
351 MI.addOperand(MCOperand::createImm(Imm));
352
353 return MCDisassembler::Success;
354}
355
356template <typename InsnType>
357static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
358 const MCDisassembler *Decoder) {
359 InsnType Rs = fieldFromInstruction(insn, 21, 5);
360 InsnType Imm = fieldFromInstruction(insn, 0, 16);
361 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
362 Rs)));
363 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
364 Rs)));
365 MI.addOperand(MCOperand::createImm(Imm));
366
367 return MCDisassembler::Success;
368}
369
370template <typename InsnType>
371static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
372 uint64_t Address,
373 const MCDisassembler *Decoder) {
374 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
375 // (otherwise we would have matched the ADDI instruction from the earlier
376 // ISA's instead).
377 //
378 // We have:
379 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii
380 // BOVC if rs >= rt
381 // BEQZALC if rs == 0 && rt != 0
382 // BEQC if rs < rt && rs != 0
383
384 InsnType Rs = fieldFromInstruction(insn, 21, 5);
385 InsnType Rt = fieldFromInstruction(insn, 16, 5);
386 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
387 bool HasRs = false;
388
389 if (Rs >= Rt) {
390 MI.setOpcode(Mips::BOVC);
391 HasRs = true;
392 } else if (Rs != 0 && Rs < Rt) {
393 MI.setOpcode(Mips::BEQC);
394 HasRs = true;
395 } else
396 MI.setOpcode(Mips::BEQZALC);
397
398 if (HasRs)
399 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
400 Rs)));
401
402 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
403 Rt)));
404 MI.addOperand(MCOperand::createImm(Imm));
405
406 return MCDisassembler::Success;
407}
408
409template <typename InsnType>
410static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn,
411 uint64_t Address,
412 const MCDisassembler *Decoder) {
413 InsnType Rt = fieldFromInstruction(insn, 21, 5);
414 InsnType Rs = fieldFromInstruction(insn, 16, 5);
415 int64_t Imm = 0;
416
417 if (Rs >= Rt) {
418 MI.setOpcode(Mips::BOVC_MMR6);
419 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
420 Rt)));
421 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
422 Rs)));
423 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
424 } else if (Rs != 0 && Rs < Rt) {
425 MI.setOpcode(Mips::BEQC_MMR6);
426 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
427 Rs)));
428 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
429 Rt)));
430 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
431 } else {
432 MI.setOpcode(Mips::BEQZALC_MMR6);
433 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
434 Rt)));
435 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
436 }
437
438 MI.addOperand(MCOperand::createImm(Imm));
439
440 return MCDisassembler::Success;
441}
442
443template <typename InsnType>
444static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
445 uint64_t Address,
446 const MCDisassembler *Decoder) {
447 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
448 // (otherwise we would have matched the ADDI instruction from the earlier
449 // ISA's instead).
450 //
451 // We have:
452 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii
453 // BNVC if rs >= rt
454 // BNEZALC if rs == 0 && rt != 0
455 // BNEC if rs < rt && rs != 0
456
457 InsnType Rs = fieldFromInstruction(insn, 21, 5);
458 InsnType Rt = fieldFromInstruction(insn, 16, 5);
459 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
460 bool HasRs = false;
461
462 if (Rs >= Rt) {
463 MI.setOpcode(Mips::BNVC);
464 HasRs = true;
465 } else if (Rs != 0 && Rs < Rt) {
466 MI.setOpcode(Mips::BNEC);
467 HasRs = true;
468 } else
469 MI.setOpcode(Mips::BNEZALC);
470
471 if (HasRs)
472 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
473 Rs)));
474
475 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
476 Rt)));
477 MI.addOperand(MCOperand::createImm(Imm));
478
479 return MCDisassembler::Success;
480}
481
482template <typename InsnType>
483static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn,
484 uint64_t Address,
485 const MCDisassembler *Decoder) {
486 InsnType Rt = fieldFromInstruction(insn, 21, 5);
487 InsnType Rs = fieldFromInstruction(insn, 16, 5);
488 int64_t Imm = 0;
489
490 if (Rs >= Rt) {
491 MI.setOpcode(Mips::BNVC_MMR6);
492 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
493 Rt)));
494 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
495 Rs)));
496 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
497 } else if (Rs != 0 && Rs < Rt) {
498 MI.setOpcode(Mips::BNEC_MMR6);
499 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
500 Rs)));
501 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
502 Rt)));
503 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
504 } else {
505 MI.setOpcode(Mips::BNEZALC_MMR6);
506 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
507 Rt)));
508 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
509 }
510
511 MI.addOperand(MCOperand::createImm(Imm));
512
513 return MCDisassembler::Success;
514}
515
516template <typename InsnType>
517static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn,
518 uint64_t Address,
519 const MCDisassembler *Decoder) {
520 // We have:
521 // 0b110101 ttttt sssss iiiiiiiiiiiiiiii
522 // Invalid if rt == 0
523 // BGTZC_MMR6 if rs == 0 && rt != 0
524 // BLTZC_MMR6 if rs == rt && rt != 0
525 // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0
526
527 InsnType Rt = fieldFromInstruction(insn, 21, 5);
528 InsnType Rs = fieldFromInstruction(insn, 16, 5);
529 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
530 bool HasRs = false;
531
532 if (Rt == 0)
533 return MCDisassembler::Fail;
534 else if (Rs == 0)
535 MI.setOpcode(Mips::BGTZC_MMR6);
536 else if (Rs == Rt)
537 MI.setOpcode(Mips::BLTZC_MMR6);
538 else {
539 MI.setOpcode(Mips::BLTC_MMR6);
540 HasRs = true;
541 }
542
543 if (HasRs)
544 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
545 Rs)));
546
547 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
548 Rt)));
549
550 MI.addOperand(MCOperand::createImm(Imm));
551
552 return MCDisassembler::Success;
553}
554
555template <typename InsnType>
556static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn,
557 uint64_t Address,
558 const MCDisassembler *Decoder) {
559 // We have:
560 // 0b111101 ttttt sssss iiiiiiiiiiiiiiii
561 // Invalid if rt == 0
562 // BLEZC_MMR6 if rs == 0 && rt != 0
563 // BGEZC_MMR6 if rs == rt && rt != 0
564 // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0
565
566 InsnType Rt = fieldFromInstruction(insn, 21, 5);
567 InsnType Rs = fieldFromInstruction(insn, 16, 5);
568 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
569 bool HasRs = false;
570
571 if (Rt == 0)
572 return MCDisassembler::Fail;
573 else if (Rs == 0)
574 MI.setOpcode(Mips::BLEZC_MMR6);
575 else if (Rs == Rt)
576 MI.setOpcode(Mips::BGEZC_MMR6);
577 else {
578 HasRs = true;
579 MI.setOpcode(Mips::BGEC_MMR6);
580 }
581
582 if (HasRs)
583 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
584 Rs)));
585
586 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
587 Rt)));
588
589 MI.addOperand(MCOperand::createImm(Imm));
590
591 return MCDisassembler::Success;
592}
593
594template <typename InsnType>
595static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
596 uint64_t Address,
597 const MCDisassembler *Decoder) {
598 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
599 // (otherwise we would have matched the BLEZL instruction from the earlier
600 // ISA's instead).
601 //
602 // We have:
603 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii
604 // Invalid if rs == 0
605 // BLEZC if rs == 0 && rt != 0
606 // BGEZC if rs == rt && rt != 0
607 // BGEC if rs != rt && rs != 0 && rt != 0
608
609 InsnType Rs = fieldFromInstruction(insn, 21, 5);
610 InsnType Rt = fieldFromInstruction(insn, 16, 5);
611 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
612 bool HasRs = false;
613
614 if (Rt == 0)
615 return MCDisassembler::Fail;
616 else if (Rs == 0)
617 MI.setOpcode(Mips::BLEZC);
618 else if (Rs == Rt)
619 MI.setOpcode(Mips::BGEZC);
620 else {
621 HasRs = true;
622 MI.setOpcode(Mips::BGEC);
623 }
624
625 if (HasRs)
626 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
627 Rs)));
628
629 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
630 Rt)));
631
632 MI.addOperand(MCOperand::createImm(Imm));
633
634 return MCDisassembler::Success;
635}
636
637template <typename InsnType>
638static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
639 uint64_t Address,
640 const MCDisassembler *Decoder) {
641 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
642 // (otherwise we would have matched the BGTZL instruction from the earlier
643 // ISA's instead).
644 //
645 // We have:
646 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii
647 // Invalid if rs == 0
648 // BGTZC if rs == 0 && rt != 0
649 // BLTZC if rs == rt && rt != 0
650 // BLTC if rs != rt && rs != 0 && rt != 0
651
652 bool HasRs = false;
653
654 InsnType Rs = fieldFromInstruction(insn, 21, 5);
655 InsnType Rt = fieldFromInstruction(insn, 16, 5);
656 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
657
658 if (Rt == 0)
659 return MCDisassembler::Fail;
660 else if (Rs == 0)
661 MI.setOpcode(Mips::BGTZC);
662 else if (Rs == Rt)
663 MI.setOpcode(Mips::BLTZC);
664 else {
665 MI.setOpcode(Mips::BLTC);
666 HasRs = true;
667 }
668
669 if (HasRs)
670 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
671 Rs)));
672
673 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
674 Rt)));
675
676 MI.addOperand(MCOperand::createImm(Imm));
677
678 return MCDisassembler::Success;
679}
680
681template <typename InsnType>
682static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
683 uint64_t Address,
684 const MCDisassembler *Decoder) {
685 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
686 // (otherwise we would have matched the BGTZ instruction from the earlier
687 // ISA's instead).
688 //
689 // We have:
690 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii
691 // BGTZ if rt == 0
692 // BGTZALC if rs == 0 && rt != 0
693 // BLTZALC if rs != 0 && rs == rt
694 // BLTUC if rs != 0 && rs != rt
695
696 InsnType Rs = fieldFromInstruction(insn, 21, 5);
697 InsnType Rt = fieldFromInstruction(insn, 16, 5);
698 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
699 bool HasRs = false;
700 bool HasRt = false;
701
702 if (Rt == 0) {
703 MI.setOpcode(Mips::BGTZ);
704 HasRs = true;
705 } else if (Rs == 0) {
706 MI.setOpcode(Mips::BGTZALC);
707 HasRt = true;
708 } else if (Rs == Rt) {
709 MI.setOpcode(Mips::BLTZALC);
710 HasRs = true;
711 } else {
712 MI.setOpcode(Mips::BLTUC);
713 HasRs = true;
714 HasRt = true;
715 }
716
717 if (HasRs)
718 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
719 Rs)));
720
721 if (HasRt)
722 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
723 Rt)));
724
725 MI.addOperand(MCOperand::createImm(Imm));
726
727 return MCDisassembler::Success;
728}
729
730template <typename InsnType>
731static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
732 uint64_t Address,
733 const MCDisassembler *Decoder) {
734 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
735 // (otherwise we would have matched the BLEZL instruction from the earlier
736 // ISA's instead).
737 //
738 // We have:
739 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii
740 // Invalid if rs == 0
741 // BLEZALC if rs == 0 && rt != 0
742 // BGEZALC if rs == rt && rt != 0
743 // BGEUC if rs != rt && rs != 0 && rt != 0
744
745 InsnType Rs = fieldFromInstruction(insn, 21, 5);
746 InsnType Rt = fieldFromInstruction(insn, 16, 5);
747 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
748 bool HasRs = false;
749
750 if (Rt == 0)
751 return MCDisassembler::Fail;
752 else if (Rs == 0)
753 MI.setOpcode(Mips::BLEZALC);
754 else if (Rs == Rt)
755 MI.setOpcode(Mips::BGEZALC);
756 else {
757 HasRs = true;
758 MI.setOpcode(Mips::BGEUC);
759 }
760
761 if (HasRs)
762 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
763 Rs)));
764 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
765 Rt)));
766
767 MI.addOperand(MCOperand::createImm(Imm));
768
769 return MCDisassembler::Success;
770}
771
772// Override the generated disassembler to produce DEXT all the time. This is
773// for feature / behaviour parity with binutils.
774template <typename InsnType>
775static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address,
776 const MCDisassembler *Decoder) {
777 unsigned Msbd = fieldFromInstruction(Insn, 11, 5);
778 unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
779 unsigned Size = 0;
780 unsigned Pos = 0;
781
782 switch (MI.getOpcode()) {
783 case Mips::DEXT:
784 Pos = Lsb;
785 Size = Msbd + 1;
786 break;
787 case Mips::DEXTM:
788 Pos = Lsb;
789 Size = Msbd + 1 + 32;
790 break;
791 case Mips::DEXTU:
792 Pos = Lsb + 32;
793 Size = Msbd + 1;
794 break;
795 default:
796 llvm_unreachable("Unknown DEXT instruction!");
797 }
798
799 MI.setOpcode(Mips::DEXT);
800
801 InsnType Rs = fieldFromInstruction(Insn, 21, 5);
802 InsnType Rt = fieldFromInstruction(Insn, 16, 5);
803
804 MI.addOperand(
805 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
806 MI.addOperand(
807 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
808 MI.addOperand(MCOperand::createImm(Pos));
809 MI.addOperand(MCOperand::createImm(Size));
810
811 return MCDisassembler::Success;
812}
813
814// Override the generated disassembler to produce DINS all the time. This is
815// for feature / behaviour parity with binutils.
816template <typename InsnType>
817static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address,
818 const MCDisassembler *Decoder) {
819 unsigned Msbd = fieldFromInstruction(Insn, 11, 5);
820 unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
821 unsigned Size = 0;
822 unsigned Pos = 0;
823
824 switch (MI.getOpcode()) {
825 case Mips::DINS:
826 Pos = Lsb;
827 Size = Msbd + 1 - Pos;
828 break;
829 case Mips::DINSM:
830 Pos = Lsb;
831 Size = Msbd + 33 - Pos;
832 break;
833 case Mips::DINSU:
834 Pos = Lsb + 32;
835 // mbsd = pos + size - 33
836 // mbsd - pos + 33 = size
837 Size = Msbd + 33 - Pos;
838 break;
839 default:
840 llvm_unreachable("Unknown DINS instruction!");
841 }
842
843 InsnType Rs = fieldFromInstruction(Insn, 21, 5);
844 InsnType Rt = fieldFromInstruction(Insn, 16, 5);
845
846 MI.setOpcode(Mips::DINS);
847 MI.addOperand(
848 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
849 MI.addOperand(
850 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
851 MI.addOperand(MCOperand::createImm(Pos));
852 MI.addOperand(MCOperand::createImm(Size));
853
854 return MCDisassembler::Success;
855}
856
857// Auto-generated decoder wouldn't add the third operand for CRC32*.
858template <typename InsnType>
859static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address,
860 const MCDisassembler *Decoder) {
861 InsnType Rs = fieldFromInstruction(Insn, 21, 5);
862 InsnType Rt = fieldFromInstruction(Insn, 16, 5);
863 MI.addOperand(
864 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));
865 MI.addOperand(
866 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs)));
867 MI.addOperand(
868 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));
869 return MCDisassembler::Success;
870}
871
872static DecodeStatus
873DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
874 const MCDisassembler *Decoder) {
875 return MCDisassembler::Fail;
876}
877
878static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
879 uint64_t Address,
880 const MCDisassembler *Decoder) {
881 if (RegNo > 31)
882 return MCDisassembler::Fail;
883
884 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
885 Inst.addOperand(MCOperand::createReg(Reg));
886 return MCDisassembler::Success;
887}
888
889static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo,
890 uint64_t Address,
891 const MCDisassembler *Decoder) {
892 if (RegNo > 7)
893 return MCDisassembler::Fail;
894 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
895 Inst.addOperand(MCOperand::createReg(Reg));
896 return MCDisassembler::Success;
897}
898
899static DecodeStatus
900DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
901 const MCDisassembler *Decoder) {
902 if (RegNo > 7)
903 return MCDisassembler::Fail;
904 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
905 Inst.addOperand(MCOperand::createReg(Reg));
906 return MCDisassembler::Success;
907}
908
909static DecodeStatus
910DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
911 const MCDisassembler *Decoder) {
912 if (RegNo > 7)
913 return MCDisassembler::Fail;
914 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo);
915 Inst.addOperand(MCOperand::createReg(Reg));
916 return MCDisassembler::Success;
917}
918
919static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
920 uint64_t Address,
921 const MCDisassembler *Decoder) {
922 if (RegNo > 31)
923 return MCDisassembler::Fail;
924 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
925 Inst.addOperand(MCOperand::createReg(Reg));
926 return MCDisassembler::Success;
927}
928
929static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, unsigned RegNo,
930 uint64_t Address,
931 const MCDisassembler *Decoder) {
932 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
933 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
934
935 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
936}
937
938static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo,
939 uint64_t Address,
940 const MCDisassembler *Decoder) {
941 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
942}
943
944static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo,
945 uint64_t Address,
946 const MCDisassembler *Decoder) {
947 if (RegNo > 31)
948 return MCDisassembler::Fail;
949
950 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
951 Inst.addOperand(MCOperand::createReg(Reg));
952 return MCDisassembler::Success;
953}
954
955static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo,
956 uint64_t Address,
957 const MCDisassembler *Decoder) {
958 if (RegNo > 31)
959 return MCDisassembler::Fail;
960
961 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
962 Inst.addOperand(MCOperand::createReg(Reg));
963 return MCDisassembler::Success;
964}
965
966static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo,
967 uint64_t Address,
968 const MCDisassembler *Decoder) {
969 if (RegNo > 31)
970 return MCDisassembler::Fail;
971 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
972 Inst.addOperand(MCOperand::createReg(Reg));
973 return MCDisassembler::Success;
974}
975
976static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo,
977 uint64_t Address,
978 const MCDisassembler *Decoder) {
979 if (RegNo > 7)
980 return MCDisassembler::Fail;
981 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
982 Inst.addOperand(MCOperand::createReg(Reg));
983 return MCDisassembler::Success;
984}
985
986static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
987 uint64_t Address,
988 const MCDisassembler *Decoder) {
989 if (RegNo > 31)
990 return MCDisassembler::Fail;
991
992 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
993 Inst.addOperand(MCOperand::createReg(Reg));
994 return MCDisassembler::Success;
995}
996
997static DecodeStatus DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address,
998 const MCDisassembler *Decoder) {
999 int Offset = SignExtend32<16>(Insn & 0xffff);
1000 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1001 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1002
1003 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1004 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1005
1006 if (Inst.getOpcode() == Mips::SC ||
1007 Inst.getOpcode() == Mips::SCD)
1008 Inst.addOperand(MCOperand::createReg(Reg));
1009
1010 Inst.addOperand(MCOperand::createReg(Reg));
1011 Inst.addOperand(MCOperand::createReg(Base));
1012 Inst.addOperand(MCOperand::createImm(Offset));
1013
1014 return MCDisassembler::Success;
1015}
1016
1017static DecodeStatus DecodeMemEVA(MCInst &Inst, unsigned Insn, uint64_t Address,
1018 const MCDisassembler *Decoder) {
1019 int Offset = SignExtend32<9>(Insn >> 7);
1020 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1021 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1022
1023 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1024 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1025
1026 if (Inst.getOpcode() == Mips::SCE)
1027 Inst.addOperand(MCOperand::createReg(Reg));
1028
1029 Inst.addOperand(MCOperand::createReg(Reg));
1030 Inst.addOperand(MCOperand::createReg(Base));
1031 Inst.addOperand(MCOperand::createImm(Offset));
1032
1033 return MCDisassembler::Success;
1034}
1035
1036static DecodeStatus DecodeLoadByte15(MCInst &Inst, unsigned Insn,
1037 uint64_t Address,
1038 const MCDisassembler *Decoder) {
1039 int Offset = SignExtend32<16>(Insn & 0xffff);
1040 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1041 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1042
1043 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1044 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1045
1046 Inst.addOperand(MCOperand::createReg(Reg));
1047 Inst.addOperand(MCOperand::createReg(Base));
1048 Inst.addOperand(MCOperand::createImm(Offset));
1049
1050 return MCDisassembler::Success;
1051}
1052
1053static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address,
1054 const MCDisassembler *Decoder) {
1055 int Offset = SignExtend32<16>(Insn & 0xffff);
1056 unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1057 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1058
1059 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1060
1061 Inst.addOperand(MCOperand::createReg(Base));
1062 Inst.addOperand(MCOperand::createImm(Offset));
1063 Inst.addOperand(MCOperand::createImm(Hint));
1064
1065 return MCDisassembler::Success;
1066}
1067
1068static DecodeStatus DecodeCacheOpMM(MCInst &Inst, unsigned Insn,
1069 uint64_t Address,
1070 const MCDisassembler *Decoder) {
1071 int Offset = SignExtend32<12>(Insn & 0xfff);
1072 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1073 unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1074
1075 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1076
1077 Inst.addOperand(MCOperand::createReg(Base));
1078 Inst.addOperand(MCOperand::createImm(Offset));
1079 Inst.addOperand(MCOperand::createImm(Hint));
1080
1081 return MCDisassembler::Success;
1082}
1083
1084static DecodeStatus DecodePrefeOpMM(MCInst &Inst, unsigned Insn,
1085 uint64_t Address,
1086 const MCDisassembler *Decoder) {
1087 int Offset = SignExtend32<9>(Insn & 0x1ff);
1088 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1089 unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1090
1091 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1092
1093 Inst.addOperand(MCOperand::createReg(Base));
1094 Inst.addOperand(MCOperand::createImm(Offset));
1095 Inst.addOperand(MCOperand::createImm(Hint));
1096
1097 return MCDisassembler::Success;
1098}
1099
1100static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, unsigned Insn,
1101 uint64_t Address,
1102 const MCDisassembler *Decoder) {
1103 int Offset = SignExtend32<9>(Insn >> 7);
1104 unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1105 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1106
1107 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1108
1109 Inst.addOperand(MCOperand::createReg(Base));
1110 Inst.addOperand(MCOperand::createImm(Offset));
1111 Inst.addOperand(MCOperand::createImm(Hint));
1112
1113 return MCDisassembler::Success;
1114}
1115
1116static DecodeStatus DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address,
1117 const MCDisassembler *Decoder) {
1118 int Offset = SignExtend32<16>(Insn & 0xffff);
1119 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1120
1121 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1122
1123 Inst.addOperand(MCOperand::createReg(Base));
1124 Inst.addOperand(MCOperand::createImm(Offset));
1125
1126 return MCDisassembler::Success;
1127}
1128
1129static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn,
1130 uint64_t Address,
1131 const MCDisassembler *Decoder) {
1132 int Offset = SignExtend32<16>(Insn & 0xffff);
1133 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1134
1135 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1136
1137 Inst.addOperand(MCOperand::createReg(Base));
1138 Inst.addOperand(MCOperand::createImm(Offset));
1139
1140 return MCDisassembler::Success;
1141}
1142
1143static DecodeStatus DecodeSynciR6(MCInst &Inst, unsigned Insn, uint64_t Address,
1144 const MCDisassembler *Decoder) {
1145 int Immediate = SignExtend32<16>(Insn & 0xffff);
1146 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1147
1148 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1149
1150 Inst.addOperand(MCOperand::createReg(Base));
1151 Inst.addOperand(MCOperand::createImm(Immediate));
1152
1153 return MCDisassembler::Success;
1154}
1155
1156static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1157 uint64_t Address,
1158 const MCDisassembler *Decoder) {
1159 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1160 unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1161 unsigned Base = fieldFromInstruction(Insn, 11, 5);
1162
1163 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1164 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1165
1166 Inst.addOperand(MCOperand::createReg(Reg));
1167 Inst.addOperand(MCOperand::createReg(Base));
1168
1169 // The immediate field of an LD/ST instruction is scaled which means it must
1170 // be multiplied (when decoding) by the size (in bytes) of the instructions'
1171 // data format.
1172 // .b - 1 byte
1173 // .h - 2 bytes
1174 // .w - 4 bytes
1175 // .d - 8 bytes
1176 switch(Inst.getOpcode())
1177 {
1178 default:
1179 assert(false && "Unexpected instruction");
1180 return MCDisassembler::Fail;
1181 break;
1182 case Mips::LD_B:
1183 case Mips::ST_B:
1184 Inst.addOperand(MCOperand::createImm(Offset));
1185 break;
1186 case Mips::LD_H:
1187 case Mips::ST_H:
1188 Inst.addOperand(MCOperand::createImm(Offset * 2));
1189 break;
1190 case Mips::LD_W:
1191 case Mips::ST_W:
1192 Inst.addOperand(MCOperand::createImm(Offset * 4));
1193 break;
1194 case Mips::LD_D:
1195 case Mips::ST_D:
1196 Inst.addOperand(MCOperand::createImm(Offset * 8));
1197 break;
1198 }
1199
1200 return MCDisassembler::Success;
1201}
1202
1203static DecodeStatus DecodeMemMMImm4(MCInst &Inst, unsigned Insn,
1204 uint64_t Address,
1205 const MCDisassembler *Decoder) {
1206 unsigned Offset = Insn & 0xf;
1207 unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1208 unsigned Base = fieldFromInstruction(Insn, 4, 3);
1209
1210 switch (Inst.getOpcode()) {
1211 case Mips::LBU16_MM:
1212 case Mips::LHU16_MM:
1213 case Mips::LW16_MM:
1214 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1215 == MCDisassembler::Fail)
1216 return MCDisassembler::Fail;
1217 break;
1218 case Mips::SB16_MM:
1219 case Mips::SB16_MMR6:
1220 case Mips::SH16_MM:
1221 case Mips::SH16_MMR6:
1222 case Mips::SW16_MM:
1223 case Mips::SW16_MMR6:
1224 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1225 == MCDisassembler::Fail)
1226 return MCDisassembler::Fail;
1227 break;
1228 }
1229
1230 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1231 == MCDisassembler::Fail)
1232 return MCDisassembler::Fail;
1233
1234 switch (Inst.getOpcode()) {
1235 case Mips::LBU16_MM:
1236 if (Offset == 0xf)
1237 Inst.addOperand(MCOperand::createImm(-1));
1238 else
1239 Inst.addOperand(MCOperand::createImm(Offset));
1240 break;
1241 case Mips::SB16_MM:
1242 case Mips::SB16_MMR6:
1243 Inst.addOperand(MCOperand::createImm(Offset));
1244 break;
1245 case Mips::LHU16_MM:
1246 case Mips::SH16_MM:
1247 case Mips::SH16_MMR6:
1248 Inst.addOperand(MCOperand::createImm(Offset << 1));
1249 break;
1250 case Mips::LW16_MM:
1251 case Mips::SW16_MM:
1252 case Mips::SW16_MMR6:
1253 Inst.addOperand(MCOperand::createImm(Offset << 2));
1254 break;
1255 }
1256
1257 return MCDisassembler::Success;
1258}
1259
1260static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, unsigned Insn,
1261 uint64_t Address,
1262 const MCDisassembler *Decoder) {
1263 unsigned Offset = Insn & 0x1F;
1264 unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1265
1266 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1267
1268 Inst.addOperand(MCOperand::createReg(Reg));
1269 Inst.addOperand(MCOperand::createReg(Mips::SP));
1270 Inst.addOperand(MCOperand::createImm(Offset << 2));
1271
1272 return MCDisassembler::Success;
1273}
1274
1275static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, unsigned Insn,
1276 uint64_t Address,
1277 const MCDisassembler *Decoder) {
1278 unsigned Offset = Insn & 0x7F;
1279 unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1280
1281 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1282
1283 Inst.addOperand(MCOperand::createReg(Reg));
1284 Inst.addOperand(MCOperand::createReg(Mips::GP));
1285 Inst.addOperand(MCOperand::createImm(Offset << 2));
1286
1287 return MCDisassembler::Success;
1288}
1289
1290static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, unsigned Insn,
1291 uint64_t Address,
1292 const MCDisassembler *Decoder) {
1293 int Offset;
1294 switch (Inst.getOpcode()) {
1295 case Mips::LWM16_MMR6:
1296 case Mips::SWM16_MMR6:
1297 Offset = fieldFromInstruction(Insn, 4, 4);
1298 break;
1299 default:
1300 Offset = SignExtend32<4>(Insn & 0xf);
1301 break;
1302 }
1303
1304 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder)
1305 == MCDisassembler::Fail)
1306 return MCDisassembler::Fail;
1307
1308 Inst.addOperand(MCOperand::createReg(Mips::SP));
1309 Inst.addOperand(MCOperand::createImm(Offset << 2));
1310
1311 return MCDisassembler::Success;
1312}
1313
1314static DecodeStatus DecodeMemMMImm9(MCInst &Inst, unsigned Insn,
1315 uint64_t Address,
1316 const MCDisassembler *Decoder) {
1317 int Offset = SignExtend32<9>(Insn & 0x1ff);
1318 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1319 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1320
1321 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1322 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1323
1324 if (Inst.getOpcode() == Mips::SCE_MM || Inst.getOpcode() == Mips::SC_MMR6)
1325 Inst.addOperand(MCOperand::createReg(Reg));
1326
1327 Inst.addOperand(MCOperand::createReg(Reg));
1328 Inst.addOperand(MCOperand::createReg(Base));
1329 Inst.addOperand(MCOperand::createImm(Offset));
1330
1331 return MCDisassembler::Success;
1332}
1333
1334static DecodeStatus DecodeMemMMImm12(MCInst &Inst, unsigned Insn,
1335 uint64_t Address,
1336 const MCDisassembler *Decoder) {
1337 int Offset = SignExtend32<12>(Insn & 0x0fff);
1338 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1339 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1340
1341 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1342 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1343
1344 switch (Inst.getOpcode()) {
1345 case Mips::SWM32_MM:
1346 case Mips::LWM32_MM:
1347 if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1348 == MCDisassembler::Fail)
1349 return MCDisassembler::Fail;
1350 Inst.addOperand(MCOperand::createReg(Base));
1351 Inst.addOperand(MCOperand::createImm(Offset));
1352 break;
1353 case Mips::SC_MM:
1354 Inst.addOperand(MCOperand::createReg(Reg));
1355 [[fallthrough]];
1356 default:
1357 Inst.addOperand(MCOperand::createReg(Reg));
1358 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1359 Inst.addOperand(MCOperand::createReg(Reg+1));
1360
1361 Inst.addOperand(MCOperand::createReg(Base));
1362 Inst.addOperand(MCOperand::createImm(Offset));
1363 }
1364
1365 return MCDisassembler::Success;
1366}
1367
1368static DecodeStatus DecodeMemMMImm16(MCInst &Inst, unsigned Insn,
1369 uint64_t Address,
1370 const MCDisassembler *Decoder) {
1371 int Offset = SignExtend32<16>(Insn & 0xffff);
1372 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1373 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1374
1375 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1376 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1377
1378 Inst.addOperand(MCOperand::createReg(Reg));
1379 Inst.addOperand(MCOperand::createReg(Base));
1380 Inst.addOperand(MCOperand::createImm(Offset));
1381
1382 return MCDisassembler::Success;
1383}
1384
1385static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address,
1386 const MCDisassembler *Decoder) {
1387 int Offset = SignExtend32<16>(Insn & 0xffff);
1388 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1389 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1390
1391 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1392 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1393
1394 Inst.addOperand(MCOperand::createReg(Reg));
1395 Inst.addOperand(MCOperand::createReg(Base));
1396 Inst.addOperand(MCOperand::createImm(Offset));
1397
1398 return MCDisassembler::Success;
1399}
1400
1401static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn,
1402 uint64_t Address,
1403 const MCDisassembler *Decoder) {
1404 // This function is the same as DecodeFMem but with the Reg and Base fields
1405 // swapped according to microMIPS spec.
1406 int Offset = SignExtend32<16>(Insn & 0xffff);
1407 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1408 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1409
1410 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1411 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1412
1413 Inst.addOperand(MCOperand::createReg(Reg));
1414 Inst.addOperand(MCOperand::createReg(Base));
1415 Inst.addOperand(MCOperand::createImm(Offset));
1416
1417 return MCDisassembler::Success;
1418}
1419
1420static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address,
1421 const MCDisassembler *Decoder) {
1422 int Offset = SignExtend32<16>(Insn & 0xffff);
1423 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1424 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1425
1426 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1427 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1428
1429 Inst.addOperand(MCOperand::createReg(Reg));
1430 Inst.addOperand(MCOperand::createReg(Base));
1431 Inst.addOperand(MCOperand::createImm(Offset));
1432
1433 return MCDisassembler::Success;
1434}
1435
1436static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address,
1437 const MCDisassembler *Decoder) {
1438 int Offset = SignExtend32<16>(Insn & 0xffff);
1439 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1440 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1441
1442 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1443 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1444
1445 Inst.addOperand(MCOperand::createReg(Reg));
1446 Inst.addOperand(MCOperand::createReg(Base));
1447 Inst.addOperand(MCOperand::createImm(Offset));
1448
1449 return MCDisassembler::Success;
1450}
1451
1452static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
1453 uint64_t Address,
1454 const MCDisassembler *Decoder) {
1455 int Offset = SignExtend32<11>(Insn & 0x07ff);
1456 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1457 unsigned Base = fieldFromInstruction(Insn, 11, 5);
1458
1459 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1460 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1461
1462 Inst.addOperand(MCOperand::createReg(Reg));
1463 Inst.addOperand(MCOperand::createReg(Base));
1464 Inst.addOperand(MCOperand::createImm(Offset));
1465
1466 return MCDisassembler::Success;
1467}
1468
1469static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn,
1470 uint64_t Address,
1471 const MCDisassembler *Decoder) {
1472 int Offset = SignExtend32<11>(Insn & 0x07ff);
1473 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1474 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1475
1476 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1477 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1478
1479 Inst.addOperand(MCOperand::createReg(Reg));
1480 Inst.addOperand(MCOperand::createReg(Base));
1481 Inst.addOperand(MCOperand::createImm(Offset));
1482
1483 return MCDisassembler::Success;
1484}
1485
1486static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn,
1487 uint64_t Address,
1488 const MCDisassembler *Decoder) {
1489 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1490 unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1491 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1492
1493 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1494 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1495
1496 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1497 Inst.addOperand(MCOperand::createReg(Rt));
1498 }
1499
1500 Inst.addOperand(MCOperand::createReg(Rt));
1501 Inst.addOperand(MCOperand::createReg(Base));
1502 Inst.addOperand(MCOperand::createImm(Offset));
1503
1504 return MCDisassembler::Success;
1505}
1506
1507static DecodeStatus DecodeBranchTarget(MCInst &Inst, unsigned Offset,
1508 uint64_t Address,
1509 const MCDisassembler *Decoder) {
1510 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
1511 Inst.addOperand(MCOperand::createImm(BranchOffset));
1512 return MCDisassembler::Success;
1513}
1514
1515static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, unsigned Offset,
1516 uint64_t Address,
1517 const MCDisassembler *Decoder) {
1518 int32_t BranchOffset = (SignExtend32<16>(Offset) * 2);
1519 Inst.addOperand(MCOperand::createImm(BranchOffset));
1520 return MCDisassembler::Success;
1521}
1522
1523static DecodeStatus DecodeJumpTarget(MCInst &Inst, unsigned Insn,
1524 uint64_t Address,
1525 const MCDisassembler *Decoder) {
1526 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1527 Inst.addOperand(MCOperand::createImm(JumpOffset));
1528 return MCDisassembler::Success;
1529}
1530
1531static DecodeStatus DecodeBranchTarget21(MCInst &Inst, unsigned Offset,
1532 uint64_t Address,
1533 const MCDisassembler *Decoder) {
1534 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4;
1535
1536 Inst.addOperand(MCOperand::createImm(BranchOffset));
1537 return MCDisassembler::Success;
1538}
1539
1540static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, unsigned Offset,
1541 uint64_t Address,
1542 const MCDisassembler *Decoder) {
1543 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4;
1544
1545 Inst.addOperand(MCOperand::createImm(BranchOffset));
1546 return MCDisassembler::Success;
1547}
1548
1549static DecodeStatus DecodeBranchTarget26(MCInst &Inst, unsigned Offset,
1550 uint64_t Address,
1551 const MCDisassembler *Decoder) {
1552 int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4;
1553
1554 Inst.addOperand(MCOperand::createImm(BranchOffset));
1555 return MCDisassembler::Success;
1556}
1557
1558static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, unsigned Offset,
1559 uint64_t Address,
1560 const MCDisassembler *Decoder) {
1561 int32_t BranchOffset = SignExtend32<8>(Offset << 1);
1562 Inst.addOperand(MCOperand::createImm(BranchOffset));
1563 return MCDisassembler::Success;
1564}
1565
1566static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, unsigned Offset,
1567 uint64_t Address,
1568 const MCDisassembler *Decoder) {
1569 int32_t BranchOffset = SignExtend32<11>(Offset << 1);
1570 Inst.addOperand(MCOperand::createImm(BranchOffset));
1571 return MCDisassembler::Success;
1572}
1573
1574static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, unsigned Offset,
1575 uint64_t Address,
1576 const MCDisassembler *Decoder) {
1577 int32_t BranchOffset = SignExtend32<16>(Offset) * 2 + 4;
1578 Inst.addOperand(MCOperand::createImm(BranchOffset));
1579 return MCDisassembler::Success;
1580}
1581
1582static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, unsigned Offset,
1583 uint64_t Address,
1584 const MCDisassembler *Decoder) {
1585 int32_t BranchOffset = SignExtend32<27>(Offset << 1);
1586
1587 Inst.addOperand(MCOperand::createImm(BranchOffset));
1588 return MCDisassembler::Success;
1589}
1590
1591static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, unsigned Insn,
1592 uint64_t Address,
1593 const MCDisassembler *Decoder) {
1594 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1595 Inst.addOperand(MCOperand::createImm(JumpOffset));
1596 return MCDisassembler::Success;
1597}
1598
1599static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, unsigned Insn,
1600 uint64_t Address,
1601 const MCDisassembler *Decoder) {
1602 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1603 Inst.addOperand(MCOperand::createImm(JumpOffset));
1604 return MCDisassembler::Success;
1605}
1606
1607static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, unsigned Value,
1608 uint64_t Address,
1609 const MCDisassembler *Decoder) {
1610 if (Value == 0)
1611 Inst.addOperand(MCOperand::createImm(1));
1612 else if (Value == 0x7)
1613 Inst.addOperand(MCOperand::createImm(-1));
1614 else
1615 Inst.addOperand(MCOperand::createImm(Value << 2));
1616 return MCDisassembler::Success;
1617}
1618
1619static DecodeStatus DecodeLi16Imm(MCInst &Inst, unsigned Value,
1620 uint64_t Address,
1621 const MCDisassembler *Decoder) {
1622 if (Value == 0x7F)
1623 Inst.addOperand(MCOperand::createImm(-1));
1624 else
1625 Inst.addOperand(MCOperand::createImm(Value));
1626 return MCDisassembler::Success;
1627}
1628
1629static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, unsigned Value,
1630 uint64_t Address,
1631 const MCDisassembler *Decoder) {
1632 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value));
1633 return MCDisassembler::Success;
1634}
1635
1636template <unsigned Bits, int Offset, int Scale>
1637static DecodeStatus
1638DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address,
1639 const MCDisassembler *Decoder) {
1640 Value &= ((1 << Bits) - 1);
1641 Value *= Scale;
1642 Inst.addOperand(MCOperand::createImm(Value + Offset));
1643 return MCDisassembler::Success;
1644}
1645
1646template <unsigned Bits, int Offset = 0, int ScaleBy = 1>
1647static DecodeStatus
1648DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address,
1649 const MCDisassembler *Decoder) {
1650 int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy;
1651 Inst.addOperand(MCOperand::createImm(Imm + Offset));
1652 return MCDisassembler::Success;
1653}
1654
1655template <unsigned Bits, int Offset>
1656static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value,
1657 uint64_t Address,
1658 const MCDisassembler *Decoder) {
1659 return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address,
1660 Decoder);
1661}
1662
1663static DecodeStatus DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address,
1664 const MCDisassembler *Decoder) {
1665 // First we need to grab the pos(lsb) from MCInst.
1666 // This function only handles the 32 bit variants of ins, as dins
1667 // variants are handled differently.
1668 int Pos = Inst.getOperand(2).getImm();
1669 int Size = (int) Insn - Pos + 1;
1670 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
1671 return MCDisassembler::Success;
1672}
1673
1674static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1675 uint64_t Address,
1676 const MCDisassembler *Decoder) {
1677 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4));
1678 return MCDisassembler::Success;
1679}
1680
1681static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1682 uint64_t Address,
1683 const MCDisassembler *Decoder) {
1684 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8));
1685 return MCDisassembler::Success;
1686}
1687
1688static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address,
1689 const MCDisassembler *Decoder) {
1690 int32_t DecodedValue;
1691 switch (Insn) {
1692 case 0: DecodedValue = 256; break;
1693 case 1: DecodedValue = 257; break;
1694 case 510: DecodedValue = -258; break;
1695 case 511: DecodedValue = -257; break;
1696 default: DecodedValue = SignExtend32<9>(Insn); break;
1697 }
1698 Inst.addOperand(MCOperand::createImm(DecodedValue * 4));
1699 return MCDisassembler::Success;
1700}
1701
1702static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
1703 uint64_t Address,
1704 const MCDisassembler *Decoder) {
1705 // Insn must be >= 0, since it is unsigned that condition is always true.
1706 assert(Insn < 16);
1707 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15,
1708 16, 31, 32, 63, 64, 255, 32768, 65535};
1709 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn]));
1710 return MCDisassembler::Success;
1711}
1712
1713static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair,
1714 uint64_t Address,
1715 const MCDisassembler *Decoder) {
1716 switch (RegPair) {
1717 default:
1718 return MCDisassembler::Fail;
1719 case 0:
1720 Inst.addOperand(MCOperand::createReg(Mips::A1));
1721 Inst.addOperand(MCOperand::createReg(Mips::A2));
1722 break;
1723 case 1:
1724 Inst.addOperand(MCOperand::createReg(Mips::A1));
1725 Inst.addOperand(MCOperand::createReg(Mips::A3));
1726 break;
1727 case 2:
1728 Inst.addOperand(MCOperand::createReg(Mips::A2));
1729 Inst.addOperand(MCOperand::createReg(Mips::A3));
1730 break;
1731 case 3:
1732 Inst.addOperand(MCOperand::createReg(Mips::A0));
1733 Inst.addOperand(MCOperand::createReg(Mips::S5));
1734 break;
1735 case 4:
1736 Inst.addOperand(MCOperand::createReg(Mips::A0));
1737 Inst.addOperand(MCOperand::createReg(Mips::S6));
1738 break;
1739 case 5:
1740 Inst.addOperand(MCOperand::createReg(Mips::A0));
1741 Inst.addOperand(MCOperand::createReg(Mips::A1));
1742 break;
1743 case 6:
1744 Inst.addOperand(MCOperand::createReg(Mips::A0));
1745 Inst.addOperand(MCOperand::createReg(Mips::A2));
1746 break;
1747 case 7:
1748 Inst.addOperand(MCOperand::createReg(Mips::A0));
1749 Inst.addOperand(MCOperand::createReg(Mips::A3));
1750 break;
1751 }
1752
1753 return MCDisassembler::Success;
1754}
1755
1756static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn,
1757 uint64_t Address,
1758 const MCDisassembler *Decoder) {
1759 unsigned RegPair = fieldFromInstruction(Insn, 7, 3);
1760 if (DecodeMovePRegPair(Inst, RegPair, Address, Decoder) ==
1761 MCDisassembler::Fail)
1762 return MCDisassembler::Fail;
1763
1764 unsigned RegRs;
1765 if (static_cast<const MipsDisassembler *>(Decoder)->hasMips32r6())
1766 RegRs = fieldFromInstruction(Insn, 0, 2) |
1767 (fieldFromInstruction(Insn, 3, 1) << 2);
1768 else
1769 RegRs = fieldFromInstruction(Insn, 1, 3);
1770 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRs, Address, Decoder) ==
1771 MCDisassembler::Fail)
1772 return MCDisassembler::Fail;
1773
1774 unsigned RegRt = fieldFromInstruction(Insn, 4, 3);
1775 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRt, Address, Decoder) ==
1776 MCDisassembler::Fail)
1777 return MCDisassembler::Fail;
1778
1779 return MCDisassembler::Success;
1780}
1781
1782static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
1783 uint64_t Address,
1784 const MCDisassembler *Decoder) {
1785 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2)));
1786 return MCDisassembler::Success;
1787}
1788
1789template <typename InsnType>
1790static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn,
1791 uint64_t Address,
1792 const MCDisassembler *Decoder) {
1793 // We have:
1794 // 0b000111 ttttt sssss iiiiiiiiiiiiiiii
1795 // Invalid if rt == 0
1796 // BGTZALC_MMR6 if rs == 0 && rt != 0
1797 // BLTZALC_MMR6 if rs != 0 && rs == rt
1798 // BLTUC_MMR6 if rs != 0 && rs != rt
1799
1800 InsnType Rt = fieldFromInstruction(insn, 21, 5);
1801 InsnType Rs = fieldFromInstruction(insn, 16, 5);
1802 InsnType Imm = 0;
1803 bool HasRs = false;
1804 bool HasRt = false;
1805
1806 if (Rt == 0)
1807 return MCDisassembler::Fail;
1808 else if (Rs == 0) {
1809 MI.setOpcode(Mips::BGTZALC_MMR6);
1810 HasRt = true;
1811 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
1812 }
1813 else if (Rs == Rt) {
1814 MI.setOpcode(Mips::BLTZALC_MMR6);
1815 HasRs = true;
1816 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
1817 }
1818 else {
1819 MI.setOpcode(Mips::BLTUC_MMR6);
1820 HasRs = true;
1821 HasRt = true;
1822 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
1823 }
1824
1825 if (HasRs)
1826 MI.addOperand(
1827 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs)));
1828
1829 if (HasRt)
1830 MI.addOperand(
1831 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));
1832
1833 MI.addOperand(MCOperand::createImm(Imm));
1834
1835 return MCDisassembler::Success;
1836}
1837
1838template <typename InsnType>
1839static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn,
1840 uint64_t Address,
1841 const MCDisassembler *Decoder) {
1842 // We have:
1843 // 0b000110 ttttt sssss iiiiiiiiiiiiiiii
1844 // Invalid if rt == 0
1845 // BLEZALC_MMR6 if rs == 0 && rt != 0
1846 // BGEZALC_MMR6 if rs == rt && rt != 0
1847 // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0
1848
1849 InsnType Rt = fieldFromInstruction(insn, 21, 5);
1850 InsnType Rs = fieldFromInstruction(insn, 16, 5);
1851 InsnType Imm = 0;
1852 bool HasRs = false;
1853
1854 if (Rt == 0)
1855 return MCDisassembler::Fail;
1856 else if (Rs == 0) {
1857 MI.setOpcode(Mips::BLEZALC_MMR6);
1858 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
1859 }
1860 else if (Rs == Rt) {
1861 MI.setOpcode(Mips::BGEZALC_MMR6);
1862 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
1863 }
1864 else {
1865 HasRs = true;
1866 MI.setOpcode(Mips::BGEUC_MMR6);
1867 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
1868 }
1869
1870 if (HasRs)
1871 MI.addOperand(
1872 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs)));
1873 MI.addOperand(
1874 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));
1875
1876 MI.addOperand(MCOperand::createImm(Imm));
1877
1878 return MCDisassembler::Success;
1879}
1880
1881// This instruction does not have a working decoder, and needs to be
1882// fixed. This "fixme" function was introduced to keep the backend compiling,
1883// while making changes to tablegen code.
1884static DecodeStatus DecodeFIXMEInstruction(MCInst &Inst, unsigned Insn,
1885 uint64_t Address,
1886 const MCDisassembler *Decoder) {
1887 return MCDisassembler::Fail;
1888}
1889
1890#include "MipsGenDisassemblerTables.inc"
1891
1892/// Read two bytes from the ArrayRef and return 16 bit halfword sorted
1893/// according to the given endianness.
1894static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
1895 uint64_t &Size, uint32_t &Insn,
1896 bool IsBigEndian) {
1897 // We want to read exactly 2 Bytes of data.
1898 if (Bytes.size() < 2) {
1899 Size = 0;
1900 return MCDisassembler::Fail;
1901 }
1902
1903 if (IsBigEndian) {
1904 Insn = (Bytes[0] << 8) | Bytes[1];
1905 } else {
1906 Insn = (Bytes[1] << 8) | Bytes[0];
1907 }
1908
1909 return MCDisassembler::Success;
1910}
1911
1912/// Read four bytes from the ArrayRef and return 32 bit word sorted
1913/// according to the given endianness.
1914static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
1915 uint64_t &Size, uint32_t &Insn,
1916 bool IsBigEndian, bool IsMicroMips) {
1917 // We want to read exactly 4 Bytes of data.
1918 if (Bytes.size() < 4) {
1919 Size = 0;
1920 return MCDisassembler::Fail;
1921 }
1922
1923 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
1924 // always precede the low 16 bits in the instruction stream (that is, they
1925 // are placed at lower addresses in the instruction stream).
1926 //
1927 // microMIPS byte ordering:
1928 // Big-endian: 0 | 1 | 2 | 3
1929 // Little-endian: 1 | 0 | 3 | 2
1930
1931 if (IsBigEndian) {
1932 // Encoded as a big-endian 32-bit word in the stream.
1933 Insn =
1934 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
1935 } else {
1936 if (IsMicroMips) {
1937 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
1938 (Bytes[1] << 24);
1939 } else {
1940 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
1941 (Bytes[3] << 24);
1942 }
1943 }
1944
1945 return MCDisassembler::Success;
1946}
1947
1948DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
1949 ArrayRef<uint8_t> Bytes,
1950 uint64_t Address,
1951 raw_ostream &CStream) const {
1952 uint32_t Insn;
1953 DecodeStatus Result;
1954 Size = 0;
1955
1956 if (IsMicroMips) {
1957 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
1958 if (Result == MCDisassembler::Fail)
1959 return MCDisassembler::Fail;
1960
1961 if (hasMips32r6()) {
1962 LLVM_DEBUG(
1963 dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n");
1964 // Calling the auto-generated decoder function for microMIPS32R6
1965 // 16-bit instructions.
1966 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn,
1967 Address, this, STI);
1968 if (Result != MCDisassembler::Fail) {
1969 Size = 2;
1970 return Result;
1971 }
1972 }
1973
1974 LLVM_DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
1975 // Calling the auto-generated decoder function for microMIPS 16-bit
1976 // instructions.
1977 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
1978 this, STI);
1979 if (Result != MCDisassembler::Fail) {
1980 Size = 2;
1981 return Result;
1982 }
1983
1984 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
1985 if (Result == MCDisassembler::Fail)
1986 return MCDisassembler::Fail;
1987
1988 if (hasMips32r6()) {
1989 LLVM_DEBUG(
1990 dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");
1991 // Calling the auto-generated decoder function.
1992 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn,
1993 Address, this, STI);
1994 if (Result != MCDisassembler::Fail) {
1995 Size = 4;
1996 return Result;
1997 }
1998 }
1999
2000 LLVM_DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
2001 // Calling the auto-generated decoder function.
2002 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
2003 this, STI);
2004 if (Result != MCDisassembler::Fail) {
2005 Size = 4;
2006 return Result;
2007 }
2008
2009 if (isFP64()) {
2010 LLVM_DEBUG(dbgs() << "Trying MicroMipsFP64 table (32-bit opcodes):\n");
2011 Result = decodeInstruction(DecoderTableMicroMipsFP6432, Instr, Insn,
2012 Address, this, STI);
2013 if (Result != MCDisassembler::Fail) {
2014 Size = 4;
2015 return Result;
2016 }
2017 }
2018
2019 // This is an invalid instruction. Claim that the Size is 2 bytes. Since
2020 // microMIPS instructions have a minimum alignment of 2, the next 2 bytes
2021 // could form a valid instruction. The two bytes we rejected as an
2022 // instruction could have actually beeen an inline constant pool that is
2023 // unconditionally branched over.
2024 Size = 2;
2025 return MCDisassembler::Fail;
2026 }
2027
2028 // Attempt to read the instruction so that we can attempt to decode it. If
2029 // the buffer is not 4 bytes long, let the higher level logic figure out
2030 // what to do with a size of zero and MCDisassembler::Fail.
2031 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
2032 if (Result == MCDisassembler::Fail)
2033 return MCDisassembler::Fail;
2034
2035 // The only instruction size for standard encoded MIPS.
2036 Size = 4;
2037
2038 if (hasCOP3()) {
2039 LLVM_DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
2040 Result =
2041 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
2042 if (Result != MCDisassembler::Fail)
2043 return Result;
2044 }
2045
2046 if (hasMips32r6() && isGP64()) {
2047 LLVM_DEBUG(
2048 dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
2049 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
2050 Address, this, STI);
2051 if (Result != MCDisassembler::Fail)
2052 return Result;
2053 }
2054
2055 if (hasMips32r6() && isPTR64()) {
2056 LLVM_DEBUG(
2057 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
2058 Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn,
2059 Address, this, STI);
2060 if (Result != MCDisassembler::Fail)
2061 return Result;
2062 }
2063
2064 if (hasMips32r6()) {
2065 LLVM_DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
2066 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
2067 Address, this, STI);
2068 if (Result != MCDisassembler::Fail)
2069 return Result;
2070 }
2071
2072 if (hasMips2() && isPTR64()) {
2073 LLVM_DEBUG(
2074 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
2075 Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn,
2076 Address, this, STI);
2077 if (Result != MCDisassembler::Fail)
2078 return Result;
2079 }
2080
2081 if (hasCnMips()) {
2082 LLVM_DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n");
2083 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, Address, this,
2084 STI);
2085 if (Result != MCDisassembler::Fail)
2086 return Result;
2087 }
2088
2089 if (hasCnMipsP()) {
2090 LLVM_DEBUG(dbgs() << "Trying CnMipsP table (32-bit opcodes):\n");
2091 Result = decodeInstruction(DecoderTableCnMipsP32, Instr, Insn, Address,
2092 this, STI);
2093 if (Result != MCDisassembler::Fail)
2094 return Result;
2095 }
2096
2097 if (isGP64()) {
2098 LLVM_DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");
2099 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, Address, this,
2100 STI);
2101 if (Result != MCDisassembler::Fail)
2102 return Result;
2103 }
2104
2105 if (isFP64()) {
2106 LLVM_DEBUG(
2107 dbgs() << "Trying MipsFP64 (64 bit FPU) table (32-bit opcodes):\n");
2108 Result = decodeInstruction(DecoderTableMipsFP6432, Instr, Insn, Address,
2109 this, STI);
2110 if (Result != MCDisassembler::Fail)
2111 return Result;
2112 }
2113
2114 LLVM_DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
2115 // Calling the auto-generated decoder function.
2116 Result =
2117 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
2118 if (Result != MCDisassembler::Fail)
2119 return Result;
2120
2121 return MCDisassembler::Fail;
2122}
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
D
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
LLVM_ABI
#define LLVM_ABI
Definition: Compiler.h:213
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:132
Size
uint64_t Size
Definition: ELFObjHandler.cpp:81
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:110
DecodePOOL16BEncodedField
static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1629
DecodeFMemCop2MMR6
static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1469
DecodeSimm19Lsl2
static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1674
DecodeMemEVA
static DecodeStatus DecodeMemEVA(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1017
DecodeBgtzlGroupBranch
static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:638
DecodeRegListOperand
static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:241
readInstruction32
static DecodeStatus readInstruction32(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian, bool IsMicroMips)
Read four bytes from the ArrayRef and return 32 bit word sorted according to the given endianness.
Definition: MipsDisassembler.cpp:1914
DecodeBranchTarget21
static DecodeStatus DecodeBranchTarget21(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1531
DecodeJumpTargetXMM
static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1599
DecodeFGR32RegisterClass
static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:955
DecodeCCRRegisterClass
static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:966
DecodeCOP2RegisterClass
static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:230
getReg
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:106
DecodeFCCRegisterClass
static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:976
DecodeCacheOpMM
static DecodeStatus DecodeCacheOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1068
readInstruction16
static DecodeStatus readInstruction16(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian)
Read two bytes from the ArrayRef and return 16 bit halfword sorted according to the given endianness.
Definition: MipsDisassembler.cpp:1894
DecodeGPRMM16RegisterClass
static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:889
DecodeSImmWithOffsetAndScale
static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1648
DecodeSimm23Lsl2
static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1782
DecodeGPRMM16MovePRegisterClass
static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:910
DecodeBranchTarget1SImm16
static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1515
DecodeMemMMImm9
static DecodeStatus DecodeMemMMImm9(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1314
DecodeMovePOperands
static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1756
DecodeCRC
static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:859
DecodePOP75GroupBranchMMR6
static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:556
DecodeDINS
static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:817
DecodeMSA128Mem
static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1156
DecodePrefeOpMM
static DecodeStatus DecodePrefeOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1084
DecodeCPU16RegsRegisterClass
static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:873
DecodeMSA128WRegisterClass
static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:186
DecodeBranchTarget26
static DecodeStatus DecodeBranchTarget26(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1549
DecodeHWRegsRegisterClass
static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:110
DecodeFMem
static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1385
DecodeCacheOp
static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1053
DecodeSyncI_MM
static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1129
DecodeLoadByte15
static DecodeStatus DecodeLoadByte15(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1036
DecodeSimm9SP
static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1688
DecodeFMem2
static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1420
DecodeUImmWithOffsetAndScale
static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1638
DecodeMemMMImm12
static DecodeStatus DecodeMemMMImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1334
DecodeDEXT
static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:775
DecodeGPRMM16ZeroRegisterClass
static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:900
DecodeLi16Imm
static DecodeStatus DecodeLi16Imm(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1619
createMipselDisassembler
static MCDisassembler * createMipselDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: MipsDisassembler.cpp:87
DecodeSimm18Lsl3
static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1681
DecodeFMem3
static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1436
DecodeBlezlGroupBranch
static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:595
DecodeCOP0RegisterClass
static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:219
DecodeBranchTarget
static DecodeStatus DecodeBranchTarget(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1507
DecodeMemMMReglistImm4Lsl2
static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1290
DecodeBgtzGroupBranch
static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:682
DecodeBranchTargetMM
static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1574
DecodePOP35GroupBranchMMR6
static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:410
DecodeFIXMEInstruction
static DecodeStatus DecodeFIXMEInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1884
DecodeBranchTarget10MM
static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1566
DecodeANDI16Imm
static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1702
DecodeMSA128DRegisterClass
static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:197
DecodeMemMMImm4
static DecodeStatus DecodeMemMMImm4(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1203
createMipsDisassembler
static MCDisassembler * createMipsDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: MipsDisassembler.cpp:81
DecodeGPR32RegisterClass
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:919
DecodeMSA128BRegisterClass
static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:164
DecodeDaddiGroupBranch
static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:444
DecodeMovePRegPair
static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1713
DecodeDAHIDATIMMR6
static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:342
DecodeBranchTarget21MM
static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1540
DecodeBranchTarget26MM
static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1582
DecodeAFGR64RegisterClass
static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:120
DecodeDAHIDATI
static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:357
DecodeLO32DSPRegisterClass
static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:153
DecodeSpecial3LlSc
static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1486
DecodeHI32DSPRegisterClass
static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:142
DecodeStatus
MCDisassembler::DecodeStatus DecodeStatus
Definition: MipsDisassembler.cpp:37
DecodeSynciR6
static DecodeStatus DecodeSynciR6(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1143
DecodePtrRegisterClass
static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:929
DecodeUImmWithOffset
static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1656
DecodeRegListOperand16
static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:269
DecodeAddiGroupBranch
static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:371
DecodeMemMMSPImm5Lsl2
static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1260
DecodeAddiur2Simm7
static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1607
DecodeMSACtrlRegisterClass
static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:208
DecodeMSA128HRegisterClass
static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:175
DecodeFMemMMR2
static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1401
DecodeCacheeOp_CacheOpR6
static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1100
DecodeMemMMImm16
static DecodeStatus DecodeMemMMImm16(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1368
DecodeBranchTarget7MM
static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1558
DecodeFGR64RegisterClass
static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:944
DecodeGPR64RegisterClass
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:878
DecodeBlezGroupBranchMMR6
static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1839
DecodeJumpTargetMM
static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1591
DecodePOP37GroupBranchMMR6
static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:483
DecodeSyncI
static DecodeStatus DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1116
DecodeJumpTarget
static DecodeStatus DecodeJumpTarget(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1523
DecodeACC64DSPRegisterClass
static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:131
DecodeFMemCop2R6
static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1452
DecodeBgtzGroupBranchMMR6
static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1790
DecodePOP65GroupBranchMMR6
static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:517
DecodeDSPRRegisterClass
static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:938
DecodeInsSize
static DecodeStatus DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1663
DecodeBlezGroupBranch
static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:731
DecodeMem
static DecodeStatus DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:997
DecodeFGRCCRegisterClass
static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:986
DecodeINSVE_DF
static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:294
DecodeMemMMGPImm7Lsl2
static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: MipsDisassembler.cpp:1275
LLVMInitializeMipsDisassembler
LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsDisassembler()
Definition: MipsDisassembler.cpp:94
LLVM_DEBUG
#define LLVM_DEBUG(...)
Definition: Debug.h:119
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:147
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:83
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:85
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:109
llvm::MCDisassembler::getInstruction
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:188
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:202
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:215
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:210
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:84
llvm::MCOperand::createReg
static MCOperand createReg(MCRegister Reg)
Definition: MCInst.h:138
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:145
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:150
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:77
llvm::MCSubtargetInfo::hasFeature
bool hasFeature(unsigned Feature) const
Definition: MCSubtargetInfo.h:122
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:146
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
uint32_t
uint64_t
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:164
llvm::MCD::fieldFromInstruction
std::enable_if_t< std::is_integral_v< IntType >, IntType > fieldFromInstruction(const IntType &Insn, unsigned StartBit, unsigned NumBits)
Definition: MCDecoder.h:36
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::Offset
@ Offset
Definition: DWP.cpp:477
llvm::getTheMips64Target
Target & getTheMips64Target()
Definition: MipsTargetInfo.cpp:22
llvm::dbgs
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:207
llvm::getTheMips64elTarget
Target & getTheMips64elTarget()
Definition: MipsTargetInfo.cpp:26
llvm::getTheMipselTarget
Target & getTheMipselTarget()
Definition: MipsTargetInfo.cpp:18
llvm::SignExtend64
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition: MathExtras.h:577
llvm::getTheMipsTarget
Target & getTheMipsTarget()
Definition: MipsTargetInfo.cpp:14
raw_ostream.h
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition: TargetRegistry.h:897
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