15#ifndef LLVM_IR_NVVMINTRINSICUTILS_H
16#define LLVM_IR_NVVMINTRINSICUTILS_H
22#include "llvm/IR/IntrinsicsNVPTX.h"
60 switch (IntrinsicID) {
61 case Intrinsic::nvvm_f2i_rm_ftz:
62 case Intrinsic::nvvm_f2i_rn_ftz:
63 case Intrinsic::nvvm_f2i_rp_ftz:
64 case Intrinsic::nvvm_f2i_rz_ftz:
66 case Intrinsic::nvvm_f2ui_rm_ftz:
67 case Intrinsic::nvvm_f2ui_rn_ftz:
68 case Intrinsic::nvvm_f2ui_rp_ftz:
69 case Intrinsic::nvvm_f2ui_rz_ftz:
71 case Intrinsic::nvvm_f2ll_rm_ftz:
72 case Intrinsic::nvvm_f2ll_rn_ftz:
73 case Intrinsic::nvvm_f2ll_rp_ftz:
74 case Intrinsic::nvvm_f2ll_rz_ftz:
76 case Intrinsic::nvvm_f2ull_rm_ftz:
77 case Intrinsic::nvvm_f2ull_rn_ftz:
78 case Intrinsic::nvvm_f2ull_rp_ftz:
79 case Intrinsic::nvvm_f2ull_rz_ftz:
82 case Intrinsic::nvvm_f2i_rm:
83 case Intrinsic::nvvm_f2i_rn:
84 case Intrinsic::nvvm_f2i_rp:
85 case Intrinsic::nvvm_f2i_rz:
87 case Intrinsic::nvvm_f2ui_rm:
88 case Intrinsic::nvvm_f2ui_rn:
89 case Intrinsic::nvvm_f2ui_rp:
90 case Intrinsic::nvvm_f2ui_rz:
92 case Intrinsic::nvvm_d2i_rm:
93 case Intrinsic::nvvm_d2i_rn:
94 case Intrinsic::nvvm_d2i_rp:
95 case Intrinsic::nvvm_d2i_rz:
97 case Intrinsic::nvvm_d2ui_rm:
98 case Intrinsic::nvvm_d2ui_rn:
99 case Intrinsic::nvvm_d2ui_rp:
100 case Intrinsic::nvvm_d2ui_rz:
102 case Intrinsic::nvvm_f2ll_rm:
103 case Intrinsic::nvvm_f2ll_rn:
104 case Intrinsic::nvvm_f2ll_rp:
105 case Intrinsic::nvvm_f2ll_rz:
107 case Intrinsic::nvvm_f2ull_rm:
108 case Intrinsic::nvvm_f2ull_rn:
109 case Intrinsic::nvvm_f2ull_rp:
110 case Intrinsic::nvvm_f2ull_rz:
112 case Intrinsic::nvvm_d2ll_rm:
113 case Intrinsic::nvvm_d2ll_rn:
114 case Intrinsic::nvvm_d2ll_rp:
115 case Intrinsic::nvvm_d2ll_rz:
117 case Intrinsic::nvvm_d2ull_rm:
118 case Intrinsic::nvvm_d2ull_rn:
119 case Intrinsic::nvvm_d2ull_rp:
120 case Intrinsic::nvvm_d2ull_rz:
127 switch (IntrinsicID) {
129 case Intrinsic::nvvm_f2i_rm:
130 case Intrinsic::nvvm_f2i_rm_ftz:
131 case Intrinsic::nvvm_f2i_rn:
132 case Intrinsic::nvvm_f2i_rn_ftz:
133 case Intrinsic::nvvm_f2i_rp:
134 case Intrinsic::nvvm_f2i_rp_ftz:
135 case Intrinsic::nvvm_f2i_rz:
136 case Intrinsic::nvvm_f2i_rz_ftz:
138 case Intrinsic::nvvm_d2i_rm:
139 case Intrinsic::nvvm_d2i_rn:
140 case Intrinsic::nvvm_d2i_rp:
141 case Intrinsic::nvvm_d2i_rz:
143 case Intrinsic::nvvm_f2ll_rm:
144 case Intrinsic::nvvm_f2ll_rm_ftz:
145 case Intrinsic::nvvm_f2ll_rn:
146 case Intrinsic::nvvm_f2ll_rn_ftz:
147 case Intrinsic::nvvm_f2ll_rp:
148 case Intrinsic::nvvm_f2ll_rp_ftz:
149 case Intrinsic::nvvm_f2ll_rz:
150 case Intrinsic::nvvm_f2ll_rz_ftz:
152 case Intrinsic::nvvm_d2ll_rm:
153 case Intrinsic::nvvm_d2ll_rn:
154 case Intrinsic::nvvm_d2ll_rp:
155 case Intrinsic::nvvm_d2ll_rz:
159 case Intrinsic::nvvm_f2ui_rm:
160 case Intrinsic::nvvm_f2ui_rm_ftz:
161 case Intrinsic::nvvm_f2ui_rn:
162 case Intrinsic::nvvm_f2ui_rn_ftz:
163 case Intrinsic::nvvm_f2ui_rp:
164 case Intrinsic::nvvm_f2ui_rp_ftz:
165 case Intrinsic::nvvm_f2ui_rz:
166 case Intrinsic::nvvm_f2ui_rz_ftz:
168 case Intrinsic::nvvm_d2ui_rm:
169 case Intrinsic::nvvm_d2ui_rn:
170 case Intrinsic::nvvm_d2ui_rp:
171 case Intrinsic::nvvm_d2ui_rz:
173 case Intrinsic::nvvm_f2ull_rm:
174 case Intrinsic::nvvm_f2ull_rm_ftz:
175 case Intrinsic::nvvm_f2ull_rn:
176 case Intrinsic::nvvm_f2ull_rn_ftz:
177 case Intrinsic::nvvm_f2ull_rp:
178 case Intrinsic::nvvm_f2ull_rp_ftz:
179 case Intrinsic::nvvm_f2ull_rz:
180 case Intrinsic::nvvm_f2ull_rz_ftz:
182 case Intrinsic::nvvm_d2ull_rm:
183 case Intrinsic::nvvm_d2ull_rn:
184 case Intrinsic::nvvm_d2ull_rp:
185 case Intrinsic::nvvm_d2ull_rz:
189 "Checking invalid f2i/d2i intrinsic for signed int conversion");
193 switch (IntrinsicID) {
195 case Intrinsic::nvvm_f2i_rm:
196 case Intrinsic::nvvm_f2i_rn:
197 case Intrinsic::nvvm_f2i_rp:
198 case Intrinsic::nvvm_f2i_rz:
199 case Intrinsic::nvvm_f2i_rm_ftz:
200 case Intrinsic::nvvm_f2i_rn_ftz:
201 case Intrinsic::nvvm_f2i_rp_ftz:
202 case Intrinsic::nvvm_f2i_rz_ftz:
204 case Intrinsic::nvvm_f2ui_rm:
205 case Intrinsic::nvvm_f2ui_rn:
206 case Intrinsic::nvvm_f2ui_rp:
207 case Intrinsic::nvvm_f2ui_rz:
208 case Intrinsic::nvvm_f2ui_rm_ftz:
209 case Intrinsic::nvvm_f2ui_rn_ftz:
210 case Intrinsic::nvvm_f2ui_rp_ftz:
211 case Intrinsic::nvvm_f2ui_rz_ftz:
214 case Intrinsic::nvvm_d2i_rm:
215 case Intrinsic::nvvm_d2i_rn:
216 case Intrinsic::nvvm_d2i_rp:
217 case Intrinsic::nvvm_d2i_rz:
219 case Intrinsic::nvvm_d2ui_rm:
220 case Intrinsic::nvvm_d2ui_rn:
221 case Intrinsic::nvvm_d2ui_rp:
222 case Intrinsic::nvvm_d2ui_rz:
224 case Intrinsic::nvvm_f2ll_rm:
225 case Intrinsic::nvvm_f2ll_rn:
226 case Intrinsic::nvvm_f2ll_rp:
227 case Intrinsic::nvvm_f2ll_rz:
228 case Intrinsic::nvvm_f2ll_rm_ftz:
229 case Intrinsic::nvvm_f2ll_rn_ftz:
230 case Intrinsic::nvvm_f2ll_rp_ftz:
231 case Intrinsic::nvvm_f2ll_rz_ftz:
233 case Intrinsic::nvvm_f2ull_rm:
234 case Intrinsic::nvvm_f2ull_rn:
235 case Intrinsic::nvvm_f2ull_rp:
236 case Intrinsic::nvvm_f2ull_rz:
237 case Intrinsic::nvvm_f2ull_rm_ftz:
238 case Intrinsic::nvvm_f2ull_rn_ftz:
239 case Intrinsic::nvvm_f2ull_rp_ftz:
240 case Intrinsic::nvvm_f2ull_rz_ftz:
242 case Intrinsic::nvvm_d2ll_rm:
243 case Intrinsic::nvvm_d2ll_rn:
244 case Intrinsic::nvvm_d2ll_rp:
245 case Intrinsic::nvvm_d2ll_rz:
247 case Intrinsic::nvvm_d2ull_rm:
248 case Intrinsic::nvvm_d2ull_rn:
249 case Intrinsic::nvvm_d2ull_rp:
250 case Intrinsic::nvvm_d2ull_rz:
258 switch (IntrinsicID) {
260 case Intrinsic::nvvm_f2i_rm:
261 case Intrinsic::nvvm_f2ui_rm:
262 case Intrinsic::nvvm_f2i_rm_ftz:
263 case Intrinsic::nvvm_f2ui_rm_ftz:
264 case Intrinsic::nvvm_d2i_rm:
265 case Intrinsic::nvvm_d2ui_rm:
267 case Intrinsic::nvvm_f2ll_rm:
268 case Intrinsic::nvvm_f2ull_rm:
269 case Intrinsic::nvvm_f2ll_rm_ftz:
270 case Intrinsic::nvvm_f2ull_rm_ftz:
271 case Intrinsic::nvvm_d2ll_rm:
272 case Intrinsic::nvvm_d2ull_rm:
276 case Intrinsic::nvvm_f2i_rn:
277 case Intrinsic::nvvm_f2ui_rn:
278 case Intrinsic::nvvm_f2i_rn_ftz:
279 case Intrinsic::nvvm_f2ui_rn_ftz:
280 case Intrinsic::nvvm_d2i_rn:
281 case Intrinsic::nvvm_d2ui_rn:
283 case Intrinsic::nvvm_f2ll_rn:
284 case Intrinsic::nvvm_f2ull_rn:
285 case Intrinsic::nvvm_f2ll_rn_ftz:
286 case Intrinsic::nvvm_f2ull_rn_ftz:
287 case Intrinsic::nvvm_d2ll_rn:
288 case Intrinsic::nvvm_d2ull_rn:
292 case Intrinsic::nvvm_f2i_rp:
293 case Intrinsic::nvvm_f2ui_rp:
294 case Intrinsic::nvvm_f2i_rp_ftz:
295 case Intrinsic::nvvm_f2ui_rp_ftz:
296 case Intrinsic::nvvm_d2i_rp:
297 case Intrinsic::nvvm_d2ui_rp:
299 case Intrinsic::nvvm_f2ll_rp:
300 case Intrinsic::nvvm_f2ull_rp:
301 case Intrinsic::nvvm_f2ll_rp_ftz:
302 case Intrinsic::nvvm_f2ull_rp_ftz:
303 case Intrinsic::nvvm_d2ll_rp:
304 case Intrinsic::nvvm_d2ull_rp:
308 case Intrinsic::nvvm_f2i_rz:
309 case Intrinsic::nvvm_f2ui_rz:
310 case Intrinsic::nvvm_f2i_rz_ftz:
311 case Intrinsic::nvvm_f2ui_rz_ftz:
312 case Intrinsic::nvvm_d2i_rz:
313 case Intrinsic::nvvm_d2ui_rz:
315 case Intrinsic::nvvm_f2ll_rz:
316 case Intrinsic::nvvm_f2ull_rz:
317 case Intrinsic::nvvm_f2ll_rz_ftz:
318 case Intrinsic::nvvm_f2ull_rz_ftz:
319 case Intrinsic::nvvm_d2ll_rz:
320 case Intrinsic::nvvm_d2ull_rz:
327 switch (IntrinsicID) {
328 case Intrinsic::nvvm_fmax_ftz_f:
329 case Intrinsic::nvvm_fmax_ftz_nan_f:
330 case Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs_f:
331 case Intrinsic::nvvm_fmax_ftz_xorsign_abs_f:
333 case Intrinsic::nvvm_fmin_ftz_f:
334 case Intrinsic::nvvm_fmin_ftz_nan_f:
335 case Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs_f:
336 case Intrinsic::nvvm_fmin_ftz_xorsign_abs_f:
339 case Intrinsic::nvvm_fmax_d:
340 case Intrinsic::nvvm_fmax_f:
341 case Intrinsic::nvvm_fmax_nan_f:
342 case Intrinsic::nvvm_fmax_nan_xorsign_abs_f:
343 case Intrinsic::nvvm_fmax_xorsign_abs_f:
345 case Intrinsic::nvvm_fmin_d:
346 case Intrinsic::nvvm_fmin_f:
347 case Intrinsic::nvvm_fmin_nan_f:
348 case Intrinsic::nvvm_fmin_nan_xorsign_abs_f:
349 case Intrinsic::nvvm_fmin_xorsign_abs_f:
356 switch (IntrinsicID) {
357 case Intrinsic::nvvm_fmax_ftz_nan_f:
358 case Intrinsic::nvvm_fmax_nan_f:
359 case Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs_f:
360 case Intrinsic::nvvm_fmax_nan_xorsign_abs_f:
362 case Intrinsic::nvvm_fmin_ftz_nan_f:
363 case Intrinsic::nvvm_fmin_nan_f:
364 case Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs_f:
365 case Intrinsic::nvvm_fmin_nan_xorsign_abs_f:
368 case Intrinsic::nvvm_fmax_d:
369 case Intrinsic::nvvm_fmax_f:
370 case Intrinsic::nvvm_fmax_ftz_f:
371 case Intrinsic::nvvm_fmax_ftz_xorsign_abs_f:
372 case Intrinsic::nvvm_fmax_xorsign_abs_f:
374 case Intrinsic::nvvm_fmin_d:
375 case Intrinsic::nvvm_fmin_f:
376 case Intrinsic::nvvm_fmin_ftz_f:
377 case Intrinsic::nvvm_fmin_ftz_xorsign_abs_f:
378 case Intrinsic::nvvm_fmin_xorsign_abs_f:
385 switch (IntrinsicID) {
386 case Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs_f:
387 case Intrinsic::nvvm_fmax_ftz_xorsign_abs_f:
388 case Intrinsic::nvvm_fmax_nan_xorsign_abs_f:
389 case Intrinsic::nvvm_fmax_xorsign_abs_f:
391 case Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs_f:
392 case Intrinsic::nvvm_fmin_ftz_xorsign_abs_f:
393 case Intrinsic::nvvm_fmin_nan_xorsign_abs_f:
394 case Intrinsic::nvvm_fmin_xorsign_abs_f:
397 case Intrinsic::nvvm_fmax_d:
398 case Intrinsic::nvvm_fmax_f:
399 case Intrinsic::nvvm_fmax_ftz_f:
400 case Intrinsic::nvvm_fmax_ftz_nan_f:
401 case Intrinsic::nvvm_fmax_nan_f:
403 case Intrinsic::nvvm_fmin_d:
404 case Intrinsic::nvvm_fmin_f:
405 case Intrinsic::nvvm_fmin_ftz_f:
406 case Intrinsic::nvvm_fmin_ftz_nan_f:
407 case Intrinsic::nvvm_fmin_nan_f:
410 llvm_unreachable(
"Checking XorSignAbs flag for invalid fmin/fmax intrinsic");
414 switch (IntrinsicID) {
415 case Intrinsic::nvvm_ceil_ftz_f:
416 case Intrinsic::nvvm_fabs_ftz:
417 case Intrinsic::nvvm_floor_ftz_f:
418 case Intrinsic::nvvm_round_ftz_f:
419 case Intrinsic::nvvm_saturate_ftz_f:
420 case Intrinsic::nvvm_sqrt_rn_ftz_f:
422 case Intrinsic::nvvm_ceil_f:
423 case Intrinsic::nvvm_ceil_d:
424 case Intrinsic::nvvm_fabs:
425 case Intrinsic::nvvm_floor_f:
426 case Intrinsic::nvvm_floor_d:
427 case Intrinsic::nvvm_round_f:
428 case Intrinsic::nvvm_round_d:
429 case Intrinsic::nvvm_saturate_d:
430 case Intrinsic::nvvm_saturate_f:
431 case Intrinsic::nvvm_sqrt_f:
432 case Intrinsic::nvvm_sqrt_rn_d:
433 case Intrinsic::nvvm_sqrt_rn_f:
440 switch (IntrinsicID) {
441 case Intrinsic::nvvm_rcp_rm_ftz_f:
442 case Intrinsic::nvvm_rcp_rn_ftz_f:
443 case Intrinsic::nvvm_rcp_rp_ftz_f:
444 case Intrinsic::nvvm_rcp_rz_ftz_f:
446 case Intrinsic::nvvm_rcp_rm_d:
447 case Intrinsic::nvvm_rcp_rm_f:
448 case Intrinsic::nvvm_rcp_rn_d:
449 case Intrinsic::nvvm_rcp_rn_f:
450 case Intrinsic::nvvm_rcp_rp_d:
451 case Intrinsic::nvvm_rcp_rp_f:
452 case Intrinsic::nvvm_rcp_rz_d:
453 case Intrinsic::nvvm_rcp_rz_f:
460 switch (IntrinsicID) {
461 case Intrinsic::nvvm_rcp_rm_f:
462 case Intrinsic::nvvm_rcp_rm_d:
463 case Intrinsic::nvvm_rcp_rm_ftz_f:
466 case Intrinsic::nvvm_rcp_rn_f:
467 case Intrinsic::nvvm_rcp_rn_d:
468 case Intrinsic::nvvm_rcp_rn_ftz_f:
471 case Intrinsic::nvvm_rcp_rp_f:
472 case Intrinsic::nvvm_rcp_rp_d:
473 case Intrinsic::nvvm_rcp_rp_ftz_f:
476 case Intrinsic::nvvm_rcp_rz_f:
477 case Intrinsic::nvvm_rcp_rz_d:
478 case Intrinsic::nvvm_rcp_rz_ftz_f:
491 switch (IntrinsicID) {
492 case Intrinsic::nvvm_add_rm_ftz_f:
493 case Intrinsic::nvvm_add_rn_ftz_f:
494 case Intrinsic::nvvm_add_rp_ftz_f:
495 case Intrinsic::nvvm_add_rz_ftz_f:
498 case Intrinsic::nvvm_add_rm_f:
499 case Intrinsic::nvvm_add_rn_f:
500 case Intrinsic::nvvm_add_rp_f:
501 case Intrinsic::nvvm_add_rz_f:
502 case Intrinsic::nvvm_add_rm_d:
503 case Intrinsic::nvvm_add_rn_d:
504 case Intrinsic::nvvm_add_rp_d:
505 case Intrinsic::nvvm_add_rz_d:
512 switch (IntrinsicID) {
513 case Intrinsic::nvvm_add_rm_f:
514 case Intrinsic::nvvm_add_rm_d:
515 case Intrinsic::nvvm_add_rm_ftz_f:
517 case Intrinsic::nvvm_add_rn_f:
518 case Intrinsic::nvvm_add_rn_d:
519 case Intrinsic::nvvm_add_rn_ftz_f:
521 case Intrinsic::nvvm_add_rp_f:
522 case Intrinsic::nvvm_add_rp_d:
523 case Intrinsic::nvvm_add_rp_ftz_f:
525 case Intrinsic::nvvm_add_rz_f:
526 case Intrinsic::nvvm_add_rz_d:
527 case Intrinsic::nvvm_add_rz_ftz_f:
534 switch (IntrinsicID) {
535 case Intrinsic::nvvm_mul_rm_ftz_f:
536 case Intrinsic::nvvm_mul_rn_ftz_f:
537 case Intrinsic::nvvm_mul_rp_ftz_f:
538 case Intrinsic::nvvm_mul_rz_ftz_f:
541 case Intrinsic::nvvm_mul_rm_f:
542 case Intrinsic::nvvm_mul_rn_f:
543 case Intrinsic::nvvm_mul_rp_f:
544 case Intrinsic::nvvm_mul_rz_f:
545 case Intrinsic::nvvm_mul_rm_d:
546 case Intrinsic::nvvm_mul_rn_d:
547 case Intrinsic::nvvm_mul_rp_d:
548 case Intrinsic::nvvm_mul_rz_d:
555 switch (IntrinsicID) {
556 case Intrinsic::nvvm_mul_rm_f:
557 case Intrinsic::nvvm_mul_rm_d:
558 case Intrinsic::nvvm_mul_rm_ftz_f:
560 case Intrinsic::nvvm_mul_rn_f:
561 case Intrinsic::nvvm_mul_rn_d:
562 case Intrinsic::nvvm_mul_rn_ftz_f:
564 case Intrinsic::nvvm_mul_rp_f:
565 case Intrinsic::nvvm_mul_rp_d:
566 case Intrinsic::nvvm_mul_rp_ftz_f:
568 case Intrinsic::nvvm_mul_rz_f:
569 case Intrinsic::nvvm_mul_rz_d:
570 case Intrinsic::nvvm_mul_rz_ftz_f:
577 switch (IntrinsicID) {
578 case Intrinsic::nvvm_div_rm_ftz_f:
579 case Intrinsic::nvvm_div_rn_ftz_f:
580 case Intrinsic::nvvm_div_rp_ftz_f:
581 case Intrinsic::nvvm_div_rz_ftz_f:
584 case Intrinsic::nvvm_div_rm_f:
585 case Intrinsic::nvvm_div_rn_f:
586 case Intrinsic::nvvm_div_rp_f:
587 case Intrinsic::nvvm_div_rz_f:
588 case Intrinsic::nvvm_div_rm_d:
589 case Intrinsic::nvvm_div_rn_d:
590 case Intrinsic::nvvm_div_rp_d:
591 case Intrinsic::nvvm_div_rz_d:
598 switch (IntrinsicID) {
599 case Intrinsic::nvvm_div_rm_f:
600 case Intrinsic::nvvm_div_rm_d:
601 case Intrinsic::nvvm_div_rm_ftz_f:
603 case Intrinsic::nvvm_div_rn_f:
604 case Intrinsic::nvvm_div_rn_d:
605 case Intrinsic::nvvm_div_rn_ftz_f:
607 case Intrinsic::nvvm_div_rp_f:
608 case Intrinsic::nvvm_div_rp_d:
609 case Intrinsic::nvvm_div_rp_ftz_f:
611 case Intrinsic::nvvm_div_rz_f:
612 case Intrinsic::nvvm_div_rz_d:
613 case Intrinsic::nvvm_div_rz_ftz_f:
620 switch (IntrinsicID) {
621 case Intrinsic::nvvm_fma_rm_ftz_f:
622 case Intrinsic::nvvm_fma_rn_ftz_f:
623 case Intrinsic::nvvm_fma_rp_ftz_f:
624 case Intrinsic::nvvm_fma_rz_ftz_f:
627 case Intrinsic::nvvm_fma_rm_f:
628 case Intrinsic::nvvm_fma_rn_f:
629 case Intrinsic::nvvm_fma_rp_f:
630 case Intrinsic::nvvm_fma_rz_f:
631 case Intrinsic::nvvm_fma_rm_d:
632 case Intrinsic::nvvm_fma_rn_d:
633 case Intrinsic::nvvm_fma_rp_d:
634 case Intrinsic::nvvm_fma_rz_d:
641 switch (IntrinsicID) {
642 case Intrinsic::nvvm_fma_rm_f:
643 case Intrinsic::nvvm_fma_rm_d:
644 case Intrinsic::nvvm_fma_rm_ftz_f:
646 case Intrinsic::nvvm_fma_rn_f:
647 case Intrinsic::nvvm_fma_rn_d:
648 case Intrinsic::nvvm_fma_rn_ftz_f:
650 case Intrinsic::nvvm_fma_rp_f:
651 case Intrinsic::nvvm_fma_rp_d:
652 case Intrinsic::nvvm_fma_rp_ftz_f:
654 case Intrinsic::nvvm_fma_rz_f:
655 case Intrinsic::nvvm_fma_rz_d:
656 case Intrinsic::nvvm_fma_rz_ftz_f:
This file declares a class to represent arbitrary precision floating point values and provide a varie...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
APFloat::roundingMode GetFMARoundingMode(Intrinsic::ID IntrinsicID)
DenormalMode GetNVVMDenormMode(bool ShouldFTZ)
bool FPToIntegerIntrinsicNaNZero(Intrinsic::ID IntrinsicID)
APFloat::roundingMode GetFDivRoundingMode(Intrinsic::ID IntrinsicID)
bool FPToIntegerIntrinsicResultIsSigned(Intrinsic::ID IntrinsicID)
APFloat::roundingMode GetFPToIntegerRoundingMode(Intrinsic::ID IntrinsicID)
bool RCPShouldFTZ(Intrinsic::ID IntrinsicID)
bool FPToIntegerIntrinsicShouldFTZ(Intrinsic::ID IntrinsicID)
bool FDivShouldFTZ(Intrinsic::ID IntrinsicID)
bool FAddShouldFTZ(Intrinsic::ID IntrinsicID)
bool FMinFMaxIsXorSignAbs(Intrinsic::ID IntrinsicID)
APFloat::roundingMode GetFMulRoundingMode(Intrinsic::ID IntrinsicID)
bool UnaryMathIntrinsicShouldFTZ(Intrinsic::ID IntrinsicID)
bool FMinFMaxShouldFTZ(Intrinsic::ID IntrinsicID)
APFloat::roundingMode GetFAddRoundingMode(Intrinsic::ID IntrinsicID)
bool FMAShouldFTZ(Intrinsic::ID IntrinsicID)
bool FMulShouldFTZ(Intrinsic::ID IntrinsicID)
APFloat::roundingMode GetRCPRoundingMode(Intrinsic::ID IntrinsicID)
bool FMinFMaxPropagatesNaNs(Intrinsic::ID IntrinsicID)
This is an optimization pass for GlobalISel generic memory operations.
static constexpr roundingMode rmTowardNegative
llvm::RoundingMode roundingMode
IEEE-754R 4.3: Rounding-direction attributes.
static constexpr roundingMode rmNearestTiesToEven
static constexpr roundingMode rmTowardZero
static constexpr roundingMode rmTowardPositive
Represent subnormal handling kind for floating point instruction inputs and outputs.
static constexpr DenormalMode getPreserveSign()
static constexpr DenormalMode getIEEE()