LLVM 22.0.0git
RISCVVLOptimizer.cpp
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1//===-------------- RISCVVLOptimizer.cpp - VL Optimizer -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===---------------------------------------------------------------------===//
8//
9// This pass reduces the VL where possible at the MI level, before VSETVLI
10// instructions are inserted.
11//
12// The purpose of this optimization is to make the VL argument, for instructions
13// that have a VL argument, as small as possible. This is implemented by
14// visiting each instruction in reverse order and checking that if it has a VL
15// argument, whether the VL can be reduced.
16//
17//===---------------------------------------------------------------------===//
18
19#include "RISCV.h"
20#include "RISCVSubtarget.h"
21#include "llvm/ADT/PostOrderIterator.h"
22#include "llvm/CodeGen/MachineDominators.h"
23#include "llvm/CodeGen/MachineFunctionPass.h"
24#include "llvm/InitializePasses.h"
25
26using namespace llvm;
27
28#define DEBUG_TYPE "riscv-vl-optimizer"
29#define PASS_NAME "RISC-V VL Optimizer"
30
31namespace {
32
33class RISCVVLOptimizer : public MachineFunctionPass {
34 const MachineRegisterInfo *MRI;
35 const MachineDominatorTree *MDT;
36 const TargetInstrInfo *TII;
37
38public:
39 static char ID;
40
41 RISCVVLOptimizer() : MachineFunctionPass(ID) {}
42
43 bool runOnMachineFunction(MachineFunction &MF) override;
44
45 void getAnalysisUsage(AnalysisUsage &AU) const override {
46 AU.setPreservesCFG();
47 AU.addRequired<MachineDominatorTreeWrapperPass>();
48 MachineFunctionPass::getAnalysisUsage(AU);
49 }
50
51 StringRef getPassName() const override { return PASS_NAME; }
52
53private:
54 std::optional<MachineOperand>
55 getMinimumVLForUser(const MachineOperand &UserOp) const;
56 /// Returns the largest common VL MachineOperand that may be used to optimize
57 /// MI. Returns std::nullopt if it failed to find a suitable VL.
58 std::optional<MachineOperand> checkUsers(const MachineInstr &MI) const;
59 bool tryReduceVL(MachineInstr &MI) const;
60 bool isCandidate(const MachineInstr &MI) const;
61
62 /// For a given instruction, records what elements of it are demanded by
63 /// downstream users.
64 DenseMap<const MachineInstr *, std::optional<MachineOperand>> DemandedVLs;
65};
66
67/// Represents the EMUL and EEW of a MachineOperand.
68struct OperandInfo {
69 // Represent as 1,2,4,8, ... and fractional indicator. This is because
70 // EMUL can take on values that don't map to RISCVVType::VLMUL values exactly.
71 // For example, a mask operand can have an EMUL less than MF8.
72 // If nullopt, then EMUL isn't used (i.e. only a single scalar is read).
73 std::optional<std::pair<unsigned, bool>> EMUL;
74
75 unsigned Log2EEW;
76
77 OperandInfo(RISCVVType::VLMUL EMUL, unsigned Log2EEW)
78 : EMUL(RISCVVType::decodeVLMUL(EMUL)), Log2EEW(Log2EEW) {}
79
80 OperandInfo(std::pair<unsigned, bool> EMUL, unsigned Log2EEW)
81 : EMUL(EMUL), Log2EEW(Log2EEW) {}
82
83 OperandInfo(unsigned Log2EEW) : Log2EEW(Log2EEW) {}
84
85 OperandInfo() = delete;
86
87 /// Return true if the EMUL and EEW produced by \p Def is compatible with the
88 /// EMUL and EEW used by \p User.
89 static bool areCompatible(const OperandInfo &Def, const OperandInfo &User) {
90 if (Def.Log2EEW != User.Log2EEW)
91 return false;
92 if (User.EMUL && Def.EMUL != User.EMUL)
93 return false;
94 return true;
95 }
96
97 void print(raw_ostream &OS) const {
98 if (EMUL) {
99 OS << "EMUL: m";
100 if (EMUL->second)
101 OS << "f";
102 OS << EMUL->first;
103 } else
104 OS << "EMUL: none\n";
105 OS << ", EEW: " << (1 << Log2EEW);
106 }
107};
108
109} // end anonymous namespace
110
111char RISCVVLOptimizer::ID = 0;
112INITIALIZE_PASS_BEGIN(RISCVVLOptimizer, DEBUG_TYPE, PASS_NAME, false, false)
113INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
114INITIALIZE_PASS_END(RISCVVLOptimizer, DEBUG_TYPE, PASS_NAME, false, false)
115
116FunctionPass *llvm::createRISCVVLOptimizerPass() {
117 return new RISCVVLOptimizer();
118}
119
120LLVM_ATTRIBUTE_UNUSED
121static raw_ostream &operator<<(raw_ostream &OS, const OperandInfo &OI) {
122 OI.print(OS);
123 return OS;
124}
125
126LLVM_ATTRIBUTE_UNUSED
127static raw_ostream &operator<<(raw_ostream &OS,
128 const std::optional<OperandInfo> &OI) {
129 if (OI)
130 OI->print(OS);
131 else
132 OS << "nullopt";
133 return OS;
134}
135
136/// Return EMUL = (EEW / SEW) * LMUL where EEW comes from Log2EEW and LMUL and
137/// SEW are from the TSFlags of MI.
138static std::pair<unsigned, bool>
139getEMULEqualsEEWDivSEWTimesLMUL(unsigned Log2EEW, const MachineInstr &MI) {
140 RISCVVType::VLMUL MIVLMUL = RISCVII::getLMul(MI.getDesc().TSFlags);
141 auto [MILMUL, MILMULIsFractional] = RISCVVType::decodeVLMUL(MIVLMUL);
142 unsigned MILog2SEW =
143 MI.getOperand(RISCVII::getSEWOpNum(MI.getDesc())).getImm();
144
145 // Mask instructions will have 0 as the SEW operand. But the LMUL of these
146 // instructions is calculated is as if the SEW operand was 3 (e8).
147 if (MILog2SEW == 0)
148 MILog2SEW = 3;
149
150 unsigned MISEW = 1 << MILog2SEW;
151
152 unsigned EEW = 1 << Log2EEW;
153 // Calculate (EEW/SEW)*LMUL preserving fractions less than 1. Use GCD
154 // to put fraction in simplest form.
155 unsigned Num = EEW, Denom = MISEW;
156 int GCD = MILMULIsFractional ? std::gcd(Num, Denom * MILMUL)
157 : std::gcd(Num * MILMUL, Denom);
158 Num = MILMULIsFractional ? Num / GCD : Num * MILMUL / GCD;
159 Denom = MILMULIsFractional ? Denom * MILMUL / GCD : Denom / GCD;
160 return std::make_pair(Num > Denom ? Num : Denom, Denom > Num);
161}
162
163/// Dest has EEW=SEW. Source EEW=SEW/Factor (i.e. F2 => EEW/2).
164/// SEW comes from TSFlags of MI.
165static unsigned getIntegerExtensionOperandEEW(unsigned Factor,
166 const MachineInstr &MI,
167 const MachineOperand &MO) {
168 unsigned MILog2SEW =
169 MI.getOperand(RISCVII::getSEWOpNum(MI.getDesc())).getImm();
170
171 if (MO.getOperandNo() == 0)
172 return MILog2SEW;
173
174 unsigned MISEW = 1 << MILog2SEW;
175 unsigned EEW = MISEW / Factor;
176 unsigned Log2EEW = Log2_32(EEW);
177
178 return Log2EEW;
179}
180
181static std::optional<unsigned>
182getOperandLog2EEW(const MachineOperand &MO, const MachineRegisterInfo *MRI) {
183 const MachineInstr &MI = *MO.getParent();
184 const MCInstrDesc &Desc = MI.getDesc();
185 const RISCVVPseudosTable::PseudoInfo *RVV =
186 RISCVVPseudosTable::getPseudoInfo(MI.getOpcode());
187 assert(RVV && "Could not find MI in PseudoTable");
188
189 // MI has a SEW associated with it. The RVV specification defines
190 // the EEW of each operand and definition in relation to MI.SEW.
191 unsigned MILog2SEW = MI.getOperand(RISCVII::getSEWOpNum(Desc)).getImm();
192
193 const bool HasPassthru = RISCVII::isFirstDefTiedToFirstUse(Desc);
194 const bool IsTied = RISCVII::isTiedPseudo(Desc.TSFlags);
195
196 bool IsMODef = MO.getOperandNo() == 0 ||
197 (HasPassthru && MO.getOperandNo() == MI.getNumExplicitDefs());
198
199 // All mask operands have EEW=1
200 const MCOperandInfo &Info = Desc.operands()[MO.getOperandNo()];
201 if (Info.OperandType == MCOI::OPERAND_REGISTER &&
202 Info.RegClass == RISCV::VMV0RegClassID)
203 return 0;
204
205 // switch against BaseInstr to reduce number of cases that need to be
206 // considered.
207 switch (RVV->BaseInstr) {
208
209 // 6. Configuration-Setting Instructions
210 // Configuration setting instructions do not read or write vector registers
211 case RISCV::VSETIVLI:
212 case RISCV::VSETVL:
213 case RISCV::VSETVLI:
214 llvm_unreachable("Configuration setting instructions do not read or write "
215 "vector registers");
216
217 // Vector Loads and Stores
218 // Vector Unit-Stride Instructions
219 // Vector Strided Instructions
220 /// Dest EEW encoded in the instruction
221 case RISCV::VLM_V:
222 case RISCV::VSM_V:
223 return 0;
224 case RISCV::VLE8_V:
225 case RISCV::VSE8_V:
226 case RISCV::VLSE8_V:
227 case RISCV::VSSE8_V:
228 return 3;
229 case RISCV::VLE16_V:
230 case RISCV::VSE16_V:
231 case RISCV::VLSE16_V:
232 case RISCV::VSSE16_V:
233 return 4;
234 case RISCV::VLE32_V:
235 case RISCV::VSE32_V:
236 case RISCV::VLSE32_V:
237 case RISCV::VSSE32_V:
238 return 5;
239 case RISCV::VLE64_V:
240 case RISCV::VSE64_V:
241 case RISCV::VLSE64_V:
242 case RISCV::VSSE64_V:
243 return 6;
244
245 // Vector Indexed Instructions
246 // vs(o|u)xei<eew>.v
247 // Dest/Data (operand 0) EEW=SEW. Source EEW=<eew>.
248 case RISCV::VLUXEI8_V:
249 case RISCV::VLOXEI8_V:
250 case RISCV::VSUXEI8_V:
251 case RISCV::VSOXEI8_V: {
252 if (MO.getOperandNo() == 0)
253 return MILog2SEW;
254 return 3;
255 }
256 case RISCV::VLUXEI16_V:
257 case RISCV::VLOXEI16_V:
258 case RISCV::VSUXEI16_V:
259 case RISCV::VSOXEI16_V: {
260 if (MO.getOperandNo() == 0)
261 return MILog2SEW;
262 return 4;
263 }
264 case RISCV::VLUXEI32_V:
265 case RISCV::VLOXEI32_V:
266 case RISCV::VSUXEI32_V:
267 case RISCV::VSOXEI32_V: {
268 if (MO.getOperandNo() == 0)
269 return MILog2SEW;
270 return 5;
271 }
272 case RISCV::VLUXEI64_V:
273 case RISCV::VLOXEI64_V:
274 case RISCV::VSUXEI64_V:
275 case RISCV::VSOXEI64_V: {
276 if (MO.getOperandNo() == 0)
277 return MILog2SEW;
278 return 6;
279 }
280
281 // Vector Integer Arithmetic Instructions
282 // Vector Single-Width Integer Add and Subtract
283 case RISCV::VADD_VI:
284 case RISCV::VADD_VV:
285 case RISCV::VADD_VX:
286 case RISCV::VSUB_VV:
287 case RISCV::VSUB_VX:
288 case RISCV::VRSUB_VI:
289 case RISCV::VRSUB_VX:
290 // Vector Bitwise Logical Instructions
291 // Vector Single-Width Shift Instructions
292 // EEW=SEW.
293 case RISCV::VAND_VI:
294 case RISCV::VAND_VV:
295 case RISCV::VAND_VX:
296 case RISCV::VOR_VI:
297 case RISCV::VOR_VV:
298 case RISCV::VOR_VX:
299 case RISCV::VXOR_VI:
300 case RISCV::VXOR_VV:
301 case RISCV::VXOR_VX:
302 case RISCV::VSLL_VI:
303 case RISCV::VSLL_VV:
304 case RISCV::VSLL_VX:
305 case RISCV::VSRL_VI:
306 case RISCV::VSRL_VV:
307 case RISCV::VSRL_VX:
308 case RISCV::VSRA_VI:
309 case RISCV::VSRA_VV:
310 case RISCV::VSRA_VX:
311 // Vector Integer Min/Max Instructions
312 // EEW=SEW.
313 case RISCV::VMINU_VV:
314 case RISCV::VMINU_VX:
315 case RISCV::VMIN_VV:
316 case RISCV::VMIN_VX:
317 case RISCV::VMAXU_VV:
318 case RISCV::VMAXU_VX:
319 case RISCV::VMAX_VV:
320 case RISCV::VMAX_VX:
321 // Vector Single-Width Integer Multiply Instructions
322 // Source and Dest EEW=SEW.
323 case RISCV::VMUL_VV:
324 case RISCV::VMUL_VX:
325 case RISCV::VMULH_VV:
326 case RISCV::VMULH_VX:
327 case RISCV::VMULHU_VV:
328 case RISCV::VMULHU_VX:
329 case RISCV::VMULHSU_VV:
330 case RISCV::VMULHSU_VX:
331 // Vector Integer Divide Instructions
332 // EEW=SEW.
333 case RISCV::VDIVU_VV:
334 case RISCV::VDIVU_VX:
335 case RISCV::VDIV_VV:
336 case RISCV::VDIV_VX:
337 case RISCV::VREMU_VV:
338 case RISCV::VREMU_VX:
339 case RISCV::VREM_VV:
340 case RISCV::VREM_VX:
341 // Vector Single-Width Integer Multiply-Add Instructions
342 // EEW=SEW.
343 case RISCV::VMACC_VV:
344 case RISCV::VMACC_VX:
345 case RISCV::VNMSAC_VV:
346 case RISCV::VNMSAC_VX:
347 case RISCV::VMADD_VV:
348 case RISCV::VMADD_VX:
349 case RISCV::VNMSUB_VV:
350 case RISCV::VNMSUB_VX:
351 // Vector Integer Merge Instructions
352 // Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
353 // EEW=SEW, except the mask operand has EEW=1. Mask operand is handled
354 // before this switch.
355 case RISCV::VMERGE_VIM:
356 case RISCV::VMERGE_VVM:
357 case RISCV::VMERGE_VXM:
358 case RISCV::VADC_VIM:
359 case RISCV::VADC_VVM:
360 case RISCV::VADC_VXM:
361 case RISCV::VSBC_VVM:
362 case RISCV::VSBC_VXM:
363 // Vector Integer Move Instructions
364 // Vector Fixed-Point Arithmetic Instructions
365 // Vector Single-Width Saturating Add and Subtract
366 // Vector Single-Width Averaging Add and Subtract
367 // EEW=SEW.
368 case RISCV::VMV_V_I:
369 case RISCV::VMV_V_V:
370 case RISCV::VMV_V_X:
371 case RISCV::VSADDU_VI:
372 case RISCV::VSADDU_VV:
373 case RISCV::VSADDU_VX:
374 case RISCV::VSADD_VI:
375 case RISCV::VSADD_VV:
376 case RISCV::VSADD_VX:
377 case RISCV::VSSUBU_VV:
378 case RISCV::VSSUBU_VX:
379 case RISCV::VSSUB_VV:
380 case RISCV::VSSUB_VX:
381 case RISCV::VAADDU_VV:
382 case RISCV::VAADDU_VX:
383 case RISCV::VAADD_VV:
384 case RISCV::VAADD_VX:
385 case RISCV::VASUBU_VV:
386 case RISCV::VASUBU_VX:
387 case RISCV::VASUB_VV:
388 case RISCV::VASUB_VX:
389 // Vector Single-Width Fractional Multiply with Rounding and Saturation
390 // EEW=SEW. The instruction produces 2*SEW product internally but
391 // saturates to fit into SEW bits.
392 case RISCV::VSMUL_VV:
393 case RISCV::VSMUL_VX:
394 // Vector Single-Width Scaling Shift Instructions
395 // EEW=SEW.
396 case RISCV::VSSRL_VI:
397 case RISCV::VSSRL_VV:
398 case RISCV::VSSRL_VX:
399 case RISCV::VSSRA_VI:
400 case RISCV::VSSRA_VV:
401 case RISCV::VSSRA_VX:
402 // Vector Permutation Instructions
403 // Integer Scalar Move Instructions
404 // Floating-Point Scalar Move Instructions
405 // EEW=SEW.
406 case RISCV::VMV_X_S:
407 case RISCV::VMV_S_X:
408 case RISCV::VFMV_F_S:
409 case RISCV::VFMV_S_F:
410 // Vector Slide Instructions
411 // EEW=SEW.
412 case RISCV::VSLIDEUP_VI:
413 case RISCV::VSLIDEUP_VX:
414 case RISCV::VSLIDEDOWN_VI:
415 case RISCV::VSLIDEDOWN_VX:
416 case RISCV::VSLIDE1UP_VX:
417 case RISCV::VFSLIDE1UP_VF:
418 case RISCV::VSLIDE1DOWN_VX:
419 case RISCV::VFSLIDE1DOWN_VF:
420 // Vector Register Gather Instructions
421 // EEW=SEW. For mask operand, EEW=1.
422 case RISCV::VRGATHER_VI:
423 case RISCV::VRGATHER_VV:
424 case RISCV::VRGATHER_VX:
425 // Vector Compress Instruction
426 // EEW=SEW.
427 case RISCV::VCOMPRESS_VM:
428 // Vector Element Index Instruction
429 case RISCV::VID_V:
430 // Vector Single-Width Floating-Point Add/Subtract Instructions
431 case RISCV::VFADD_VF:
432 case RISCV::VFADD_VV:
433 case RISCV::VFSUB_VF:
434 case RISCV::VFSUB_VV:
435 case RISCV::VFRSUB_VF:
436 // Vector Single-Width Floating-Point Multiply/Divide Instructions
437 case RISCV::VFMUL_VF:
438 case RISCV::VFMUL_VV:
439 case RISCV::VFDIV_VF:
440 case RISCV::VFDIV_VV:
441 case RISCV::VFRDIV_VF:
442 // Vector Single-Width Floating-Point Fused Multiply-Add Instructions
443 case RISCV::VFMACC_VV:
444 case RISCV::VFMACC_VF:
445 case RISCV::VFNMACC_VV:
446 case RISCV::VFNMACC_VF:
447 case RISCV::VFMSAC_VV:
448 case RISCV::VFMSAC_VF:
449 case RISCV::VFNMSAC_VV:
450 case RISCV::VFNMSAC_VF:
451 case RISCV::VFMADD_VV:
452 case RISCV::VFMADD_VF:
453 case RISCV::VFNMADD_VV:
454 case RISCV::VFNMADD_VF:
455 case RISCV::VFMSUB_VV:
456 case RISCV::VFMSUB_VF:
457 case RISCV::VFNMSUB_VV:
458 case RISCV::VFNMSUB_VF:
459 // Vector Floating-Point Square-Root Instruction
460 case RISCV::VFSQRT_V:
461 // Vector Floating-Point Reciprocal Square-Root Estimate Instruction
462 case RISCV::VFRSQRT7_V:
463 // Vector Floating-Point Reciprocal Estimate Instruction
464 case RISCV::VFREC7_V:
465 // Vector Floating-Point MIN/MAX Instructions
466 case RISCV::VFMIN_VF:
467 case RISCV::VFMIN_VV:
468 case RISCV::VFMAX_VF:
469 case RISCV::VFMAX_VV:
470 // Vector Floating-Point Sign-Injection Instructions
471 case RISCV::VFSGNJ_VF:
472 case RISCV::VFSGNJ_VV:
473 case RISCV::VFSGNJN_VV:
474 case RISCV::VFSGNJN_VF:
475 case RISCV::VFSGNJX_VF:
476 case RISCV::VFSGNJX_VV:
477 // Vector Floating-Point Classify Instruction
478 case RISCV::VFCLASS_V:
479 // Vector Floating-Point Move Instruction
480 case RISCV::VFMV_V_F:
481 // Single-Width Floating-Point/Integer Type-Convert Instructions
482 case RISCV::VFCVT_XU_F_V:
483 case RISCV::VFCVT_X_F_V:
484 case RISCV::VFCVT_RTZ_XU_F_V:
485 case RISCV::VFCVT_RTZ_X_F_V:
486 case RISCV::VFCVT_F_XU_V:
487 case RISCV::VFCVT_F_X_V:
488 // Vector Floating-Point Merge Instruction
489 case RISCV::VFMERGE_VFM:
490 // Vector count population in mask vcpop.m
491 // vfirst find-first-set mask bit
492 case RISCV::VCPOP_M:
493 case RISCV::VFIRST_M:
494 // Vector Bit-manipulation Instructions (Zvbb)
495 // Vector And-Not
496 case RISCV::VANDN_VV:
497 case RISCV::VANDN_VX:
498 // Vector Reverse Bits in Elements
499 case RISCV::VBREV_V:
500 // Vector Reverse Bits in Bytes
501 case RISCV::VBREV8_V:
502 // Vector Reverse Bytes
503 case RISCV::VREV8_V:
504 // Vector Count Leading Zeros
505 case RISCV::VCLZ_V:
506 // Vector Count Trailing Zeros
507 case RISCV::VCTZ_V:
508 // Vector Population Count
509 case RISCV::VCPOP_V:
510 // Vector Rotate Left
511 case RISCV::VROL_VV:
512 case RISCV::VROL_VX:
513 // Vector Rotate Right
514 case RISCV::VROR_VI:
515 case RISCV::VROR_VV:
516 case RISCV::VROR_VX:
517 // Vector Carry-less Multiplication Instructions (Zvbc)
518 // Vector Carry-less Multiply
519 case RISCV::VCLMUL_VV:
520 case RISCV::VCLMUL_VX:
521 // Vector Carry-less Multiply Return High Half
522 case RISCV::VCLMULH_VV:
523 case RISCV::VCLMULH_VX:
524 return MILog2SEW;
525
526 // Vector Widening Shift Left Logical (Zvbb)
527 case RISCV::VWSLL_VI:
528 case RISCV::VWSLL_VX:
529 case RISCV::VWSLL_VV:
530 // Vector Widening Integer Add/Subtract
531 // Def uses EEW=2*SEW . Operands use EEW=SEW.
532 case RISCV::VWADDU_VV:
533 case RISCV::VWADDU_VX:
534 case RISCV::VWSUBU_VV:
535 case RISCV::VWSUBU_VX:
536 case RISCV::VWADD_VV:
537 case RISCV::VWADD_VX:
538 case RISCV::VWSUB_VV:
539 case RISCV::VWSUB_VX:
540 // Vector Widening Integer Multiply Instructions
541 // Destination EEW=2*SEW. Source EEW=SEW.
542 case RISCV::VWMUL_VV:
543 case RISCV::VWMUL_VX:
544 case RISCV::VWMULSU_VV:
545 case RISCV::VWMULSU_VX:
546 case RISCV::VWMULU_VV:
547 case RISCV::VWMULU_VX:
548 // Vector Widening Integer Multiply-Add Instructions
549 // Destination EEW=2*SEW. Source EEW=SEW.
550 // A SEW-bit*SEW-bit multiply of the sources forms a 2*SEW-bit value, which
551 // is then added to the 2*SEW-bit Dest. These instructions never have a
552 // passthru operand.
553 case RISCV::VWMACCU_VV:
554 case RISCV::VWMACCU_VX:
555 case RISCV::VWMACC_VV:
556 case RISCV::VWMACC_VX:
557 case RISCV::VWMACCSU_VV:
558 case RISCV::VWMACCSU_VX:
559 case RISCV::VWMACCUS_VX:
560 // Vector Widening Floating-Point Fused Multiply-Add Instructions
561 case RISCV::VFWMACC_VF:
562 case RISCV::VFWMACC_VV:
563 case RISCV::VFWNMACC_VF:
564 case RISCV::VFWNMACC_VV:
565 case RISCV::VFWMSAC_VF:
566 case RISCV::VFWMSAC_VV:
567 case RISCV::VFWNMSAC_VF:
568 case RISCV::VFWNMSAC_VV:
569 case RISCV::VFWMACCBF16_VV:
570 case RISCV::VFWMACCBF16_VF:
571 // Vector Widening Floating-Point Add/Subtract Instructions
572 // Dest EEW=2*SEW. Source EEW=SEW.
573 case RISCV::VFWADD_VV:
574 case RISCV::VFWADD_VF:
575 case RISCV::VFWSUB_VV:
576 case RISCV::VFWSUB_VF:
577 // Vector Widening Floating-Point Multiply
578 case RISCV::VFWMUL_VF:
579 case RISCV::VFWMUL_VV:
580 // Widening Floating-Point/Integer Type-Convert Instructions
581 case RISCV::VFWCVT_XU_F_V:
582 case RISCV::VFWCVT_X_F_V:
583 case RISCV::VFWCVT_RTZ_XU_F_V:
584 case RISCV::VFWCVT_RTZ_X_F_V:
585 case RISCV::VFWCVT_F_XU_V:
586 case RISCV::VFWCVT_F_X_V:
587 case RISCV::VFWCVT_F_F_V:
588 case RISCV::VFWCVTBF16_F_F_V:
589 return IsMODef ? MILog2SEW + 1 : MILog2SEW;
590
591 // Def and Op1 uses EEW=2*SEW. Op2 uses EEW=SEW.
592 case RISCV::VWADDU_WV:
593 case RISCV::VWADDU_WX:
594 case RISCV::VWSUBU_WV:
595 case RISCV::VWSUBU_WX:
596 case RISCV::VWADD_WV:
597 case RISCV::VWADD_WX:
598 case RISCV::VWSUB_WV:
599 case RISCV::VWSUB_WX:
600 // Vector Widening Floating-Point Add/Subtract Instructions
601 case RISCV::VFWADD_WF:
602 case RISCV::VFWADD_WV:
603 case RISCV::VFWSUB_WF:
604 case RISCV::VFWSUB_WV: {
605 bool IsOp1 = (HasPassthru && !IsTied) ? MO.getOperandNo() == 2
606 : MO.getOperandNo() == 1;
607 bool TwoTimes = IsMODef || IsOp1;
608 return TwoTimes ? MILog2SEW + 1 : MILog2SEW;
609 }
610
611 // Vector Integer Extension
612 case RISCV::VZEXT_VF2:
613 case RISCV::VSEXT_VF2:
614 return getIntegerExtensionOperandEEW(2, MI, MO);
615 case RISCV::VZEXT_VF4:
616 case RISCV::VSEXT_VF4:
617 return getIntegerExtensionOperandEEW(4, MI, MO);
618 case RISCV::VZEXT_VF8:
619 case RISCV::VSEXT_VF8:
620 return getIntegerExtensionOperandEEW(8, MI, MO);
621
622 // Vector Narrowing Integer Right Shift Instructions
623 // Destination EEW=SEW, Op 1 has EEW=2*SEW. Op2 has EEW=SEW
624 case RISCV::VNSRL_WX:
625 case RISCV::VNSRL_WI:
626 case RISCV::VNSRL_WV:
627 case RISCV::VNSRA_WI:
628 case RISCV::VNSRA_WV:
629 case RISCV::VNSRA_WX:
630 // Vector Narrowing Fixed-Point Clip Instructions
631 // Destination and Op1 EEW=SEW. Op2 EEW=2*SEW.
632 case RISCV::VNCLIPU_WI:
633 case RISCV::VNCLIPU_WV:
634 case RISCV::VNCLIPU_WX:
635 case RISCV::VNCLIP_WI:
636 case RISCV::VNCLIP_WV:
637 case RISCV::VNCLIP_WX:
638 // Narrowing Floating-Point/Integer Type-Convert Instructions
639 case RISCV::VFNCVT_XU_F_W:
640 case RISCV::VFNCVT_X_F_W:
641 case RISCV::VFNCVT_RTZ_XU_F_W:
642 case RISCV::VFNCVT_RTZ_X_F_W:
643 case RISCV::VFNCVT_F_XU_W:
644 case RISCV::VFNCVT_F_X_W:
645 case RISCV::VFNCVT_F_F_W:
646 case RISCV::VFNCVT_ROD_F_F_W:
647 case RISCV::VFNCVTBF16_F_F_W: {
648 assert(!IsTied);
649 bool IsOp1 = HasPassthru ? MO.getOperandNo() == 2 : MO.getOperandNo() == 1;
650 bool TwoTimes = IsOp1;
651 return TwoTimes ? MILog2SEW + 1 : MILog2SEW;
652 }
653
654 // Vector Mask Instructions
655 // Vector Mask-Register Logical Instructions
656 // vmsbf.m set-before-first mask bit
657 // vmsif.m set-including-first mask bit
658 // vmsof.m set-only-first mask bit
659 // EEW=1
660 // We handle the cases when operand is a v0 mask operand above the switch,
661 // but these instructions may use non-v0 mask operands and need to be handled
662 // specifically.
663 case RISCV::VMAND_MM:
664 case RISCV::VMNAND_MM:
665 case RISCV::VMANDN_MM:
666 case RISCV::VMXOR_MM:
667 case RISCV::VMOR_MM:
668 case RISCV::VMNOR_MM:
669 case RISCV::VMORN_MM:
670 case RISCV::VMXNOR_MM:
671 case RISCV::VMSBF_M:
672 case RISCV::VMSIF_M:
673 case RISCV::VMSOF_M: {
674 return MILog2SEW;
675 }
676
677 // Vector Iota Instruction
678 // EEW=SEW, except the mask operand has EEW=1. Mask operand is not handled
679 // before this switch.
680 case RISCV::VIOTA_M: {
681 if (IsMODef || MO.getOperandNo() == 1)
682 return MILog2SEW;
683 return 0;
684 }
685
686 // Vector Integer Compare Instructions
687 // Dest EEW=1. Source EEW=SEW.
688 case RISCV::VMSEQ_VI:
689 case RISCV::VMSEQ_VV:
690 case RISCV::VMSEQ_VX:
691 case RISCV::VMSNE_VI:
692 case RISCV::VMSNE_VV:
693 case RISCV::VMSNE_VX:
694 case RISCV::VMSLTU_VV:
695 case RISCV::VMSLTU_VX:
696 case RISCV::VMSLT_VV:
697 case RISCV::VMSLT_VX:
698 case RISCV::VMSLEU_VV:
699 case RISCV::VMSLEU_VI:
700 case RISCV::VMSLEU_VX:
701 case RISCV::VMSLE_VV:
702 case RISCV::VMSLE_VI:
703 case RISCV::VMSLE_VX:
704 case RISCV::VMSGTU_VI:
705 case RISCV::VMSGTU_VX:
706 case RISCV::VMSGT_VI:
707 case RISCV::VMSGT_VX:
708 // Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
709 // Dest EEW=1. Source EEW=SEW. Mask source operand handled above this switch.
710 case RISCV::VMADC_VIM:
711 case RISCV::VMADC_VVM:
712 case RISCV::VMADC_VXM:
713 case RISCV::VMSBC_VVM:
714 case RISCV::VMSBC_VXM:
715 // Dest EEW=1. Source EEW=SEW.
716 case RISCV::VMADC_VV:
717 case RISCV::VMADC_VI:
718 case RISCV::VMADC_VX:
719 case RISCV::VMSBC_VV:
720 case RISCV::VMSBC_VX:
721 // 13.13. Vector Floating-Point Compare Instructions
722 // Dest EEW=1. Source EEW=SEW
723 case RISCV::VMFEQ_VF:
724 case RISCV::VMFEQ_VV:
725 case RISCV::VMFNE_VF:
726 case RISCV::VMFNE_VV:
727 case RISCV::VMFLT_VF:
728 case RISCV::VMFLT_VV:
729 case RISCV::VMFLE_VF:
730 case RISCV::VMFLE_VV:
731 case RISCV::VMFGT_VF:
732 case RISCV::VMFGE_VF: {
733 if (IsMODef)
734 return 0;
735 return MILog2SEW;
736 }
737
738 // Vector Reduction Operations
739 // Vector Single-Width Integer Reduction Instructions
740 case RISCV::VREDAND_VS:
741 case RISCV::VREDMAX_VS:
742 case RISCV::VREDMAXU_VS:
743 case RISCV::VREDMIN_VS:
744 case RISCV::VREDMINU_VS:
745 case RISCV::VREDOR_VS:
746 case RISCV::VREDSUM_VS:
747 case RISCV::VREDXOR_VS:
748 // Vector Single-Width Floating-Point Reduction Instructions
749 case RISCV::VFREDMAX_VS:
750 case RISCV::VFREDMIN_VS:
751 case RISCV::VFREDOSUM_VS:
752 case RISCV::VFREDUSUM_VS: {
753 return MILog2SEW;
754 }
755
756 // Vector Widening Integer Reduction Instructions
757 // The Dest and VS1 read only element 0 for the vector register. Return
758 // 2*EEW for these. VS2 has EEW=SEW and EMUL=LMUL.
759 case RISCV::VWREDSUM_VS:
760 case RISCV::VWREDSUMU_VS:
761 // Vector Widening Floating-Point Reduction Instructions
762 case RISCV::VFWREDOSUM_VS:
763 case RISCV::VFWREDUSUM_VS: {
764 bool TwoTimes = IsMODef || MO.getOperandNo() == 3;
765 return TwoTimes ? MILog2SEW + 1 : MILog2SEW;
766 }
767
768 // Vector Register Gather with 16-bit Index Elements Instruction
769 // Dest and source data EEW=SEW. Index vector EEW=16.
770 case RISCV::VRGATHEREI16_VV: {
771 if (MO.getOperandNo() == 2)
772 return 4;
773 return MILog2SEW;
774 }
775
776 default:
777 return std::nullopt;
778 }
779}
780
781static std::optional<OperandInfo>
782getOperandInfo(const MachineOperand &MO, const MachineRegisterInfo *MRI) {
783 const MachineInstr &MI = *MO.getParent();
784 const RISCVVPseudosTable::PseudoInfo *RVV =
785 RISCVVPseudosTable::getPseudoInfo(MI.getOpcode());
786 assert(RVV && "Could not find MI in PseudoTable");
787
788 std::optional<unsigned> Log2EEW = getOperandLog2EEW(MO, MRI);
789 if (!Log2EEW)
790 return std::nullopt;
791
792 switch (RVV->BaseInstr) {
793 // Vector Reduction Operations
794 // Vector Single-Width Integer Reduction Instructions
795 // Vector Widening Integer Reduction Instructions
796 // Vector Widening Floating-Point Reduction Instructions
797 // The Dest and VS1 only read element 0 of the vector register. Return just
798 // the EEW for these.
799 case RISCV::VREDAND_VS:
800 case RISCV::VREDMAX_VS:
801 case RISCV::VREDMAXU_VS:
802 case RISCV::VREDMIN_VS:
803 case RISCV::VREDMINU_VS:
804 case RISCV::VREDOR_VS:
805 case RISCV::VREDSUM_VS:
806 case RISCV::VREDXOR_VS:
807 case RISCV::VWREDSUM_VS:
808 case RISCV::VWREDSUMU_VS:
809 case RISCV::VFWREDOSUM_VS:
810 case RISCV::VFWREDUSUM_VS:
811 if (MO.getOperandNo() != 2)
812 return OperandInfo(*Log2EEW);
813 break;
814 };
815
816 // All others have EMUL=EEW/SEW*LMUL
817 return OperandInfo(getEMULEqualsEEWDivSEWTimesLMUL(*Log2EEW, MI), *Log2EEW);
818}
819
820/// Return true if this optimization should consider MI for VL reduction. This
821/// white-list approach simplifies this optimization for instructions that may
822/// have more complex semantics with relation to how it uses VL.
823static bool isSupportedInstr(const MachineInstr &MI) {
824 const RISCVVPseudosTable::PseudoInfo *RVV =
825 RISCVVPseudosTable::getPseudoInfo(MI.getOpcode());
826
827 if (!RVV)
828 return false;
829
830 switch (RVV->BaseInstr) {
831 // Vector Unit-Stride Instructions
832 // Vector Strided Instructions
833 case RISCV::VLM_V:
834 case RISCV::VLE8_V:
835 case RISCV::VLSE8_V:
836 case RISCV::VLE16_V:
837 case RISCV::VLSE16_V:
838 case RISCV::VLE32_V:
839 case RISCV::VLSE32_V:
840 case RISCV::VLE64_V:
841 case RISCV::VLSE64_V:
842 // Vector Indexed Instructions
843 case RISCV::VLUXEI8_V:
844 case RISCV::VLOXEI8_V:
845 case RISCV::VLUXEI16_V:
846 case RISCV::VLOXEI16_V:
847 case RISCV::VLUXEI32_V:
848 case RISCV::VLOXEI32_V:
849 case RISCV::VLUXEI64_V:
850 case RISCV::VLOXEI64_V:
851 // Vector Single-Width Integer Add and Subtract
852 case RISCV::VADD_VI:
853 case RISCV::VADD_VV:
854 case RISCV::VADD_VX:
855 case RISCV::VSUB_VV:
856 case RISCV::VSUB_VX:
857 case RISCV::VRSUB_VI:
858 case RISCV::VRSUB_VX:
859 // Vector Bitwise Logical Instructions
860 // Vector Single-Width Shift Instructions
861 case RISCV::VAND_VI:
862 case RISCV::VAND_VV:
863 case RISCV::VAND_VX:
864 case RISCV::VOR_VI:
865 case RISCV::VOR_VV:
866 case RISCV::VOR_VX:
867 case RISCV::VXOR_VI:
868 case RISCV::VXOR_VV:
869 case RISCV::VXOR_VX:
870 case RISCV::VSLL_VI:
871 case RISCV::VSLL_VV:
872 case RISCV::VSLL_VX:
873 case RISCV::VSRL_VI:
874 case RISCV::VSRL_VV:
875 case RISCV::VSRL_VX:
876 case RISCV::VSRA_VI:
877 case RISCV::VSRA_VV:
878 case RISCV::VSRA_VX:
879 // Vector Widening Integer Add/Subtract
880 case RISCV::VWADDU_VV:
881 case RISCV::VWADDU_VX:
882 case RISCV::VWSUBU_VV:
883 case RISCV::VWSUBU_VX:
884 case RISCV::VWADD_VV:
885 case RISCV::VWADD_VX:
886 case RISCV::VWSUB_VV:
887 case RISCV::VWSUB_VX:
888 case RISCV::VWADDU_WV:
889 case RISCV::VWADDU_WX:
890 case RISCV::VWSUBU_WV:
891 case RISCV::VWSUBU_WX:
892 case RISCV::VWADD_WV:
893 case RISCV::VWADD_WX:
894 case RISCV::VWSUB_WV:
895 case RISCV::VWSUB_WX:
896 // Vector Integer Extension
897 case RISCV::VZEXT_VF2:
898 case RISCV::VSEXT_VF2:
899 case RISCV::VZEXT_VF4:
900 case RISCV::VSEXT_VF4:
901 case RISCV::VZEXT_VF8:
902 case RISCV::VSEXT_VF8:
903 // Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
904 // FIXME: Add support
905 case RISCV::VMADC_VV:
906 case RISCV::VMADC_VI:
907 case RISCV::VMADC_VX:
908 case RISCV::VMSBC_VV:
909 case RISCV::VMSBC_VX:
910 // Vector Narrowing Integer Right Shift Instructions
911 case RISCV::VNSRL_WX:
912 case RISCV::VNSRL_WI:
913 case RISCV::VNSRL_WV:
914 case RISCV::VNSRA_WI:
915 case RISCV::VNSRA_WV:
916 case RISCV::VNSRA_WX:
917 // Vector Integer Compare Instructions
918 case RISCV::VMSEQ_VI:
919 case RISCV::VMSEQ_VV:
920 case RISCV::VMSEQ_VX:
921 case RISCV::VMSNE_VI:
922 case RISCV::VMSNE_VV:
923 case RISCV::VMSNE_VX:
924 case RISCV::VMSLTU_VV:
925 case RISCV::VMSLTU_VX:
926 case RISCV::VMSLT_VV:
927 case RISCV::VMSLT_VX:
928 case RISCV::VMSLEU_VV:
929 case RISCV::VMSLEU_VI:
930 case RISCV::VMSLEU_VX:
931 case RISCV::VMSLE_VV:
932 case RISCV::VMSLE_VI:
933 case RISCV::VMSLE_VX:
934 case RISCV::VMSGTU_VI:
935 case RISCV::VMSGTU_VX:
936 case RISCV::VMSGT_VI:
937 case RISCV::VMSGT_VX:
938 // Vector Integer Min/Max Instructions
939 case RISCV::VMINU_VV:
940 case RISCV::VMINU_VX:
941 case RISCV::VMIN_VV:
942 case RISCV::VMIN_VX:
943 case RISCV::VMAXU_VV:
944 case RISCV::VMAXU_VX:
945 case RISCV::VMAX_VV:
946 case RISCV::VMAX_VX:
947 // Vector Single-Width Integer Multiply Instructions
948 case RISCV::VMUL_VV:
949 case RISCV::VMUL_VX:
950 case RISCV::VMULH_VV:
951 case RISCV::VMULH_VX:
952 case RISCV::VMULHU_VV:
953 case RISCV::VMULHU_VX:
954 case RISCV::VMULHSU_VV:
955 case RISCV::VMULHSU_VX:
956 // Vector Integer Divide Instructions
957 case RISCV::VDIVU_VV:
958 case RISCV::VDIVU_VX:
959 case RISCV::VDIV_VV:
960 case RISCV::VDIV_VX:
961 case RISCV::VREMU_VV:
962 case RISCV::VREMU_VX:
963 case RISCV::VREM_VV:
964 case RISCV::VREM_VX:
965 // Vector Widening Integer Multiply Instructions
966 case RISCV::VWMUL_VV:
967 case RISCV::VWMUL_VX:
968 case RISCV::VWMULSU_VV:
969 case RISCV::VWMULSU_VX:
970 case RISCV::VWMULU_VV:
971 case RISCV::VWMULU_VX:
972 // Vector Single-Width Integer Multiply-Add Instructions
973 case RISCV::VMACC_VV:
974 case RISCV::VMACC_VX:
975 case RISCV::VNMSAC_VV:
976 case RISCV::VNMSAC_VX:
977 case RISCV::VMADD_VV:
978 case RISCV::VMADD_VX:
979 case RISCV::VNMSUB_VV:
980 case RISCV::VNMSUB_VX:
981 // Vector Integer Merge Instructions
982 case RISCV::VMERGE_VIM:
983 case RISCV::VMERGE_VVM:
984 case RISCV::VMERGE_VXM:
985 // Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
986 case RISCV::VADC_VIM:
987 case RISCV::VADC_VVM:
988 case RISCV::VADC_VXM:
989 case RISCV::VMADC_VIM:
990 case RISCV::VMADC_VVM:
991 case RISCV::VMADC_VXM:
992 case RISCV::VSBC_VVM:
993 case RISCV::VSBC_VXM:
994 case RISCV::VMSBC_VVM:
995 case RISCV::VMSBC_VXM:
996 // Vector Widening Integer Multiply-Add Instructions
997 case RISCV::VWMACCU_VV:
998 case RISCV::VWMACCU_VX:
999 case RISCV::VWMACC_VV:
1000 case RISCV::VWMACC_VX:
1001 case RISCV::VWMACCSU_VV:
1002 case RISCV::VWMACCSU_VX:
1003 case RISCV::VWMACCUS_VX:
1004 // Vector Integer Merge Instructions
1005 // FIXME: Add support
1006 // Vector Integer Move Instructions
1007 // FIXME: Add support
1008 case RISCV::VMV_V_I:
1009 case RISCV::VMV_V_X:
1010 case RISCV::VMV_V_V:
1011 // Vector Single-Width Saturating Add and Subtract
1012 case RISCV::VSADDU_VV:
1013 case RISCV::VSADDU_VX:
1014 case RISCV::VSADDU_VI:
1015 case RISCV::VSADD_VV:
1016 case RISCV::VSADD_VX:
1017 case RISCV::VSADD_VI:
1018 case RISCV::VSSUBU_VV:
1019 case RISCV::VSSUBU_VX:
1020 case RISCV::VSSUB_VV:
1021 case RISCV::VSSUB_VX:
1022 // Vector Single-Width Averaging Add and Subtract
1023 case RISCV::VAADDU_VV:
1024 case RISCV::VAADDU_VX:
1025 case RISCV::VAADD_VV:
1026 case RISCV::VAADD_VX:
1027 case RISCV::VASUBU_VV:
1028 case RISCV::VASUBU_VX:
1029 case RISCV::VASUB_VV:
1030 case RISCV::VASUB_VX:
1031 // Vector Single-Width Fractional Multiply with Rounding and Saturation
1032 case RISCV::VSMUL_VV:
1033 case RISCV::VSMUL_VX:
1034 // Vector Single-Width Scaling Shift Instructions
1035 case RISCV::VSSRL_VV:
1036 case RISCV::VSSRL_VX:
1037 case RISCV::VSSRL_VI:
1038 case RISCV::VSSRA_VV:
1039 case RISCV::VSSRA_VX:
1040 case RISCV::VSSRA_VI:
1041 // Vector Narrowing Fixed-Point Clip Instructions
1042 case RISCV::VNCLIPU_WV:
1043 case RISCV::VNCLIPU_WX:
1044 case RISCV::VNCLIPU_WI:
1045 case RISCV::VNCLIP_WV:
1046 case RISCV::VNCLIP_WX:
1047 case RISCV::VNCLIP_WI:
1048 // Vector Bit-manipulation Instructions (Zvbb)
1049 // Vector And-Not
1050 case RISCV::VANDN_VV:
1051 case RISCV::VANDN_VX:
1052 // Vector Reverse Bits in Elements
1053 case RISCV::VBREV_V:
1054 // Vector Reverse Bits in Bytes
1055 case RISCV::VBREV8_V:
1056 // Vector Reverse Bytes
1057 case RISCV::VREV8_V:
1058 // Vector Count Leading Zeros
1059 case RISCV::VCLZ_V:
1060 // Vector Count Trailing Zeros
1061 case RISCV::VCTZ_V:
1062 // Vector Population Count
1063 case RISCV::VCPOP_V:
1064 // Vector Rotate Left
1065 case RISCV::VROL_VV:
1066 case RISCV::VROL_VX:
1067 // Vector Rotate Right
1068 case RISCV::VROR_VI:
1069 case RISCV::VROR_VV:
1070 case RISCV::VROR_VX:
1071 // Vector Widening Shift Left Logical
1072 case RISCV::VWSLL_VI:
1073 case RISCV::VWSLL_VX:
1074 case RISCV::VWSLL_VV:
1075 // Vector Carry-less Multiplication Instructions (Zvbc)
1076 // Vector Carry-less Multiply
1077 case RISCV::VCLMUL_VV:
1078 case RISCV::VCLMUL_VX:
1079 // Vector Carry-less Multiply Return High Half
1080 case RISCV::VCLMULH_VV:
1081 case RISCV::VCLMULH_VX:
1082 // Vector Mask Instructions
1083 // Vector Mask-Register Logical Instructions
1084 // vmsbf.m set-before-first mask bit
1085 // vmsif.m set-including-first mask bit
1086 // vmsof.m set-only-first mask bit
1087 // Vector Iota Instruction
1088 // Vector Element Index Instruction
1089 case RISCV::VMAND_MM:
1090 case RISCV::VMNAND_MM:
1091 case RISCV::VMANDN_MM:
1092 case RISCV::VMXOR_MM:
1093 case RISCV::VMOR_MM:
1094 case RISCV::VMNOR_MM:
1095 case RISCV::VMORN_MM:
1096 case RISCV::VMXNOR_MM:
1097 case RISCV::VMSBF_M:
1098 case RISCV::VMSIF_M:
1099 case RISCV::VMSOF_M:
1100 case RISCV::VIOTA_M:
1101 case RISCV::VID_V:
1102 // Vector Slide Instructions
1103 case RISCV::VSLIDEUP_VX:
1104 case RISCV::VSLIDEUP_VI:
1105 case RISCV::VSLIDEDOWN_VX:
1106 case RISCV::VSLIDEDOWN_VI:
1107 case RISCV::VSLIDE1UP_VX:
1108 case RISCV::VFSLIDE1UP_VF:
1109 // Vector Register Gather Instructions
1110 case RISCV::VRGATHER_VI:
1111 case RISCV::VRGATHER_VV:
1112 case RISCV::VRGATHER_VX:
1113 case RISCV::VRGATHEREI16_VV:
1114 // Vector Single-Width Floating-Point Add/Subtract Instructions
1115 case RISCV::VFADD_VF:
1116 case RISCV::VFADD_VV:
1117 case RISCV::VFSUB_VF:
1118 case RISCV::VFSUB_VV:
1119 case RISCV::VFRSUB_VF:
1120 // Vector Widening Floating-Point Add/Subtract Instructions
1121 case RISCV::VFWADD_VV:
1122 case RISCV::VFWADD_VF:
1123 case RISCV::VFWSUB_VV:
1124 case RISCV::VFWSUB_VF:
1125 case RISCV::VFWADD_WF:
1126 case RISCV::VFWADD_WV:
1127 case RISCV::VFWSUB_WF:
1128 case RISCV::VFWSUB_WV:
1129 // Vector Single-Width Floating-Point Multiply/Divide Instructions
1130 case RISCV::VFMUL_VF:
1131 case RISCV::VFMUL_VV:
1132 case RISCV::VFDIV_VF:
1133 case RISCV::VFDIV_VV:
1134 case RISCV::VFRDIV_VF:
1135 // Vector Widening Floating-Point Multiply
1136 case RISCV::VFWMUL_VF:
1137 case RISCV::VFWMUL_VV:
1138 // Vector Single-Width Floating-Point Fused Multiply-Add Instructions
1139 case RISCV::VFMACC_VV:
1140 case RISCV::VFMACC_VF:
1141 case RISCV::VFNMACC_VV:
1142 case RISCV::VFNMACC_VF:
1143 case RISCV::VFMSAC_VV:
1144 case RISCV::VFMSAC_VF:
1145 case RISCV::VFNMSAC_VV:
1146 case RISCV::VFNMSAC_VF:
1147 case RISCV::VFMADD_VV:
1148 case RISCV::VFMADD_VF:
1149 case RISCV::VFNMADD_VV:
1150 case RISCV::VFNMADD_VF:
1151 case RISCV::VFMSUB_VV:
1152 case RISCV::VFMSUB_VF:
1153 case RISCV::VFNMSUB_VV:
1154 case RISCV::VFNMSUB_VF:
1155 // Vector Widening Floating-Point Fused Multiply-Add Instructions
1156 case RISCV::VFWMACC_VV:
1157 case RISCV::VFWMACC_VF:
1158 case RISCV::VFWNMACC_VV:
1159 case RISCV::VFWNMACC_VF:
1160 case RISCV::VFWMSAC_VV:
1161 case RISCV::VFWMSAC_VF:
1162 case RISCV::VFWNMSAC_VV:
1163 case RISCV::VFWNMSAC_VF:
1164 case RISCV::VFWMACCBF16_VV:
1165 case RISCV::VFWMACCBF16_VF:
1166 // Vector Floating-Point Square-Root Instruction
1167 case RISCV::VFSQRT_V:
1168 // Vector Floating-Point Reciprocal Square-Root Estimate Instruction
1169 case RISCV::VFRSQRT7_V:
1170 // Vector Floating-Point Reciprocal Estimate Instruction
1171 case RISCV::VFREC7_V:
1172 // Vector Floating-Point MIN/MAX Instructions
1173 case RISCV::VFMIN_VF:
1174 case RISCV::VFMIN_VV:
1175 case RISCV::VFMAX_VF:
1176 case RISCV::VFMAX_VV:
1177 // Vector Floating-Point Sign-Injection Instructions
1178 case RISCV::VFSGNJ_VF:
1179 case RISCV::VFSGNJ_VV:
1180 case RISCV::VFSGNJN_VV:
1181 case RISCV::VFSGNJN_VF:
1182 case RISCV::VFSGNJX_VF:
1183 case RISCV::VFSGNJX_VV:
1184 // Vector Floating-Point Compare Instructions
1185 case RISCV::VMFEQ_VF:
1186 case RISCV::VMFEQ_VV:
1187 case RISCV::VMFNE_VF:
1188 case RISCV::VMFNE_VV:
1189 case RISCV::VMFLT_VF:
1190 case RISCV::VMFLT_VV:
1191 case RISCV::VMFLE_VF:
1192 case RISCV::VMFLE_VV:
1193 case RISCV::VMFGT_VF:
1194 case RISCV::VMFGE_VF:
1195 // Vector Floating-Point Classify Instruction
1196 case RISCV::VFCLASS_V:
1197 // Vector Floating-Point Merge Instruction
1198 case RISCV::VFMERGE_VFM:
1199 // Vector Floating-Point Move Instruction
1200 case RISCV::VFMV_V_F:
1201 // Single-Width Floating-Point/Integer Type-Convert Instructions
1202 case RISCV::VFCVT_XU_F_V:
1203 case RISCV::VFCVT_X_F_V:
1204 case RISCV::VFCVT_RTZ_XU_F_V:
1205 case RISCV::VFCVT_RTZ_X_F_V:
1206 case RISCV::VFCVT_F_XU_V:
1207 case RISCV::VFCVT_F_X_V:
1208 // Widening Floating-Point/Integer Type-Convert Instructions
1209 case RISCV::VFWCVT_XU_F_V:
1210 case RISCV::VFWCVT_X_F_V:
1211 case RISCV::VFWCVT_RTZ_XU_F_V:
1212 case RISCV::VFWCVT_RTZ_X_F_V:
1213 case RISCV::VFWCVT_F_XU_V:
1214 case RISCV::VFWCVT_F_X_V:
1215 case RISCV::VFWCVT_F_F_V:
1216 case RISCV::VFWCVTBF16_F_F_V:
1217 // Narrowing Floating-Point/Integer Type-Convert Instructions
1218 case RISCV::VFNCVT_XU_F_W:
1219 case RISCV::VFNCVT_X_F_W:
1220 case RISCV::VFNCVT_RTZ_XU_F_W:
1221 case RISCV::VFNCVT_RTZ_X_F_W:
1222 case RISCV::VFNCVT_F_XU_W:
1223 case RISCV::VFNCVT_F_X_W:
1224 case RISCV::VFNCVT_F_F_W:
1225 case RISCV::VFNCVT_ROD_F_F_W:
1226 case RISCV::VFNCVTBF16_F_F_W:
1227 return true;
1228 }
1229
1230 return false;
1231}
1232
1233/// Return true if MO is a vector operand but is used as a scalar operand.
1234static bool isVectorOpUsedAsScalarOp(const MachineOperand &MO) {
1235 const MachineInstr *MI = MO.getParent();
1236 const RISCVVPseudosTable::PseudoInfo *RVV =
1237 RISCVVPseudosTable::getPseudoInfo(MI->getOpcode());
1238
1239 if (!RVV)
1240 return false;
1241
1242 switch (RVV->BaseInstr) {
1243 // Reductions only use vs1[0] of vs1
1244 case RISCV::VREDAND_VS:
1245 case RISCV::VREDMAX_VS:
1246 case RISCV::VREDMAXU_VS:
1247 case RISCV::VREDMIN_VS:
1248 case RISCV::VREDMINU_VS:
1249 case RISCV::VREDOR_VS:
1250 case RISCV::VREDSUM_VS:
1251 case RISCV::VREDXOR_VS:
1252 case RISCV::VWREDSUM_VS:
1253 case RISCV::VWREDSUMU_VS:
1254 case RISCV::VFREDMAX_VS:
1255 case RISCV::VFREDMIN_VS:
1256 case RISCV::VFREDOSUM_VS:
1257 case RISCV::VFREDUSUM_VS:
1258 case RISCV::VFWREDOSUM_VS:
1259 case RISCV::VFWREDUSUM_VS:
1260 return MO.getOperandNo() == 3;
1261 case RISCV::VMV_X_S:
1262 case RISCV::VFMV_F_S:
1263 return MO.getOperandNo() == 1;
1264 default:
1265 return false;
1266 }
1267}
1268
1269bool RISCVVLOptimizer::isCandidate(const MachineInstr &MI) const {
1270 const MCInstrDesc &Desc = MI.getDesc();
1271 if (!RISCVII::hasVLOp(Desc.TSFlags) || !RISCVII::hasSEWOp(Desc.TSFlags))
1272 return false;
1273
1274 if (MI.getNumExplicitDefs() != 1)
1275 return false;
1276
1277 // Some instructions have implicit defs e.g. $vxsat. If they might be read
1278 // later then we can't reduce VL.
1279 if (!MI.allImplicitDefsAreDead()) {
1280 LLVM_DEBUG(dbgs() << "Not a candidate because has non-dead implicit def\n");
1281 return false;
1282 }
1283
1284 if (MI.mayRaiseFPException()) {
1285 LLVM_DEBUG(dbgs() << "Not a candidate because may raise FP exception\n");
1286 return false;
1287 }
1288
1289 for (const MachineMemOperand *MMO : MI.memoperands()) {
1290 if (MMO->isVolatile()) {
1291 LLVM_DEBUG(dbgs() << "Not a candidate because contains volatile MMO\n");
1292 return false;
1293 }
1294 }
1295
1296 // Some instructions that produce vectors have semantics that make it more
1297 // difficult to determine whether the VL can be reduced. For example, some
1298 // instructions, such as reductions, may write lanes past VL to a scalar
1299 // register. Other instructions, such as some loads or stores, may write
1300 // lower lanes using data from higher lanes. There may be other complex
1301 // semantics not mentioned here that make it hard to determine whether
1302 // the VL can be optimized. As a result, a white-list of supported
1303 // instructions is used. Over time, more instructions can be supported
1304 // upon careful examination of their semantics under the logic in this
1305 // optimization.
1306 // TODO: Use a better approach than a white-list, such as adding
1307 // properties to instructions using something like TSFlags.
1308 if (!isSupportedInstr(MI)) {
1309 LLVM_DEBUG(dbgs() << "Not a candidate due to unsupported instruction: "
1310 << MI);
1311 return false;
1312 }
1313
1314 assert(!RISCVII::elementsDependOnVL(
1315 TII->get(RISCV::getRVVMCOpcode(MI.getOpcode())).TSFlags) &&
1316 "Instruction shouldn't be supported if elements depend on VL");
1317
1318 assert(RISCVRI::isVRegClass(
1319 MRI->getRegClass(MI.getOperand(0).getReg())->TSFlags) &&
1320 "All supported instructions produce a vector register result");
1321
1322 LLVM_DEBUG(dbgs() << "Found a candidate for VL reduction: " << MI << "\n");
1323 return true;
1324}
1325
1326std::optional<MachineOperand>
1327RISCVVLOptimizer::getMinimumVLForUser(const MachineOperand &UserOp) const {
1328 const MachineInstr &UserMI = *UserOp.getParent();
1329 const MCInstrDesc &Desc = UserMI.getDesc();
1330
1331 if (!RISCVII::hasVLOp(Desc.TSFlags) || !RISCVII::hasSEWOp(Desc.TSFlags)) {
1332 LLVM_DEBUG(dbgs() << " Abort due to lack of VL, assume that"
1333 " use VLMAX\n");
1334 return std::nullopt;
1335 }
1336
1337 if (RISCVII::readsPastVL(
1338 TII->get(RISCV::getRVVMCOpcode(UserMI.getOpcode())).TSFlags)) {
1339 LLVM_DEBUG(dbgs() << " Abort because used by unsafe instruction\n");
1340 return std::nullopt;
1341 }
1342
1343 unsigned VLOpNum = RISCVII::getVLOpNum(Desc);
1344 const MachineOperand &VLOp = UserMI.getOperand(VLOpNum);
1345 // Looking for an immediate or a register VL that isn't X0.
1346 assert((!VLOp.isReg() || VLOp.getReg() != RISCV::X0) &&
1347 "Did not expect X0 VL");
1348
1349 // If the user is a passthru it will read the elements past VL, so
1350 // abort if any of the elements past VL are demanded.
1351 if (UserOp.isTied()) {
1352 assert(UserOp.getOperandNo() == UserMI.getNumExplicitDefs() &&
1353 RISCVII::isFirstDefTiedToFirstUse(UserMI.getDesc()));
1354 auto DemandedVL = DemandedVLs.lookup(&UserMI);
1355 if (!DemandedVL || !RISCV::isVLKnownLE(*DemandedVL, VLOp)) {
1356 LLVM_DEBUG(dbgs() << " Abort because user is passthru in "
1357 "instruction with demanded tail\n");
1358 return std::nullopt;
1359 }
1360 }
1361
1362 // Instructions like reductions may use a vector register as a scalar
1363 // register. In this case, we should treat it as only reading the first lane.
1364 if (isVectorOpUsedAsScalarOp(UserOp)) {
1365 LLVM_DEBUG(dbgs() << " Used this operand as a scalar operand\n");
1366 return MachineOperand::CreateImm(1);
1367 }
1368
1369 // If we know the demanded VL of UserMI, then we can reduce the VL it
1370 // requires.
1371 if (auto DemandedVL = DemandedVLs.lookup(&UserMI)) {
1372 assert(isCandidate(UserMI));
1373 if (RISCV::isVLKnownLE(*DemandedVL, VLOp))
1374 return DemandedVL;
1375 }
1376
1377 return VLOp;
1378}
1379
1380std::optional<MachineOperand>
1381RISCVVLOptimizer::checkUsers(const MachineInstr &MI) const {
1382 std::optional<MachineOperand> CommonVL;
1383 SmallSetVector<MachineOperand *, 8> Worklist;
1384 SmallPtrSet<const MachineInstr *, 4> PHISeen;
1385 for (auto &UserOp : MRI->use_operands(MI.getOperand(0).getReg()))
1386 Worklist.insert(&UserOp);
1387
1388 while (!Worklist.empty()) {
1389 MachineOperand &UserOp = *Worklist.pop_back_val();
1390 const MachineInstr &UserMI = *UserOp.getParent();
1391 LLVM_DEBUG(dbgs() << " Checking user: " << UserMI << "\n");
1392
1393 if (UserMI.isFullCopy() && UserMI.getOperand(0).getReg().isVirtual()) {
1394 LLVM_DEBUG(dbgs() << " Peeking through uses of COPY\n");
1395 Worklist.insert_range(llvm::make_pointer_range(
1396 MRI->use_operands(UserMI.getOperand(0).getReg())));
1397 continue;
1398 }
1399
1400 if (UserMI.isPHI()) {
1401 // Don't follow PHI cycles
1402 if (!PHISeen.insert(&UserMI).second)
1403 continue;
1404 LLVM_DEBUG(dbgs() << " Peeking through uses of PHI\n");
1405 Worklist.insert_range(llvm::make_pointer_range(
1406 MRI->use_operands(UserMI.getOperand(0).getReg())));
1407 continue;
1408 }
1409
1410 auto VLOp = getMinimumVLForUser(UserOp);
1411 if (!VLOp)
1412 return std::nullopt;
1413
1414 // Use the largest VL among all the users. If we cannot determine this
1415 // statically, then we cannot optimize the VL.
1416 if (!CommonVL || RISCV::isVLKnownLE(*CommonVL, *VLOp)) {
1417 CommonVL = *VLOp;
1418 LLVM_DEBUG(dbgs() << " User VL is: " << VLOp << "\n");
1419 } else if (!RISCV::isVLKnownLE(*VLOp, *CommonVL)) {
1420 LLVM_DEBUG(dbgs() << " Abort because cannot determine a common VL\n");
1421 return std::nullopt;
1422 }
1423
1424 if (!RISCVII::hasSEWOp(UserMI.getDesc().TSFlags)) {
1425 LLVM_DEBUG(dbgs() << " Abort due to lack of SEW operand\n");
1426 return std::nullopt;
1427 }
1428
1429 std::optional<OperandInfo> ConsumerInfo = getOperandInfo(UserOp, MRI);
1430 std::optional<OperandInfo> ProducerInfo =
1431 getOperandInfo(MI.getOperand(0), MRI);
1432 if (!ConsumerInfo || !ProducerInfo) {
1433 LLVM_DEBUG(dbgs() << " Abort due to unknown operand information.\n");
1434 LLVM_DEBUG(dbgs() << " ConsumerInfo is: " << ConsumerInfo << "\n");
1435 LLVM_DEBUG(dbgs() << " ProducerInfo is: " << ProducerInfo << "\n");
1436 return std::nullopt;
1437 }
1438
1439 if (!OperandInfo::areCompatible(*ProducerInfo, *ConsumerInfo)) {
1440 LLVM_DEBUG(
1441 dbgs()
1442 << " Abort due to incompatible information for EMUL or EEW.\n");
1443 LLVM_DEBUG(dbgs() << " ConsumerInfo is: " << ConsumerInfo << "\n");
1444 LLVM_DEBUG(dbgs() << " ProducerInfo is: " << ProducerInfo << "\n");
1445 return std::nullopt;
1446 }
1447 }
1448
1449 return CommonVL;
1450}
1451
1452bool RISCVVLOptimizer::tryReduceVL(MachineInstr &MI) const {
1453 LLVM_DEBUG(dbgs() << "Trying to reduce VL for " << MI);
1454
1455 unsigned VLOpNum = RISCVII::getVLOpNum(MI.getDesc());
1456 MachineOperand &VLOp = MI.getOperand(VLOpNum);
1457
1458 // If the VL is 1, then there is no need to reduce it. This is an
1459 // optimization, not needed to preserve correctness.
1460 if (VLOp.isImm() && VLOp.getImm() == 1) {
1461 LLVM_DEBUG(dbgs() << " Abort due to VL == 1, no point in reducing.\n");
1462 return false;
1463 }
1464
1465 auto CommonVL = DemandedVLs.lookup(&MI);
1466 if (!CommonVL)
1467 return false;
1468
1469 assert((CommonVL->isImm() || CommonVL->getReg().isVirtual()) &&
1470 "Expected VL to be an Imm or virtual Reg");
1471
1472 if (!RISCV::isVLKnownLE(*CommonVL, VLOp)) {
1473 LLVM_DEBUG(dbgs() << " Abort due to CommonVL not <= VLOp.\n");
1474 return false;
1475 }
1476
1477 if (CommonVL->isIdenticalTo(VLOp)) {
1478 LLVM_DEBUG(
1479 dbgs() << " Abort due to CommonVL == VLOp, no point in reducing.\n");
1480 return false;
1481 }
1482
1483 if (CommonVL->isImm()) {
1484 LLVM_DEBUG(dbgs() << " Reduce VL from " << VLOp << " to "
1485 << CommonVL->getImm() << " for " << MI << "\n");
1486 VLOp.ChangeToImmediate(CommonVL->getImm());
1487 return true;
1488 }
1489 const MachineInstr *VLMI = MRI->getVRegDef(CommonVL->getReg());
1490 if (!MDT->dominates(VLMI, &MI)) {
1491 LLVM_DEBUG(dbgs() << " Abort due to VL not dominating.\n");
1492 return false;
1493 }
1494 LLVM_DEBUG(
1495 dbgs() << " Reduce VL from " << VLOp << " to "
1496 << printReg(CommonVL->getReg(), MRI->getTargetRegisterInfo())
1497 << " for " << MI << "\n");
1498
1499 // All our checks passed. We can reduce VL.
1500 VLOp.ChangeToRegister(CommonVL->getReg(), false);
1501 return true;
1502}
1503
1504bool RISCVVLOptimizer::runOnMachineFunction(MachineFunction &MF) {
1505 if (skipFunction(MF.getFunction()))
1506 return false;
1507
1508 MRI = &MF.getRegInfo();
1509 MDT = &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
1510
1511 const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>();
1512 if (!ST.hasVInstructions())
1513 return false;
1514
1515 TII = ST.getInstrInfo();
1516
1517 assert(DemandedVLs.empty());
1518
1519 // For each instruction that defines a vector, compute what VL its
1520 // downstream users demand.
1521 for (MachineBasicBlock *MBB : post_order(&MF)) {
1522 assert(MDT->isReachableFromEntry(MBB));
1523 for (MachineInstr &MI : reverse(*MBB)) {
1524 if (!isCandidate(MI))
1525 continue;
1526 DemandedVLs.insert({&MI, checkUsers(MI)});
1527 }
1528 }
1529
1530 // Then go through and see if we can reduce the VL of any instructions to
1531 // only what's demanded.
1532 bool MadeChange = false;
1533 for (MachineBasicBlock &MBB : MF) {
1534 // Avoid unreachable blocks as they have degenerate dominance
1535 if (!MDT->isReachableFromEntry(&MBB))
1536 continue;
1537
1538 for (auto &MI : reverse(MBB)) {
1539 if (!isCandidate(MI))
1540 continue;
1541 if (!tryReduceVL(MI))
1542 continue;
1543 MadeChange = true;
1544 }
1545 }
1546
1547 DemandedVLs.clear();
1548 return MadeChange;
1549}
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:103
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
MBB
MachineBasicBlock & MBB
Definition: ARMSLSHardening.cpp:71
print
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
Definition: ArchiveWriter.cpp:205
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
LLVM_ATTRIBUTE_UNUSED
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:298
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:118
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:110
isCandidate
static bool isCandidate(const MachineInstr *MI, Register &DefedReg, Register FrameReg)
Definition: MachineLateInstrsCleanup.cpp:179
INITIALIZE_PASS_DEPENDENCY
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:42
INITIALIZE_PASS_END
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:44
INITIALIZE_PASS_BEGIN
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:39
PostOrderIterator.h
This file builds on the ADT/GraphTraits.h file to build a generic graph post order iterator.
operator<<
static LLVM_ATTRIBUTE_UNUSED raw_ostream & operator<<(raw_ostream &OS, const OperandInfo &OI)
Definition: RISCVVLOptimizer.cpp:121
getIntegerExtensionOperandEEW
static unsigned getIntegerExtensionOperandEEW(unsigned Factor, const MachineInstr &MI, const MachineOperand &MO)
Dest has EEW=SEW.
Definition: RISCVVLOptimizer.cpp:165
getOperandLog2EEW
static std::optional< unsigned > getOperandLog2EEW(const MachineOperand &MO, const MachineRegisterInfo *MRI)
Definition: RISCVVLOptimizer.cpp:182
isVectorOpUsedAsScalarOp
static bool isVectorOpUsedAsScalarOp(const MachineOperand &MO)
Return true if MO is a vector operand but is used as a scalar operand.
Definition: RISCVVLOptimizer.cpp:1234
getEMULEqualsEEWDivSEWTimesLMUL
static std::pair< unsigned, bool > getEMULEqualsEEWDivSEWTimesLMUL(unsigned Log2EEW, const MachineInstr &MI)
Return EMUL = (EEW / SEW) * LMUL where EEW comes from Log2EEW and LMUL and SEW are from the TSFlags o...
Definition: RISCVVLOptimizer.cpp:139
isSupportedInstr
static bool isSupportedInstr(const MachineInstr &MI)
Return true if this optimization should consider MI for VL reduction.
Definition: RISCVVLOptimizer.cpp:823
PASS_NAME
#define PASS_NAME
Definition: RISCVVLOptimizer.cpp:29
DEBUG_TYPE
#define DEBUG_TYPE
Definition: RISCVVLOptimizer.cpp:28
getOperandInfo
static std::optional< OperandInfo > getOperandInfo(const MachineOperand &MO, const MachineRegisterInfo *MRI)
Definition: RISCVVLOptimizer.cpp:782
OS
raw_pwrite_stream & OS
Definition: SampleProfWriter.cpp:51
LLVM_DEBUG
#define LLVM_DEBUG(...)
Definition: Debug.h:119
PASS_NAME
#define PASS_NAME
Definition: TypePromotion.cpp:43
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:48
llvm::AnalysisUsage::addRequired
AnalysisUsage & addRequired()
Definition: PassAnalysisSupport.h:76
llvm::AnalysisUsage::setPreservesCFG
LLVM_ABI void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:270
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:314
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:199
llvm::MCOperandInfo
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:86
llvm::MachineDominatorTreeWrapperPass
Analysis pass which computes a MachineDominatorTree.
Definition: MachineDominators.h:127
llvm::MachineDominatorTree
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Definition: MachineDominators.h:71
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:31
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:184
llvm::MachineFunctionPass::runOnMachineFunction
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:762
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:772
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:733
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:72
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:587
llvm::MachineInstr::isFullCopy
bool isFullCopy() const
Definition: MachineInstr.h:1435
llvm::MachineInstr::getDesc
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:584
llvm::MachineInstr::getNumExplicitDefs
LLVM_ABI unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
Definition: MachineInstr.cpp:839
llvm::MachineInstr::isPHI
bool isPHI() const
Definition: MachineInstr.h:1397
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:595
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:130
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::MachineOperand::getOperandNo
LLVM_ABI unsigned getOperandNo() const
Returns the index of this operand in the instruction that it belongs to.
Definition: MachineOperand.cpp:55
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:556
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:328
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:330
llvm::MachineOperand::ChangeToImmediate
LLVM_ABI void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
Definition: MachineOperand.cpp:161
llvm::MachineOperand::ChangeToRegister
LLVM_ABI void ChangeToRegister(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value.
Definition: MachineOperand.cpp:272
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:243
llvm::MachineOperand::CreateImm
static MachineOperand CreateImm(int64_t Val)
Definition: MachineOperand.h:821
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:368
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:53
llvm::Pass::getPassName
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Definition: Pass.cpp:85
llvm::Register::isVirtual
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:74
llvm::SetVector::insert_range
void insert_range(Range &&R)
Definition: SetVector.h:193
llvm::SetVector::empty
bool empty() const
Determine if the SetVector is empty or not.
Definition: SetVector.h:99
llvm::SetVector::insert
bool insert(const value_type &X)
Insert a new element into the SetVector.
Definition: SetVector.h:168
llvm::SetVector::pop_back_val
value_type pop_back_val()
Definition: SetVector.h:296
llvm::SmallPtrSetImpl::insert
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:401
llvm::SmallPtrSet
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:541
llvm::SmallSetVector
A SetVector that performs no allocations if smaller than a certain size.
Definition: SetVector.h:356
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:55
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:114
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:164
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MCOI::OPERAND_REGISTER
@ OPERAND_REGISTER
Definition: MCInstrDesc.h:62
llvm::RISCVII::readsPastVL
static bool readsPastVL(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:203
llvm::RISCVII::isTiedPseudo
static bool isTiedPseudo(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:157
llvm::RISCVII::getLMul
static RISCVVType::VLMUL getLMul(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:153
llvm::RISCVII::getVLOpNum
static unsigned getVLOpNum(const MCInstrDesc &Desc)
Definition: RISCVBaseInfo.h:207
llvm::RISCVII::hasVLOp
static bool hasVLOp(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:165
llvm::RISCVII::getSEWOpNum
static unsigned getSEWOpNum(const MCInstrDesc &Desc)
Definition: RISCVBaseInfo.h:225
llvm::RISCVII::elementsDependOnVL
static bool elementsDependOnVL(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:191
llvm::RISCVII::hasSEWOp
static bool hasSEWOp(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:161
llvm::RISCVII::isFirstDefTiedToFirstUse
static bool isFirstDefTiedToFirstUse(const MCInstrDesc &Desc)
Definition: RISCVBaseInfo.h:272
llvm::RISCVRI::isVRegClass
static bool isVRegClass(uint8_t TSFlags)
Definition: RISCVRegisterInfo.h:41
llvm::RISCVVType::decodeVLMUL
LLVM_ABI std::pair< unsigned, bool > decodeVLMUL(VLMUL VLMul)
Definition: RISCVTargetParser.cpp:186
llvm::RISCV::isVLKnownLE
bool isVLKnownLE(const MachineOperand &LHS, const MachineOperand &RHS)
Given two VL operands, do we know that LHS <= RHS?
Definition: RISCVInstrInfo.cpp:4800
llvm::RISCV::getRVVMCOpcode
unsigned getRVVMCOpcode(unsigned RVVPseudoOpcode)
Definition: RISCVInstrInfo.cpp:4779
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::createRISCVVLOptimizerPass
FunctionPass * createRISCVVLOptimizerPass()
Definition: RISCVVLOptimizer.cpp:116
llvm::post_order
iterator_range< po_iterator< T > > post_order(const T &G)
Definition: PostOrderIterator.h:197
llvm::Log2_32
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:336
llvm::reverse
auto reverse(ContainerTy &&C)
Definition: STLExtras.h:428
llvm::dbgs
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:207
llvm::make_pointer_range
iterator_range< pointer_iterator< WrappedIteratorT > > make_pointer_range(RangeT &&Range)
Definition: iterator.h:363
llvm::printReg
LLVM_ABI Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:107
llvm::DWARFExpression::Operation::Description
Description of the encoding of one expression Op.
Definition: DWARFExpression.h:67
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