LLVM 22.0.0git
AArch64Disassembler.cpp
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1//===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//
10//===----------------------------------------------------------------------===//
11
12#include "AArch64Disassembler.h"
13#include "AArch64ExternalSymbolizer.h"
14#include "MCTargetDesc/AArch64AddressingModes.h"
15#include "MCTargetDesc/AArch64MCTargetDesc.h"
16#include "TargetInfo/AArch64TargetInfo.h"
17#include "Utils/AArch64BaseInfo.h"
18#include "llvm/MC/MCDecoder.h"
19#include "llvm/MC/MCDecoderOps.h"
20#include "llvm/MC/MCDisassembler/MCRelocationInfo.h"
21#include "llvm/MC/MCInst.h"
22#include "llvm/MC/MCInstrDesc.h"
23#include "llvm/MC/MCRegisterInfo.h"
24#include "llvm/MC/MCSubtargetInfo.h"
25#include "llvm/MC/TargetRegistry.h"
26#include "llvm/Support/Compiler.h"
27#include "llvm/Support/Debug.h"
28#include <memory>
29
30using namespace llvm;
31using namespace llvm::MCD;
32
33#define DEBUG_TYPE "aarch64-disassembler"
34
35// Pull DecodeStatus and its enum values into the global namespace.
36using DecodeStatus = MCDisassembler::DecodeStatus;
37
38template <int Bits>
39static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address,
40 const MCDisassembler *Decoder);
41
42#define Success MCDisassembler::Success
43#define Fail MCDisassembler::Fail
44#define SoftFail MCDisassembler::SoftFail
45
46template <unsigned RegClassID, unsigned FirstReg, unsigned NumRegsInClass>
47static DecodeStatus DecodeSimpleRegisterClass(MCInst &Inst, unsigned RegNo,
48 uint64_t Address,
49 const MCDisassembler *Decoder) {
50 if (RegNo > NumRegsInClass - 1)
51 return Fail;
52
53 MCRegister Register =
54 AArch64MCRegisterClasses[RegClassID].getRegister(RegNo + FirstReg);
55 Inst.addOperand(MCOperand::createReg(Register));
56 return Success;
57}
58
59static DecodeStatus
60DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
61 const MCDisassembler *Decoder) {
62 if (RegNo > 22)
63 return Fail;
64 if (RegNo & 1)
65 return Fail;
66
67 MCRegister Register =
68 AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID].getRegister(
69 RegNo >> 1);
70 Inst.addOperand(MCOperand::createReg(Register));
71 return Success;
72}
73
74template <unsigned Min, unsigned Max>
75static DecodeStatus DecodeZPRMul2_MinMax(MCInst &Inst, unsigned RegNo,
76 uint64_t Address,
77 const MCDisassembler *Decoder) {
78 unsigned Reg = (RegNo * 2) + Min;
79 if (Reg < Min || Reg > Max || (Reg & 1))
80 return Fail;
81 MCRegister Register =
82 AArch64MCRegisterClasses[AArch64::ZPRRegClassID].getRegister(Reg);
83 Inst.addOperand(MCOperand::createReg(Register));
84 return Success;
85}
86
87template <unsigned Min, unsigned Max>
88static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
89 uint64_t Address,
90 const void *Decoder) {
91 unsigned Reg = (RegNo * 2) + Min;
92 if (Reg < Min || Reg > Max || (Reg & 1))
93 return Fail;
94
95 MCRegister Register =
96 AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(Reg);
97 Inst.addOperand(MCOperand::createReg(Register));
98 return Success;
99}
100
101static DecodeStatus DecodeZK(MCInst &Inst, unsigned RegNo, uint64_t Address,
102 const MCDisassembler *Decoder) {
103 if (RegNo > 7)
104 return Fail;
105
106 MCRegister Register =
107 AArch64MCRegisterClasses[AArch64::ZPR_KRegClassID].getRegister(RegNo);
108 Inst.addOperand(MCOperand::createReg(Register));
109 return Success;
110}
111
112static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo,
113 uint64_t Address,
114 const void *Decoder) {
115 if (RegNo * 4 > 28)
116 return Fail;
117 MCRegister Register =
118 AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo * 4);
119 Inst.addOperand(MCOperand::createReg(Register));
120 return Success;
121}
122
123static DecodeStatus
124DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask,
125 uint64_t Address,
126 const MCDisassembler *Decoder) {
127 if (RegMask > 0xFF)
128 return Fail;
129 Inst.addOperand(MCOperand::createImm(RegMask));
130 return Success;
131}
132
133static const MCPhysReg MatrixZATileDecoderTable[5][16] = {
134 {AArch64::ZAB0},
135 {AArch64::ZAH0, AArch64::ZAH1},
136 {AArch64::ZAS0, AArch64::ZAS1, AArch64::ZAS2, AArch64::ZAS3},
137 {AArch64::ZAD0, AArch64::ZAD1, AArch64::ZAD2, AArch64::ZAD3, AArch64::ZAD4,
138 AArch64::ZAD5, AArch64::ZAD6, AArch64::ZAD7},
139 {AArch64::ZAQ0, AArch64::ZAQ1, AArch64::ZAQ2, AArch64::ZAQ3, AArch64::ZAQ4,
140 AArch64::ZAQ5, AArch64::ZAQ6, AArch64::ZAQ7, AArch64::ZAQ8, AArch64::ZAQ9,
141 AArch64::ZAQ10, AArch64::ZAQ11, AArch64::ZAQ12, AArch64::ZAQ13,
142 AArch64::ZAQ14, AArch64::ZAQ15}};
143
144template <unsigned NumBitsForTile>
145static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
146 uint64_t Address,
147 const MCDisassembler *Decoder) {
148 unsigned LastReg = (1 << NumBitsForTile) - 1;
149 if (RegNo > LastReg)
150 return Fail;
151 Inst.addOperand(
152 MCOperand::createReg(MatrixZATileDecoderTable[NumBitsForTile][RegNo]));
153 return Success;
154}
155
156static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
157 uint64_t Address,
158 const void *Decoder) {
159 if ((RegNo * 2) > 14)
160 return Fail;
161 MCRegister Register =
162 AArch64MCRegisterClasses[AArch64::PPR2RegClassID].getRegister(RegNo * 2);
163 Inst.addOperand(MCOperand::createReg(Register));
164 return Success;
165}
166
167static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
168 uint64_t Addr,
169 const MCDisassembler *Decoder) {
170 // scale{5} is asserted as 1 in tblgen.
171 Imm |= 0x20;
172 Inst.addOperand(MCOperand::createImm(64 - Imm));
173 return Success;
174}
175
176static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
177 uint64_t Addr,
178 const MCDisassembler *Decoder) {
179 Inst.addOperand(MCOperand::createImm(64 - Imm));
180 return Success;
181}
182
183static DecodeStatus DecodePCRelLabel16(MCInst &Inst, unsigned Imm,
184 uint64_t Addr,
185 const MCDisassembler *Decoder) {
186 // Immediate is encoded as the top 16-bits of an unsigned 18-bit negative
187 // PC-relative offset.
188 uint64_t ImmVal = Imm;
189 if (ImmVal > (1 << 16))
190 return Fail;
191 ImmVal = -ImmVal;
192 if (!Decoder->tryAddingSymbolicOperand(Inst, (ImmVal << 2), Addr,
193 /*IsBranch=*/false, 0, 0, 4))
194 Inst.addOperand(MCOperand::createImm(ImmVal));
195 return Success;
196}
197
198static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
199 uint64_t Addr,
200 const MCDisassembler *Decoder) {
201 int64_t ImmVal = Imm;
202
203 // Sign-extend 19-bit immediate.
204 if (ImmVal & (1 << (19 - 1)))
205 ImmVal |= ~((1LL << 19) - 1);
206
207 if (!Decoder->tryAddingSymbolicOperand(
208 Inst, ImmVal * 4, Addr, Inst.getOpcode() != AArch64::LDRXl, 0, 0, 4))
209 Inst.addOperand(MCOperand::createImm(ImmVal));
210 return Success;
211}
212
213static DecodeStatus DecodePCRelLabel9(MCInst &Inst, unsigned Imm, uint64_t Addr,
214 const MCDisassembler *Decoder) {
215 int64_t ImmVal = Imm;
216
217 // Sign-extend 9-bit immediate.
218 if (ImmVal & (1 << (9 - 1)))
219 ImmVal |= ~((1LL << 9) - 1);
220
221 if (!Decoder->tryAddingSymbolicOperand(Inst, (ImmVal * 4), Addr,
222 /*IsBranch=*/true, 0, 0, 4))
223 Inst.addOperand(MCOperand::createImm(ImmVal));
224 return Success;
225}
226
227static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
228 uint64_t Address,
229 const MCDisassembler *Decoder) {
230 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1));
231 Inst.addOperand(MCOperand::createImm(Imm & 1));
232 return Success;
233}
234
235static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
236 uint64_t Address,
237 const MCDisassembler *Decoder) {
238 Inst.addOperand(MCOperand::createImm(Imm));
239
240 // Every system register in the encoding space is valid with the syntax
241 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds.
242 return Success;
243}
244
245static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
246 uint64_t Address,
247 const MCDisassembler *Decoder) {
248 Inst.addOperand(MCOperand::createImm(Imm));
249
250 return Success;
251}
252
253static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
254 uint64_t Address,
255 const MCDisassembler *Decoder) {
256 // This decoder exists to add the dummy Lane operand to the MCInst, which must
257 // be 1 in assembly but has no other real manifestation.
258 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
259 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
260 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
261
262 if (IsToVec) {
263 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(
264 Inst, Rd, Address, Decoder);
265 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(
266 Inst, Rn, Address, Decoder);
267 } else {
268 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(
269 Inst, Rd, Address, Decoder);
270 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(
271 Inst, Rn, Address, Decoder);
272 }
273
274 // Add the lane
275 Inst.addOperand(MCOperand::createImm(1));
276
277 return Success;
278}
279
280static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm,
281 unsigned Add) {
282 Inst.addOperand(MCOperand::createImm(Add - Imm));
283 return Success;
284}
285
286static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm,
287 unsigned Add) {
288 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1)));
289 return Success;
290}
291
292static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
293 uint64_t Addr,
294 const MCDisassembler *Decoder) {
295 return DecodeVecShiftRImm(Inst, Imm, 64);
296}
297
298static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
299 uint64_t Addr,
300 const MCDisassembler *Decoder) {
301 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
302}
303
304static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
305 uint64_t Addr,
306 const MCDisassembler *Decoder) {
307 return DecodeVecShiftRImm(Inst, Imm, 32);
308}
309
310static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
311 uint64_t Addr,
312 const MCDisassembler *Decoder) {
313 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
314}
315
316static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
317 uint64_t Addr,
318 const MCDisassembler *Decoder) {
319 return DecodeVecShiftRImm(Inst, Imm, 16);
320}
321
322static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
323 uint64_t Addr,
324 const MCDisassembler *Decoder) {
325 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
326}
327
328static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
329 uint64_t Addr,
330 const MCDisassembler *Decoder) {
331 return DecodeVecShiftRImm(Inst, Imm, 8);
332}
333
334static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
335 uint64_t Addr,
336 const MCDisassembler *Decoder) {
337 return DecodeVecShiftLImm(Inst, Imm, 64);
338}
339
340static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
341 uint64_t Addr,
342 const MCDisassembler *Decoder) {
343 return DecodeVecShiftLImm(Inst, Imm, 32);
344}
345
346static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
347 uint64_t Addr,
348 const MCDisassembler *Decoder) {
349 return DecodeVecShiftLImm(Inst, Imm, 16);
350}
351
352static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
353 uint64_t Addr,
354 const MCDisassembler *Decoder) {
355 return DecodeVecShiftLImm(Inst, Imm, 8);
356}
357
358static DecodeStatus
359DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
360 const MCDisassembler *Decoder) {
361 unsigned Rd = fieldFromInstruction(insn, 0, 5);
362 unsigned Rn = fieldFromInstruction(insn, 5, 5);
363 unsigned Rm = fieldFromInstruction(insn, 16, 5);
364 unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
365 unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
366 unsigned shift = (shiftHi << 6) | shiftLo;
367 switch (Inst.getOpcode()) {
368 default:
369 return Fail;
370 case AArch64::ADDWrs:
371 case AArch64::ADDSWrs:
372 case AArch64::SUBWrs:
373 case AArch64::SUBSWrs:
374 // if shift == '11' then ReservedValue()
375 if (shiftHi == 0x3)
376 return Fail;
377 [[fallthrough]];
378 case AArch64::ANDWrs:
379 case AArch64::ANDSWrs:
380 case AArch64::BICWrs:
381 case AArch64::BICSWrs:
382 case AArch64::ORRWrs:
383 case AArch64::ORNWrs:
384 case AArch64::EORWrs:
385 case AArch64::EONWrs: {
386 // if sf == '0' and imm6<5> == '1' then ReservedValue()
387 if (shiftLo >> 5 == 1)
388 return Fail;
389 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd, Addr,
390 Decoder);
391 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rn, Addr,
392 Decoder);
393 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr,
394 Decoder);
395 break;
396 }
397 case AArch64::ADDXrs:
398 case AArch64::ADDSXrs:
399 case AArch64::SUBXrs:
400 case AArch64::SUBSXrs:
401 // if shift == '11' then ReservedValue()
402 if (shiftHi == 0x3)
403 return Fail;
404 [[fallthrough]];
405 case AArch64::ANDXrs:
406 case AArch64::ANDSXrs:
407 case AArch64::BICXrs:
408 case AArch64::BICSXrs:
409 case AArch64::ORRXrs:
410 case AArch64::ORNXrs:
411 case AArch64::EORXrs:
412 case AArch64::EONXrs:
413 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
414 Decoder);
415 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rn, Addr,
416 Decoder);
417 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rm, Addr,
418 Decoder);
419 break;
420 }
421
422 Inst.addOperand(MCOperand::createImm(shift));
423 return Success;
424}
425
426static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
427 uint64_t Addr,
428 const MCDisassembler *Decoder) {
429 unsigned Rd = fieldFromInstruction(insn, 0, 5);
430 unsigned imm = fieldFromInstruction(insn, 5, 16);
431 unsigned shift = fieldFromInstruction(insn, 21, 2);
432 shift <<= 4;
433 switch (Inst.getOpcode()) {
434 default:
435 return Fail;
436 case AArch64::MOVZWi:
437 case AArch64::MOVNWi:
438 case AArch64::MOVKWi:
439 if (shift & (1U << 5))
440 return Fail;
441 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd, Addr,
442 Decoder);
443 break;
444 case AArch64::MOVZXi:
445 case AArch64::MOVNXi:
446 case AArch64::MOVKXi:
447 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
448 Decoder);
449 break;
450 }
451
452 if (Inst.getOpcode() == AArch64::MOVKWi ||
453 Inst.getOpcode() == AArch64::MOVKXi)
454 Inst.addOperand(Inst.getOperand(0));
455
456 if (!Decoder->tryAddingSymbolicOperand(Inst, imm, Addr, /*IsBranch*/ false, 0,
457 0, 4))
458 Inst.addOperand(MCOperand::createImm(imm));
459
460 Inst.addOperand(MCOperand::createImm(shift));
461 return Success;
462}
463
464static DecodeStatus
465DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
466 const MCDisassembler *Decoder) {
467 unsigned Rt = fieldFromInstruction(insn, 0, 5);
468 unsigned Rn = fieldFromInstruction(insn, 5, 5);
469 unsigned offset = fieldFromInstruction(insn, 10, 12);
470
471 switch (Inst.getOpcode()) {
472 default:
473 return Fail;
474 case AArch64::PRFMui:
475 // Rt is an immediate in prefetch.
476 Inst.addOperand(MCOperand::createImm(Rt));
477 break;
478 case AArch64::STRBBui:
479 case AArch64::LDRBBui:
480 case AArch64::LDRSBWui:
481 case AArch64::STRHHui:
482 case AArch64::LDRHHui:
483 case AArch64::LDRSHWui:
484 case AArch64::STRWui:
485 case AArch64::LDRWui:
486 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt, Addr,
487 Decoder);
488 break;
489 case AArch64::LDRSBXui:
490 case AArch64::LDRSHXui:
491 case AArch64::LDRSWui:
492 case AArch64::STRXui:
493 case AArch64::LDRXui:
494 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
495 Decoder);
496 break;
497 case AArch64::LDRQui:
498 case AArch64::STRQui:
499 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rt, Addr,
500 Decoder);
501 break;
502 case AArch64::LDRDui:
503 case AArch64::STRDui:
504 DecodeSimpleRegisterClass<AArch64::FPR64RegClassID, 0, 32>(Inst, Rt, Addr,
505 Decoder);
506 break;
507 case AArch64::LDRSui:
508 case AArch64::STRSui:
509 DecodeSimpleRegisterClass<AArch64::FPR32RegClassID, 0, 32>(Inst, Rt, Addr,
510 Decoder);
511 break;
512 case AArch64::LDRHui:
513 case AArch64::STRHui:
514 DecodeSimpleRegisterClass<AArch64::FPR16RegClassID, 0, 32>(Inst, Rt, Addr,
515 Decoder);
516 break;
517 case AArch64::LDRBui:
518 case AArch64::STRBui:
519 DecodeSimpleRegisterClass<AArch64::FPR8RegClassID, 0, 32>(Inst, Rt, Addr,
520 Decoder);
521 break;
522 }
523
524 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
525 Decoder);
526 if (!Decoder->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 0, 4))
527 Inst.addOperand(MCOperand::createImm(offset));
528 return Success;
529}
530
531static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
532 uint64_t Addr,
533 const MCDisassembler *Decoder) {
534 unsigned Rt = fieldFromInstruction(insn, 0, 5);
535 unsigned Rn = fieldFromInstruction(insn, 5, 5);
536 int64_t offset = fieldFromInstruction(insn, 12, 9);
537
538 // offset is a 9-bit signed immediate, so sign extend it to
539 // fill the unsigned.
540 if (offset & (1 << (9 - 1)))
541 offset |= ~((1LL << 9) - 1);
542
543 // First operand is always the writeback to the address register, if needed.
544 switch (Inst.getOpcode()) {
545 default:
546 break;
547 case AArch64::LDRSBWpre:
548 case AArch64::LDRSHWpre:
549 case AArch64::STRBBpre:
550 case AArch64::LDRBBpre:
551 case AArch64::STRHHpre:
552 case AArch64::LDRHHpre:
553 case AArch64::STRWpre:
554 case AArch64::LDRWpre:
555 case AArch64::LDRSBWpost:
556 case AArch64::LDRSHWpost:
557 case AArch64::STRBBpost:
558 case AArch64::LDRBBpost:
559 case AArch64::STRHHpost:
560 case AArch64::LDRHHpost:
561 case AArch64::STRWpost:
562 case AArch64::LDRWpost:
563 case AArch64::LDRSBXpre:
564 case AArch64::LDRSHXpre:
565 case AArch64::STRXpre:
566 case AArch64::LDRSWpre:
567 case AArch64::LDRXpre:
568 case AArch64::LDRSBXpost:
569 case AArch64::LDRSHXpost:
570 case AArch64::STRXpost:
571 case AArch64::LDRSWpost:
572 case AArch64::LDRXpost:
573 case AArch64::LDRQpre:
574 case AArch64::STRQpre:
575 case AArch64::LDRQpost:
576 case AArch64::STRQpost:
577 case AArch64::LDRDpre:
578 case AArch64::STRDpre:
579 case AArch64::LDRDpost:
580 case AArch64::STRDpost:
581 case AArch64::LDRSpre:
582 case AArch64::STRSpre:
583 case AArch64::LDRSpost:
584 case AArch64::STRSpost:
585 case AArch64::LDRHpre:
586 case AArch64::STRHpre:
587 case AArch64::LDRHpost:
588 case AArch64::STRHpost:
589 case AArch64::LDRBpre:
590 case AArch64::STRBpre:
591 case AArch64::LDRBpost:
592 case AArch64::STRBpost:
593 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
594 Decoder);
595 break;
596 }
597
598 switch (Inst.getOpcode()) {
599 default:
600 return Fail;
601 case AArch64::PRFUMi:
602 // Rt is an immediate in prefetch.
603 Inst.addOperand(MCOperand::createImm(Rt));
604 break;
605 case AArch64::STURBBi:
606 case AArch64::LDURBBi:
607 case AArch64::LDURSBWi:
608 case AArch64::STURHHi:
609 case AArch64::LDURHHi:
610 case AArch64::LDURSHWi:
611 case AArch64::STURWi:
612 case AArch64::LDURWi:
613 case AArch64::LDTRSBWi:
614 case AArch64::LDTRSHWi:
615 case AArch64::STTRWi:
616 case AArch64::LDTRWi:
617 case AArch64::STTRHi:
618 case AArch64::LDTRHi:
619 case AArch64::LDTRBi:
620 case AArch64::STTRBi:
621 case AArch64::LDRSBWpre:
622 case AArch64::LDRSHWpre:
623 case AArch64::STRBBpre:
624 case AArch64::LDRBBpre:
625 case AArch64::STRHHpre:
626 case AArch64::LDRHHpre:
627 case AArch64::STRWpre:
628 case AArch64::LDRWpre:
629 case AArch64::LDRSBWpost:
630 case AArch64::LDRSHWpost:
631 case AArch64::STRBBpost:
632 case AArch64::LDRBBpost:
633 case AArch64::STRHHpost:
634 case AArch64::LDRHHpost:
635 case AArch64::STRWpost:
636 case AArch64::LDRWpost:
637 case AArch64::STLURBi:
638 case AArch64::STLURHi:
639 case AArch64::STLURWi:
640 case AArch64::LDAPURBi:
641 case AArch64::LDAPURSBWi:
642 case AArch64::LDAPURHi:
643 case AArch64::LDAPURSHWi:
644 case AArch64::LDAPURi:
645 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt, Addr,
646 Decoder);
647 break;
648 case AArch64::LDURSBXi:
649 case AArch64::LDURSHXi:
650 case AArch64::LDURSWi:
651 case AArch64::STURXi:
652 case AArch64::LDURXi:
653 case AArch64::LDTRSBXi:
654 case AArch64::LDTRSHXi:
655 case AArch64::LDTRSWi:
656 case AArch64::STTRXi:
657 case AArch64::LDTRXi:
658 case AArch64::LDRSBXpre:
659 case AArch64::LDRSHXpre:
660 case AArch64::STRXpre:
661 case AArch64::LDRSWpre:
662 case AArch64::LDRXpre:
663 case AArch64::LDRSBXpost:
664 case AArch64::LDRSHXpost:
665 case AArch64::STRXpost:
666 case AArch64::LDRSWpost:
667 case AArch64::LDRXpost:
668 case AArch64::LDAPURSWi:
669 case AArch64::LDAPURSHXi:
670 case AArch64::LDAPURSBXi:
671 case AArch64::STLURXi:
672 case AArch64::LDAPURXi:
673 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
674 Decoder);
675 break;
676 case AArch64::LDURQi:
677 case AArch64::STURQi:
678 case AArch64::LDRQpre:
679 case AArch64::STRQpre:
680 case AArch64::LDRQpost:
681 case AArch64::STRQpost:
682 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rt, Addr,
683 Decoder);
684 break;
685 case AArch64::LDURDi:
686 case AArch64::STURDi:
687 case AArch64::LDRDpre:
688 case AArch64::STRDpre:
689 case AArch64::LDRDpost:
690 case AArch64::STRDpost:
691 DecodeSimpleRegisterClass<AArch64::FPR64RegClassID, 0, 32>(Inst, Rt, Addr,
692 Decoder);
693 break;
694 case AArch64::LDURSi:
695 case AArch64::STURSi:
696 case AArch64::LDRSpre:
697 case AArch64::STRSpre:
698 case AArch64::LDRSpost:
699 case AArch64::STRSpost:
700 DecodeSimpleRegisterClass<AArch64::FPR32RegClassID, 0, 32>(Inst, Rt, Addr,
701 Decoder);
702 break;
703 case AArch64::LDURHi:
704 case AArch64::STURHi:
705 case AArch64::LDRHpre:
706 case AArch64::STRHpre:
707 case AArch64::LDRHpost:
708 case AArch64::STRHpost:
709 DecodeSimpleRegisterClass<AArch64::FPR16RegClassID, 0, 32>(Inst, Rt, Addr,
710 Decoder);
711 break;
712 case AArch64::LDURBi:
713 case AArch64::STURBi:
714 case AArch64::LDRBpre:
715 case AArch64::STRBpre:
716 case AArch64::LDRBpost:
717 case AArch64::STRBpost:
718 DecodeSimpleRegisterClass<AArch64::FPR8RegClassID, 0, 32>(Inst, Rt, Addr,
719 Decoder);
720 break;
721 }
722
723 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
724 Decoder);
725 Inst.addOperand(MCOperand::createImm(offset));
726
727 bool IsLoad = fieldFromInstruction(insn, 22, 1);
728 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
729 bool IsFP = fieldFromInstruction(insn, 26, 1);
730
731 // Cannot write back to a transfer register (but xzr != sp).
732 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
733 return SoftFail;
734
735 return Success;
736}
737
738static DecodeStatus
739DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
740 const MCDisassembler *Decoder) {
741 unsigned Rt = fieldFromInstruction(insn, 0, 5);
742 unsigned Rn = fieldFromInstruction(insn, 5, 5);
743 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
744 unsigned Rs = fieldFromInstruction(insn, 16, 5);
745
746 unsigned Opcode = Inst.getOpcode();
747 switch (Opcode) {
748 default:
749 return Fail;
750 case AArch64::STLXRW:
751 case AArch64::STLXRB:
752 case AArch64::STLXRH:
753 case AArch64::STXRW:
754 case AArch64::STXRB:
755 case AArch64::STXRH:
756 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rs, Addr,
757 Decoder);
758 [[fallthrough]];
759 case AArch64::LDARW:
760 case AArch64::LDARB:
761 case AArch64::LDARH:
762 case AArch64::LDAXRW:
763 case AArch64::LDAXRB:
764 case AArch64::LDAXRH:
765 case AArch64::LDXRW:
766 case AArch64::LDXRB:
767 case AArch64::LDXRH:
768 case AArch64::STLRW:
769 case AArch64::STLRB:
770 case AArch64::STLRH:
771 case AArch64::STLLRW:
772 case AArch64::STLLRB:
773 case AArch64::STLLRH:
774 case AArch64::LDLARW:
775 case AArch64::LDLARB:
776 case AArch64::LDLARH:
777 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt, Addr,
778 Decoder);
779 break;
780 case AArch64::STLXRX:
781 case AArch64::STXRX:
782 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rs, Addr,
783 Decoder);
784 [[fallthrough]];
785 case AArch64::LDARX:
786 case AArch64::LDAXRX:
787 case AArch64::LDXRX:
788 case AArch64::STLRX:
789 case AArch64::LDLARX:
790 case AArch64::STLLRX:
791 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
792 Decoder);
793 break;
794 case AArch64::STLXPW:
795 case AArch64::STXPW:
796 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rs, Addr,
797 Decoder);
798 [[fallthrough]];
799 case AArch64::LDAXPW:
800 case AArch64::LDXPW:
801 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt, Addr,
802 Decoder);
803 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt2, Addr,
804 Decoder);
805 break;
806 case AArch64::STLXPX:
807 case AArch64::STXPX:
808 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rs, Addr,
809 Decoder);
810 [[fallthrough]];
811 case AArch64::LDAXPX:
812 case AArch64::LDXPX:
813 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
814 Decoder);
815 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt2, Addr,
816 Decoder);
817 break;
818 }
819
820 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
821 Decoder);
822
823 // You shouldn't load to the same register twice in an instruction...
824 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
825 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&
826 Rt == Rt2)
827 return SoftFail;
828
829 return Success;
830}
831
832static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
833 uint64_t Addr,
834 const MCDisassembler *Decoder) {
835 unsigned Rt = fieldFromInstruction(insn, 0, 5);
836 unsigned Rn = fieldFromInstruction(insn, 5, 5);
837 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
838 int64_t offset = fieldFromInstruction(insn, 15, 7);
839 bool IsLoad = fieldFromInstruction(insn, 22, 1);
840
841 // offset is a 7-bit signed immediate, so sign extend it to
842 // fill the unsigned.
843 if (offset & (1 << (7 - 1)))
844 offset |= ~((1LL << 7) - 1);
845
846 unsigned Opcode = Inst.getOpcode();
847 bool NeedsDisjointWritebackTransfer = false;
848
849 // First operand is always writeback of base register.
850 switch (Opcode) {
851 default:
852 break;
853 case AArch64::LDPXpost:
854 case AArch64::STPXpost:
855 case AArch64::LDPSWpost:
856 case AArch64::LDPXpre:
857 case AArch64::STPXpre:
858 case AArch64::LDPSWpre:
859 case AArch64::LDPWpost:
860 case AArch64::STPWpost:
861 case AArch64::LDPWpre:
862 case AArch64::STPWpre:
863 case AArch64::LDPQpost:
864 case AArch64::STPQpost:
865 case AArch64::LDPQpre:
866 case AArch64::STPQpre:
867 case AArch64::LDPDpost:
868 case AArch64::STPDpost:
869 case AArch64::LDPDpre:
870 case AArch64::STPDpre:
871 case AArch64::LDPSpost:
872 case AArch64::STPSpost:
873 case AArch64::LDPSpre:
874 case AArch64::STPSpre:
875 case AArch64::STGPpre:
876 case AArch64::STGPpost:
877 case AArch64::LDTPpre:
878 case AArch64::LDTPpost:
879 case AArch64::LDTPQpost:
880 case AArch64::LDTPQpre:
881 case AArch64::STTPpost:
882 case AArch64::STTPpre:
883 case AArch64::STTPQpost:
884 case AArch64::STTPQpre:
885 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
886 Decoder);
887 break;
888 }
889
890 switch (Opcode) {
891 default:
892 return Fail;
893 case AArch64::LDPXpost:
894 case AArch64::STPXpost:
895 case AArch64::LDPSWpost:
896 case AArch64::LDPXpre:
897 case AArch64::STPXpre:
898 case AArch64::LDPSWpre:
899 case AArch64::STGPpre:
900 case AArch64::STGPpost:
901 case AArch64::LDTPpost:
902 case AArch64::LDTPpre:
903 case AArch64::STTPpost:
904 case AArch64::STTPpre:
905 NeedsDisjointWritebackTransfer = true;
906 [[fallthrough]];
907 case AArch64::LDNPXi:
908 case AArch64::STNPXi:
909 case AArch64::LDPXi:
910 case AArch64::STPXi:
911 case AArch64::LDPSWi:
912 case AArch64::STGPi:
913 case AArch64::LDTPi:
914 case AArch64::STTPi:
915 case AArch64::STTNPXi:
916 case AArch64::LDTNPXi:
917 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
918 Decoder);
919 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt2, Addr,
920 Decoder);
921 break;
922 case AArch64::LDPWpost:
923 case AArch64::STPWpost:
924 case AArch64::LDPWpre:
925 case AArch64::STPWpre:
926 NeedsDisjointWritebackTransfer = true;
927 [[fallthrough]];
928 case AArch64::LDNPWi:
929 case AArch64::STNPWi:
930 case AArch64::LDPWi:
931 case AArch64::STPWi:
932 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt, Addr,
933 Decoder);
934 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt2, Addr,
935 Decoder);
936 break;
937 case AArch64::LDNPQi:
938 case AArch64::STNPQi:
939 case AArch64::LDPQpost:
940 case AArch64::STPQpost:
941 case AArch64::LDPQi:
942 case AArch64::STPQi:
943 case AArch64::LDPQpre:
944 case AArch64::STPQpre:
945 case AArch64::LDTPQi:
946 case AArch64::LDTPQpost:
947 case AArch64::LDTPQpre:
948 case AArch64::LDTNPQi:
949 case AArch64::STTPQi:
950 case AArch64::STTPQpost:
951 case AArch64::STTPQpre:
952 case AArch64::STTNPQi:
953 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rt, Addr,
954 Decoder);
955 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rt2, Addr,
956 Decoder);
957 break;
958 case AArch64::LDNPDi:
959 case AArch64::STNPDi:
960 case AArch64::LDPDpost:
961 case AArch64::STPDpost:
962 case AArch64::LDPDi:
963 case AArch64::STPDi:
964 case AArch64::LDPDpre:
965 case AArch64::STPDpre:
966 DecodeSimpleRegisterClass<AArch64::FPR64RegClassID, 0, 32>(Inst, Rt, Addr,
967 Decoder);
968 DecodeSimpleRegisterClass<AArch64::FPR64RegClassID, 0, 32>(Inst, Rt2, Addr,
969 Decoder);
970 break;
971 case AArch64::LDNPSi:
972 case AArch64::STNPSi:
973 case AArch64::LDPSpost:
974 case AArch64::STPSpost:
975 case AArch64::LDPSi:
976 case AArch64::STPSi:
977 case AArch64::LDPSpre:
978 case AArch64::STPSpre:
979 DecodeSimpleRegisterClass<AArch64::FPR32RegClassID, 0, 32>(Inst, Rt, Addr,
980 Decoder);
981 DecodeSimpleRegisterClass<AArch64::FPR32RegClassID, 0, 32>(Inst, Rt2, Addr,
982 Decoder);
983 break;
984 }
985
986 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
987 Decoder);
988 Inst.addOperand(MCOperand::createImm(offset));
989
990 // You shouldn't load to the same register twice in an instruction...
991 if (IsLoad && Rt == Rt2)
992 return SoftFail;
993
994 // ... or do any operation that writes-back to a transfer register. But note
995 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
996 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
997 return SoftFail;
998
999 return Success;
1000}
1001
1002static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn,
1003 uint64_t Addr,
1004 const MCDisassembler *Decoder) {
1005 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1006 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1007 uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 |
1008 fieldFromInstruction(insn, 12, 9);
1009 unsigned writeback = fieldFromInstruction(insn, 11, 1);
1010
1011 switch (Inst.getOpcode()) {
1012 default:
1013 return Fail;
1014 case AArch64::LDRAAwriteback:
1015 case AArch64::LDRABwriteback:
1016 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(
1017 Inst, Rn /* writeback register */, Addr, Decoder);
1018 break;
1019 case AArch64::LDRAAindexed:
1020 case AArch64::LDRABindexed:
1021 break;
1022 }
1023
1024 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
1025 Decoder);
1026 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1027 Decoder);
1028 DecodeSImm<10>(Inst, offset, Addr, Decoder);
1029
1030 if (writeback && Rt == Rn && Rn != 31) {
1031 return SoftFail;
1032 }
1033
1034 return Success;
1035}
1036
1037static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
1038 uint64_t Addr,
1039 const MCDisassembler *Decoder) {
1040 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1041 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1042 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1043 unsigned extend = fieldFromInstruction(insn, 10, 6);
1044
1045 unsigned shift = extend & 0x7;
1046 if (shift > 4)
1047 return Fail;
1048
1049 switch (Inst.getOpcode()) {
1050 default:
1051 return Fail;
1052 case AArch64::ADDWrx:
1053 case AArch64::SUBWrx:
1054 DecodeSimpleRegisterClass<AArch64::GPR32spRegClassID, 0, 32>(Inst, Rd, Addr,
1055 Decoder);
1056 DecodeSimpleRegisterClass<AArch64::GPR32spRegClassID, 0, 32>(Inst, Rn, Addr,
1057 Decoder);
1058 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr,
1059 Decoder);
1060 break;
1061 case AArch64::ADDSWrx:
1062 case AArch64::SUBSWrx:
1063 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd, Addr,
1064 Decoder);
1065 DecodeSimpleRegisterClass<AArch64::GPR32spRegClassID, 0, 32>(Inst, Rn, Addr,
1066 Decoder);
1067 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr,
1068 Decoder);
1069 break;
1070 case AArch64::ADDXrx:
1071 case AArch64::SUBXrx:
1072 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rd, Addr,
1073 Decoder);
1074 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1075 Decoder);
1076 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr,
1077 Decoder);
1078 break;
1079 case AArch64::ADDSXrx:
1080 case AArch64::SUBSXrx:
1081 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
1082 Decoder);
1083 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1084 Decoder);
1085 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr,
1086 Decoder);
1087 break;
1088 case AArch64::ADDXrx64:
1089 case AArch64::SUBXrx64:
1090 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rd, Addr,
1091 Decoder);
1092 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1093 Decoder);
1094 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rm, Addr,
1095 Decoder);
1096 break;
1097 case AArch64::SUBSXrx64:
1098 case AArch64::ADDSXrx64:
1099 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
1100 Decoder);
1101 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1102 Decoder);
1103 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rm, Addr,
1104 Decoder);
1105 break;
1106 }
1107
1108 Inst.addOperand(MCOperand::createImm(extend));
1109 return Success;
1110}
1111
1112static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
1113 uint64_t Addr,
1114 const MCDisassembler *Decoder) {
1115 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1116 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1117 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1118 unsigned imm;
1119
1120 if (Datasize) {
1121 if (Inst.getOpcode() == AArch64::ANDSXri)
1122 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
1123 Decoder);
1124 else
1125 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(
1126 Inst, Rd, Addr, Decoder);
1127 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rn, Addr,
1128 Decoder);
1129 imm = fieldFromInstruction(insn, 10, 13);
1130 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1131 return Fail;
1132 } else {
1133 if (Inst.getOpcode() == AArch64::ANDSWri)
1134 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd, Addr,
1135 Decoder);
1136 else
1137 DecodeSimpleRegisterClass<AArch64::GPR32spRegClassID, 0, 32>(
1138 Inst, Rd, Addr, Decoder);
1139 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rn, Addr,
1140 Decoder);
1141 imm = fieldFromInstruction(insn, 10, 12);
1142 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32))
1143 return Fail;
1144 }
1145 Inst.addOperand(MCOperand::createImm(imm));
1146 return Success;
1147}
1148
1149static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
1150 uint64_t Addr,
1151 const MCDisassembler *Decoder) {
1152 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1153 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1154 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1155 imm |= fieldFromInstruction(insn, 5, 5);
1156
1157 if (Inst.getOpcode() == AArch64::MOVID)
1158 DecodeSimpleRegisterClass<AArch64::FPR64RegClassID, 0, 32>(Inst, Rd, Addr,
1159 Decoder);
1160 else
1161 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rd, Addr,
1162 Decoder);
1163
1164 Inst.addOperand(MCOperand::createImm(imm));
1165
1166 switch (Inst.getOpcode()) {
1167 default:
1168 break;
1169 case AArch64::MOVIv4i16:
1170 case AArch64::MOVIv8i16:
1171 case AArch64::MVNIv4i16:
1172 case AArch64::MVNIv8i16:
1173 case AArch64::MOVIv2i32:
1174 case AArch64::MOVIv4i32:
1175 case AArch64::MVNIv2i32:
1176 case AArch64::MVNIv4i32:
1177 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
1178 break;
1179 case AArch64::MOVIv2s_msl:
1180 case AArch64::MOVIv4s_msl:
1181 case AArch64::MVNIv2s_msl:
1182 case AArch64::MVNIv4s_msl:
1183 Inst.addOperand(MCOperand::createImm((cmode & 1) ? 0x110 : 0x108));
1184 break;
1185 }
1186
1187 return Success;
1188}
1189
1190static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
1191 uint64_t Addr,
1192 const MCDisassembler *Decoder) {
1193 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1194 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1195 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1196 imm |= fieldFromInstruction(insn, 5, 5);
1197
1198 // Tied operands added twice.
1199 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rd, Addr,
1200 Decoder);
1201 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rd, Addr,
1202 Decoder);
1203
1204 Inst.addOperand(MCOperand::createImm(imm));
1205 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
1206
1207 return Success;
1208}
1209
1210static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
1211 uint64_t Addr,
1212 const MCDisassembler *Decoder) {
1213 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1214 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1215 imm |= fieldFromInstruction(insn, 29, 2);
1216
1217 // Sign-extend the 21-bit immediate.
1218 if (imm & (1 << (21 - 1)))
1219 imm |= ~((1LL << 21) - 1);
1220
1221 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
1222 Decoder);
1223 if (!Decoder->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 0, 4))
1224 Inst.addOperand(MCOperand::createImm(imm));
1225
1226 return Success;
1227}
1228
1229static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn,
1230 uint64_t Addr,
1231 const MCDisassembler *Decoder) {
1232 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1233 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1234 unsigned Imm = fieldFromInstruction(insn, 10, 14);
1235 unsigned S = fieldFromInstruction(insn, 29, 1);
1236 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1237
1238 unsigned ShifterVal = (Imm >> 12) & 3;
1239 unsigned ImmVal = Imm & 0xFFF;
1240
1241 if (ShifterVal != 0 && ShifterVal != 1)
1242 return Fail;
1243
1244 if (Datasize) {
1245 if (Rd == 31 && !S)
1246 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(
1247 Inst, Rd, Addr, Decoder);
1248 else
1249 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
1250 Decoder);
1251 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1252 Decoder);
1253 } else {
1254 if (Rd == 31 && !S)
1255 DecodeSimpleRegisterClass<AArch64::GPR32spRegClassID, 0, 32>(
1256 Inst, Rd, Addr, Decoder);
1257 else
1258 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd, Addr,
1259 Decoder);
1260 DecodeSimpleRegisterClass<AArch64::GPR32spRegClassID, 0, 32>(Inst, Rn, Addr,
1261 Decoder);
1262 }
1263
1264 if (!Decoder->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 0, 4))
1265 Inst.addOperand(MCOperand::createImm(ImmVal));
1266 Inst.addOperand(MCOperand::createImm(12 * ShifterVal));
1267 return Success;
1268}
1269
1270static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
1271 uint64_t Addr,
1272 const MCDisassembler *Decoder) {
1273 int64_t imm = fieldFromInstruction(insn, 0, 26);
1274
1275 // Sign-extend the 26-bit immediate.
1276 if (imm & (1 << (26 - 1)))
1277 imm |= ~((1LL << 26) - 1);
1278
1279 if (!Decoder->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 0, 4))
1280 Inst.addOperand(MCOperand::createImm(imm));
1281
1282 return Success;
1283}
1284
1285static bool isInvalidPState(uint64_t Op1, uint64_t Op2) {
1286 return Op1 == 0b000 && (Op2 == 0b000 || // CFINV
1287 Op2 == 0b001 || // XAFlag
1288 Op2 == 0b010); // AXFlag
1289}
1290
1291static DecodeStatus
1292DecodeSystemPStateImm0_15Instruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1293 const MCDisassembler *Decoder) {
1294 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1295 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1296 uint64_t imm = fieldFromInstruction(insn, 8, 4);
1297 uint64_t pstate_field = (op1 << 3) | op2;
1298
1299 if (isInvalidPState(op1, op2))
1300 return Fail;
1301
1302 Inst.addOperand(MCOperand::createImm(pstate_field));
1303 Inst.addOperand(MCOperand::createImm(imm));
1304
1305 auto PState = AArch64PState::lookupPStateImm0_15ByEncoding(pstate_field);
1306 if (PState &&
1307 PState->haveFeatures(Decoder->getSubtargetInfo().getFeatureBits()))
1308 return Success;
1309 return Fail;
1310}
1311
1312static DecodeStatus
1313DecodeSystemPStateImm0_1Instruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1314 const MCDisassembler *Decoder) {
1315 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1316 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1317 uint64_t crm_high = fieldFromInstruction(insn, 9, 3);
1318 uint64_t imm = fieldFromInstruction(insn, 8, 1);
1319 uint64_t pstate_field = (crm_high << 6) | (op1 << 3) | op2;
1320
1321 if (isInvalidPState(op1, op2))
1322 return Fail;
1323
1324 Inst.addOperand(MCOperand::createImm(pstate_field));
1325 Inst.addOperand(MCOperand::createImm(imm));
1326
1327 auto PState = AArch64PState::lookupPStateImm0_1ByEncoding(pstate_field);
1328 if (PState &&
1329 PState->haveFeatures(Decoder->getSubtargetInfo().getFeatureBits()))
1330 return Success;
1331 return Fail;
1332}
1333
1334static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
1335 uint64_t Addr,
1336 const MCDisassembler *Decoder) {
1337 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1338 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1339 bit |= fieldFromInstruction(insn, 19, 5);
1340 int64_t dst = fieldFromInstruction(insn, 5, 14);
1341
1342 // Sign-extend 14-bit immediate.
1343 if (dst & (1 << (14 - 1)))
1344 dst |= ~((1LL << 14) - 1);
1345
1346 if (fieldFromInstruction(insn, 31, 1) == 0)
1347 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt, Addr,
1348 Decoder);
1349 else
1350 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
1351 Decoder);
1352 Inst.addOperand(MCOperand::createImm(bit));
1353 if (!Decoder->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 0, 4))
1354 Inst.addOperand(MCOperand::createImm(dst));
1355
1356 return Success;
1357}
1358
1359static DecodeStatus
1360DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID,
1361 unsigned RegNo, uint64_t Addr,
1362 const MCDisassembler *Decoder) {
1363 // Register number must be even (see CASP instruction)
1364 if (RegNo & 0x1)
1365 return Fail;
1366
1367 MCRegister Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2);
1368 Inst.addOperand(MCOperand::createReg(Reg));
1369 return Success;
1370}
1371
1372static DecodeStatus
1373DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
1374 const MCDisassembler *Decoder) {
1375 return DecodeGPRSeqPairsClassRegisterClass(
1376 Inst, AArch64::WSeqPairsClassRegClassID, RegNo, Addr, Decoder);
1377}
1378
1379static DecodeStatus
1380DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
1381 const MCDisassembler *Decoder) {
1382 return DecodeGPRSeqPairsClassRegisterClass(
1383 Inst, AArch64::XSeqPairsClassRegClassID, RegNo, Addr, Decoder);
1384}
1385
1386static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn,
1387 uint64_t Addr,
1388 const MCDisassembler *Decoder) {
1389 unsigned op1 = fieldFromInstruction(insn, 16, 3);
1390 unsigned CRn = fieldFromInstruction(insn, 12, 4);
1391 unsigned CRm = fieldFromInstruction(insn, 8, 4);
1392 unsigned op2 = fieldFromInstruction(insn, 5, 3);
1393 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1394 if (Rt != 0b11111)
1395 return Fail;
1396
1397 Inst.addOperand(MCOperand::createImm(op1));
1398 Inst.addOperand(MCOperand::createImm(CRn));
1399 Inst.addOperand(MCOperand::createImm(CRm));
1400 Inst.addOperand(MCOperand::createImm(op2));
1401 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
1402 Decoder);
1403
1404 return Success;
1405}
1406
1407static DecodeStatus
1408DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1409 const MCDisassembler *Decoder) {
1410 unsigned Zdn = fieldFromInstruction(insn, 0, 5);
1411 unsigned imm = fieldFromInstruction(insn, 5, 13);
1412 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1413 return Fail;
1414
1415 // The same (tied) operand is added twice to the instruction.
1416 DecodeSimpleRegisterClass<AArch64::ZPRRegClassID, 0, 32>(Inst, Zdn, Addr,
1417 Decoder);
1418 if (Inst.getOpcode() != AArch64::DUPM_ZI)
1419 DecodeSimpleRegisterClass<AArch64::ZPRRegClassID, 0, 32>(Inst, Zdn, Addr,
1420 Decoder);
1421 Inst.addOperand(MCOperand::createImm(imm));
1422 return Success;
1423}
1424
1425template <int Bits>
1426static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address,
1427 const MCDisassembler *Decoder) {
1428 if (Imm & ~((1LL << Bits) - 1))
1429 return Fail;
1430
1431 // Imm is a signed immediate, so sign extend it.
1432 if (Imm & (1 << (Bits - 1)))
1433 Imm |= ~((1LL << Bits) - 1);
1434
1435 Inst.addOperand(MCOperand::createImm(Imm));
1436 return Success;
1437}
1438
1439// Decode 8-bit signed/unsigned immediate for a given element width.
1440template <int ElementWidth>
1441static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr,
1442 const MCDisassembler *Decoder) {
1443 unsigned Val = (uint8_t)Imm;
1444 unsigned Shift = (Imm & 0x100) ? 8 : 0;
1445 if (ElementWidth == 8 && Shift)
1446 return Fail;
1447 Inst.addOperand(MCOperand::createImm(Val));
1448 Inst.addOperand(MCOperand::createImm(Shift));
1449 return Success;
1450}
1451
1452// Decode uimm4 ranged from 1-16.
1453static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
1454 uint64_t Addr,
1455 const MCDisassembler *Decoder) {
1456 Inst.addOperand(MCOperand::createImm(Imm + 1));
1457 return Success;
1458}
1459
1460static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address,
1461 const MCDisassembler *Decoder) {
1462 if (AArch64SVCR::lookupSVCRByEncoding(Imm)) {
1463 Inst.addOperand(MCOperand::createImm(Imm));
1464 return Success;
1465 }
1466 return Fail;
1467}
1468
1469static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn,
1470 uint64_t Addr,
1471 const MCDisassembler *Decoder) {
1472 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1473 unsigned Rs = fieldFromInstruction(insn, 16, 5);
1474 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1475
1476 // None of the registers may alias: if they do, then the instruction is not
1477 // merely unpredictable but actually entirely unallocated.
1478 if (Rd == Rs || Rs == Rn || Rd == Rn)
1479 return MCDisassembler::Fail;
1480
1481 // All three register operands are written back, so they all appear
1482 // twice in the operand list, once as outputs and once as inputs.
1483 if (!DecodeSimpleRegisterClass<AArch64::GPR64commonRegClassID, 0, 31>(
1484 Inst, Rd, Addr, Decoder) ||
1485 !DecodeSimpleRegisterClass<AArch64::GPR64commonRegClassID, 0, 31>(
1486 Inst, Rs, Addr, Decoder) ||
1487 !DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(
1488 Inst, Rn, Addr, Decoder) ||
1489 !DecodeSimpleRegisterClass<AArch64::GPR64commonRegClassID, 0, 31>(
1490 Inst, Rd, Addr, Decoder) ||
1491 !DecodeSimpleRegisterClass<AArch64::GPR64commonRegClassID, 0, 31>(
1492 Inst, Rs, Addr, Decoder) ||
1493 !DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(
1494 Inst, Rn, Addr, Decoder))
1495 return MCDisassembler::Fail;
1496
1497 return MCDisassembler::Success;
1498}
1499
1500static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn,
1501 uint64_t Addr,
1502 const MCDisassembler *Decoder) {
1503 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1504 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1505 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1506
1507 // None of the registers may alias: if they do, then the instruction is not
1508 // merely unpredictable but actually entirely unallocated.
1509 if (Rd == Rm || Rm == Rn || Rd == Rn)
1510 return MCDisassembler::Fail;
1511
1512 // Rd and Rn (not Rm) register operands are written back, so they appear
1513 // twice in the operand list, once as outputs and once as inputs.
1514 if (!DecodeSimpleRegisterClass<AArch64::GPR64commonRegClassID, 0, 31>(
1515 Inst, Rd, Addr, Decoder) ||
1516 !DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(
1517 Inst, Rn, Addr, Decoder) ||
1518 !DecodeSimpleRegisterClass<AArch64::GPR64commonRegClassID, 0, 31>(
1519 Inst, Rd, Addr, Decoder) ||
1520 !DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(
1521 Inst, Rn, Addr, Decoder) ||
1522 !DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(
1523 Inst, Rm, Addr, Decoder))
1524 return MCDisassembler::Fail;
1525
1526 return MCDisassembler::Success;
1527}
1528
1529static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn,
1530 uint64_t Addr,
1531 const MCDisassembler *Decoder) {
1532 // PRFM with Rt = '11xxx' should be decoded as RPRFM.
1533 // Fail to decode and defer to fallback decoder table to decode RPRFM.
1534 unsigned Mask = 0x18;
1535 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1536 if ((Rt & Mask) == Mask)
1537 return Fail;
1538
1539 uint64_t Rn = fieldFromInstruction(insn, 5, 5);
1540 uint64_t Shift = fieldFromInstruction(insn, 12, 1);
1541 uint64_t Extend = fieldFromInstruction(insn, 15, 1);
1542 uint64_t Rm = fieldFromInstruction(insn, 16, 5);
1543
1544 Inst.addOperand(MCOperand::createImm(Rt));
1545 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1546 Decoder);
1547
1548 switch (Inst.getOpcode()) {
1549 default:
1550 return Fail;
1551 case AArch64::PRFMroW:
1552 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr,
1553 Decoder);
1554 break;
1555 case AArch64::PRFMroX:
1556 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rm, Addr,
1557 Decoder);
1558 break;
1559 }
1560
1561 DecodeMemExtend(Inst, (Extend << 1) | Shift, Addr, Decoder);
1562
1563 return Success;
1564}
1565
1566#include "AArch64GenDisassemblerTables.inc"
1567#include "AArch64GenInstrInfo.inc"
1568
1569static MCDisassembler *createAArch64Disassembler(const Target &T,
1570 const MCSubtargetInfo &STI,
1571 MCContext &Ctx) {
1572
1573 return new AArch64Disassembler(STI, Ctx, T.createMCInstrInfo());
1574}
1575
1576DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
1577 ArrayRef<uint8_t> Bytes,
1578 uint64_t Address,
1579 raw_ostream &CS) const {
1580 CommentStream = &CS;
1581
1582 Size = 0;
1583 // We want to read exactly 4 bytes of data.
1584 if (Bytes.size() < 4)
1585 return Fail;
1586 Size = 4;
1587
1588 // Encoded as a small-endian 32-bit word in the stream.
1589 uint32_t Insn =
1590 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
1591
1592 const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32};
1593
1594 for (const auto *Table : Tables) {
1595 DecodeStatus Result =
1596 decodeInstruction(Table, MI, Insn, Address, this, STI);
1597
1598 const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
1599
1600 // For Scalable Matrix Extension (SME) instructions that have an implicit
1601 // operand for the accumulator (ZA) or implicit immediate zero which isn't
1602 // encoded, manually insert operand.
1603 for (unsigned i = 0; i < Desc.getNumOperands(); i++) {
1604 if (Desc.operands()[i].OperandType == MCOI::OPERAND_REGISTER) {
1605 switch (Desc.operands()[i].RegClass) {
1606 default:
1607 break;
1608 case AArch64::MPRRegClassID:
1609 MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZA));
1610 break;
1611 case AArch64::MPR8RegClassID:
1612 MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZAB0));
1613 break;
1614 case AArch64::ZTRRegClassID:
1615 MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZT0));
1616 break;
1617 }
1618 } else if (Desc.operands()[i].OperandType ==
1619 AArch64::OPERAND_IMPLICIT_IMM_0) {
1620 MI.insert(MI.begin() + i, MCOperand::createImm(0));
1621 }
1622 }
1623
1624 if (MI.getOpcode() == AArch64::LDR_ZA ||
1625 MI.getOpcode() == AArch64::STR_ZA) {
1626 // Spill and fill instructions have a single immediate used for both
1627 // the vector select offset and optional memory offset. Replicate
1628 // the decoded immediate.
1629 const MCOperand &Imm4Op = MI.getOperand(2);
1630 assert(Imm4Op.isImm() && "Unexpected operand type!");
1631 MI.addOperand(Imm4Op);
1632 }
1633
1634 if (Result != MCDisassembler::Fail)
1635 return Result;
1636 }
1637
1638 return MCDisassembler::Fail;
1639}
1640
1641uint64_t AArch64Disassembler::suggestBytesToSkip(ArrayRef<uint8_t> Bytes,
1642 uint64_t Address) const {
1643 // AArch64 instructions are always 4 bytes wide, so there's no point
1644 // in skipping any smaller number of bytes if an instruction can't
1645 // be decoded.
1646 return 4;
1647}
1648
1649static MCSymbolizer *
1650createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo,
1651 LLVMSymbolLookupCallback SymbolLookUp,
1652 void *DisInfo, MCContext *Ctx,
1653 std::unique_ptr<MCRelocationInfo> &&RelInfo) {
1654 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo,
1655 SymbolLookUp, DisInfo);
1656}
1657
1658extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
1659LLVMInitializeAArch64Disassembler() {
1660 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(),
1661 createAArch64Disassembler);
1662 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(),
1663 createAArch64Disassembler);
1664 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(),
1665 createAArch64ExternalSymbolizer);
1666 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(),
1667 createAArch64ExternalSymbolizer);
1668 TargetRegistry::RegisterMCDisassembler(getTheAArch64_32Target(),
1669 createAArch64Disassembler);
1670 TargetRegistry::RegisterMCSymbolizer(getTheAArch64_32Target(),
1671 createAArch64ExternalSymbolizer);
1672
1673 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(),
1674 createAArch64Disassembler);
1675 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(),
1676 createAArch64ExternalSymbolizer);
1677 TargetRegistry::RegisterMCDisassembler(getTheARM64_32Target(),
1678 createAArch64Disassembler);
1679 TargetRegistry::RegisterMCSymbolizer(getTheARM64_32Target(),
1680 createAArch64ExternalSymbolizer);
1681}
DecodeUnconditionalBranch
static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1270
DecodePCRelLabel16
static DecodeStatus DecodePCRelLabel16(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:183
DecodeSystemPStateImm0_1Instruction
static DecodeStatus DecodeSystemPStateImm0_1Instruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1313
DecodeZPRMul2_MinMax
static DecodeStatus DecodeZPRMul2_MinMax(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:75
DecodeVecShiftL64Imm
static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:334
DecodeVecShiftL32Imm
static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:340
createAArch64ExternalSymbolizer
static MCSymbolizer * createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
Definition: AArch64Disassembler.cpp:1650
DecodeCPYMemOpInstruction
static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1469
DecodeVecShiftR8Imm
static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:328
DecodeUnsignedLdStInstruction
static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:465
DecodeModImmTiedInstruction
static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1190
DecodeFixedPointScaleImm64
static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:176
DecodeSystemPStateImm0_15Instruction
static DecodeStatus DecodeSystemPStateImm0_15Instruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1292
DecodeModImmInstruction
static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1149
createAArch64Disassembler
static MCDisassembler * createAArch64Disassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: AArch64Disassembler.cpp:1569
DecodeGPR64x8ClassRegisterClass
static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:60
DecodeThreeAddrSRegInstruction
static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:359
MatrixZATileDecoderTable
static const MCPhysReg MatrixZATileDecoderTable[5][16]
Definition: AArch64Disassembler.cpp:133
DecodeXSeqPairsClassRegisterClass
static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1380
DecodeExclusiveLdStInstruction
static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:739
DecodeVecShiftL16Imm
static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:346
DecodeTestAndBranch
static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1334
SoftFail
#define SoftFail
Definition: AArch64Disassembler.cpp:44
DecodeMatrixTile
static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:145
DecodeSImm
static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1426
DecodeVecShiftR32ImmNarrow
static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:310
DecodeZK
static DecodeStatus DecodeZK(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:101
DecodeAdrInstruction
static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1210
DecodePPR2Mul2RegisterClass
static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:156
DecodePairLdStInstruction
static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:832
DecodeVecShiftL8Imm
static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:352
DecodeSVEIncDecImm
static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1453
DecodeVecShiftRImm
static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, unsigned Add)
Definition: AArch64Disassembler.cpp:280
DecodeFixedPointScaleImm32
static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:167
DecodeMoveImmInstruction
static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:426
DecodeVecShiftR64Imm
static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:292
DecodePCRelLabel9
static DecodeStatus DecodePCRelLabel9(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:213
DecodeVecShiftLImm
static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, unsigned Add)
Definition: AArch64Disassembler.cpp:286
DecodeVecShiftR16ImmNarrow
static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:322
DecodeSVCROp
static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1460
DecodeWSeqPairsClassRegisterClass
static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1373
DecodeVecShiftR64ImmNarrow
static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:298
DecodeZPR4Mul4RegisterClass
static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:112
DecodeLogicalImmInstruction
static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1112
Fail
#define Fail
Definition: AArch64Disassembler.cpp:43
DecodeMSRSystemRegister
static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:245
DecodeZPR2Mul2RegisterClass
static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:88
LLVMInitializeAArch64Disassembler
LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler()
Definition: AArch64Disassembler.cpp:1659
Success
#define Success
Definition: AArch64Disassembler.cpp:42
DecodeSETMemOpInstruction
static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1500
DecodeSVELogicalImmInstruction
static DecodeStatus DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1408
DecodeMemExtend
static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:227
DecodeSignedLdStInstruction
static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:531
DecodeAuthLoadInstruction
static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1002
DecodeSyspXzrInstruction
static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1386
DecodeFMOVLaneInstruction
static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:253
DecodeAddSubERegInstruction
static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1037
isInvalidPState
static bool isInvalidPState(uint64_t Op1, uint64_t Op2)
Definition: AArch64Disassembler.cpp:1285
DecodeSimpleRegisterClass
static DecodeStatus DecodeSimpleRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:47
DecodeMatrixTileListRegisterClass
static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:124
DecodeVecShiftR16Imm
static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:316
DecodeVecShiftR32Imm
static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:304
DecodeImm8OptLsl
static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1441
DecodePRFMRegInstruction
static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1529
DecodeAddSubImmShift
static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1229
DecodeGPRSeqPairsClassRegisterClass
static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1360
DecodeMRSSystemRegister
static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:235
DecodePCRelLabel19
static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:198
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
LLVM_ABI
#define LLVM_ABI
Definition: Compiler.h:213
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:132
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:79
Size
uint64_t Size
Definition: ELFObjHandler.cpp:81
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:110
llvm::AArch64Disassembler::getInstruction
MCDisassembler::DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
Returns the disassembly of a single instruction.
Definition: AArch64Disassembler.cpp:1576
llvm::AArch64Disassembler::suggestBytesToSkip
uint64_t suggestBytesToSkip(ArrayRef< uint8_t > Bytes, uint64_t Address) const override
Suggest a distance to skip in a buffer of data to find the next place to look for the start of an ins...
Definition: AArch64Disassembler.cpp:1641
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:147
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:83
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:85
llvm::MCDisassembler::tryAddingSymbolicOperand
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const
Definition: MCDisassembler.cpp:28
llvm::MCDisassembler::getSubtargetInfo
const MCSubtargetInfo & getSubtargetInfo() const
Definition: MCDisassembler.h:230
llvm::MCDisassembler::STI
const MCSubtargetInfo & STI
Definition: MCDisassembler.h:213
llvm::MCDisassembler::CommentStream
raw_ostream * CommentStream
Definition: MCDisassembler.h:237
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:109
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:188
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:202
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:215
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:210
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:199
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:40
llvm::MCOperand::createReg
static MCOperand createReg(MCRegister Reg)
Definition: MCInst.h:138
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:145
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:66
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:77
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:115
llvm::MCSymbolizer
Symbolize and annotate disassembled instructions.
Definition: MCSymbolizer.h:40
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:146
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:47
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
uint16_t
uint32_t
uint64_t
uint8_t
LLVMSymbolLookupCallback
const char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
Definition: DisassemblerTypes.h:118
LLVMOpInfoCallback
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t OpSize, uint64_t InstSize, int TagType, void *TagBuf)
The type for the operand information call back function.
Definition: DisassemblerTypes.h:48
llvm::AArch64_AM::isValidDecodeLogicalImmediate
static bool isValidDecodeLogicalImmediate(uint64_t val, unsigned regSize)
isValidDecodeLogicalImmediate - Check to see if the logical immediate value in the form "N:immr:imms"...
Definition: AArch64AddressingModes.h:321
llvm::MCD::fieldFromInstruction
std::enable_if_t< std::is_integral_v< IntType >, IntType > fieldFromInstruction(const IntType &Insn, unsigned StartBit, unsigned NumBits)
Definition: MCDecoder.h:36
llvm::MCOI::OPERAND_REGISTER
@ OPERAND_REGISTER
Definition: MCInstrDesc.h:62
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::getTheAArch64beTarget
Target & getTheAArch64beTarget()
Definition: AArch64TargetInfo.cpp:18
llvm::getTheAArch64leTarget
Target & getTheAArch64leTarget()
Definition: AArch64TargetInfo.cpp:14
llvm::getTheAArch64_32Target
Target & getTheAArch64_32Target()
Definition: AArch64TargetInfo.cpp:22
llvm::getTheARM64_32Target
Target & getTheARM64_32Target()
Definition: AArch64TargetInfo.cpp:30
llvm::RecurKind::Add
@ Add
Sum of integers.
llvm::getTheARM64Target
Target & getTheARM64Target()
Definition: AArch64TargetInfo.cpp:26
llvm::DWARFExpression::Operation::Description
Description of the encoding of one expression Op.
Definition: DWARFExpression.h:67
llvm::TargetRegistry::RegisterMCSymbolizer
static void RegisterMCSymbolizer(Target &T, Target::MCSymbolizerCtorTy Fn)
RegisterMCSymbolizer - Register an MCSymbolizer implementation for the given target.
Definition: TargetRegistry.h:987
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition: TargetRegistry.h:897
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