LLVM 22.0.0git
AArch64InstPrinter.cpp
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1//==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This class prints an AArch64 MCInst to a .s file.
10//
11//===----------------------------------------------------------------------===//
12
13#include "AArch64InstPrinter.h"
14#include "MCTargetDesc/AArch64AddressingModes.h"
15#include "Utils/AArch64BaseInfo.h"
16#include "llvm/ADT/StringExtras.h"
17#include "llvm/ADT/StringRef.h"
18#include "llvm/MC/MCAsmInfo.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCRegisterInfo.h"
22#include "llvm/MC/MCSubtargetInfo.h"
23#include "llvm/Support/Casting.h"
24#include "llvm/Support/ErrorHandling.h"
25#include "llvm/Support/Format.h"
26#include "llvm/Support/MathExtras.h"
27#include "llvm/Support/raw_ostream.h"
28#include <cassert>
29#include <cstdint>
30#include <string>
31
32using namespace llvm;
33
34#define DEBUG_TYPE "asm-printer"
35
36#define GET_INSTRUCTION_NAME
37#define PRINT_ALIAS_INSTR
38#include "AArch64GenAsmWriter.inc"
39#define GET_INSTRUCTION_NAME
40#define PRINT_ALIAS_INSTR
41#include "AArch64GenAsmWriter1.inc"
42
43AArch64InstPrinter::AArch64InstPrinter(const MCAsmInfo &MAI,
44 const MCInstrInfo &MII,
45 const MCRegisterInfo &MRI)
46 : MCInstPrinter(MAI, MII, MRI) {}
47
48AArch64AppleInstPrinter::AArch64AppleInstPrinter(const MCAsmInfo &MAI,
49 const MCInstrInfo &MII,
50 const MCRegisterInfo &MRI)
51 : AArch64InstPrinter(MAI, MII, MRI) {}
52
53bool AArch64InstPrinter::applyTargetSpecificCLOption(StringRef Opt) {
54 if (Opt == "no-aliases") {
55 PrintAliases = false;
56 return true;
57 }
58 return false;
59}
60
61void AArch64InstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) {
62 markup(OS, Markup::Register) << getRegisterName(Reg);
63}
64
65void AArch64InstPrinter::printRegName(raw_ostream &OS, MCRegister Reg,
66 unsigned AltIdx) {
67 markup(OS, Markup::Register) << getRegisterName(Reg, AltIdx);
68}
69
70StringRef AArch64InstPrinter::getRegName(MCRegister Reg) const {
71 return getRegisterName(Reg);
72}
73
74void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
75 StringRef Annot, const MCSubtargetInfo &STI,
76 raw_ostream &O) {
77 // Check for special encodings and print the canonical alias instead.
78
79 unsigned Opcode = MI->getOpcode();
80
81 if (Opcode == AArch64::SYSxt)
82 if (printSysAlias(MI, STI, O)) {
83 printAnnotation(O, Annot);
84 return;
85 }
86
87 if (Opcode == AArch64::SYSPxt || Opcode == AArch64::SYSPxt_XZR)
88 if (printSyspAlias(MI, STI, O)) {
89 printAnnotation(O, Annot);
90 return;
91 }
92
93 // RPRFM overlaps PRFM (reg), so try to print it as RPRFM here.
94 if ((Opcode == AArch64::PRFMroX) || (Opcode == AArch64::PRFMroW)) {
95 if (printRangePrefetchAlias(MI, STI, O, Annot))
96 return;
97 }
98
99 // SBFM/UBFM should print to a nicer aliased form if possible.
100 if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri ||
101 Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) {
102 const MCOperand &Op0 = MI->getOperand(0);
103 const MCOperand &Op1 = MI->getOperand(1);
104 const MCOperand &Op2 = MI->getOperand(2);
105 const MCOperand &Op3 = MI->getOperand(3);
106
107 bool IsSigned = (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri);
108 bool Is64Bit = (Opcode == AArch64::SBFMXri || Opcode == AArch64::UBFMXri);
109 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) {
110 const char *AsmMnemonic = nullptr;
111
112 switch (Op3.getImm()) {
113 default:
114 break;
115 case 7:
116 if (IsSigned)
117 AsmMnemonic = "sxtb";
118 else if (!Is64Bit)
119 AsmMnemonic = "uxtb";
120 break;
121 case 15:
122 if (IsSigned)
123 AsmMnemonic = "sxth";
124 else if (!Is64Bit)
125 AsmMnemonic = "uxth";
126 break;
127 case 31:
128 // *xtw is only valid for signed 64-bit operations.
129 if (Is64Bit && IsSigned)
130 AsmMnemonic = "sxtw";
131 break;
132 }
133
134 if (AsmMnemonic) {
135 O << '\t' << AsmMnemonic << '\t';
136 printRegName(O, Op0.getReg());
137 O << ", ";
138 printRegName(O, getWRegFromXReg(Op1.getReg()));
139 printAnnotation(O, Annot);
140 return;
141 }
142 }
143
144 // All immediate shifts are aliases, implemented using the Bitfield
145 // instruction. In all cases the immediate shift amount shift must be in
146 // the range 0 to (reg.size -1).
147 if (Op2.isImm() && Op3.isImm()) {
148 const char *AsmMnemonic = nullptr;
149 int shift = 0;
150 int64_t immr = Op2.getImm();
151 int64_t imms = Op3.getImm();
152 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
153 AsmMnemonic = "lsl";
154 shift = 31 - imms;
155 } else if (Opcode == AArch64::UBFMXri && imms != 0x3f &&
156 ((imms + 1 == immr))) {
157 AsmMnemonic = "lsl";
158 shift = 63 - imms;
159 } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) {
160 AsmMnemonic = "lsr";
161 shift = immr;
162 } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) {
163 AsmMnemonic = "lsr";
164 shift = immr;
165 } else if (Opcode == AArch64::SBFMWri && imms == 0x1f) {
166 AsmMnemonic = "asr";
167 shift = immr;
168 } else if (Opcode == AArch64::SBFMXri && imms == 0x3f) {
169 AsmMnemonic = "asr";
170 shift = immr;
171 }
172 if (AsmMnemonic) {
173 O << '\t' << AsmMnemonic << '\t';
174 printRegName(O, Op0.getReg());
175 O << ", ";
176 printRegName(O, Op1.getReg());
177 O << ", ";
178 markup(O, Markup::Immediate) << "#" << shift;
179 printAnnotation(O, Annot);
180 return;
181 }
182 }
183
184 // SBFIZ/UBFIZ aliases
185 if (Op2.getImm() > Op3.getImm()) {
186 O << '\t' << (IsSigned ? "sbfiz" : "ubfiz") << '\t';
187 printRegName(O, Op0.getReg());
188 O << ", ";
189 printRegName(O, Op1.getReg());
190 O << ", ";
191 markup(O, Markup::Immediate) << "#" << (Is64Bit ? 64 : 32) - Op2.getImm();
192 O << ", ";
193 markup(O, Markup::Immediate) << "#" << Op3.getImm() + 1;
194 printAnnotation(O, Annot);
195 return;
196 }
197
198 // Otherwise SBFX/UBFX is the preferred form
199 O << '\t' << (IsSigned ? "sbfx" : "ubfx") << '\t';
200 printRegName(O, Op0.getReg());
201 O << ", ";
202 printRegName(O, Op1.getReg());
203 O << ", ";
204 markup(O, Markup::Immediate) << "#" << Op2.getImm();
205 O << ", ";
206 markup(O, Markup::Immediate) << "#" << Op3.getImm() - Op2.getImm() + 1;
207 printAnnotation(O, Annot);
208 return;
209 }
210
211 if (Opcode == AArch64::BFMXri || Opcode == AArch64::BFMWri) {
212 const MCOperand &Op0 = MI->getOperand(0); // Op1 == Op0
213 const MCOperand &Op2 = MI->getOperand(2);
214 int ImmR = MI->getOperand(3).getImm();
215 int ImmS = MI->getOperand(4).getImm();
216
217 if ((Op2.getReg() == AArch64::WZR || Op2.getReg() == AArch64::XZR) &&
218 (ImmR == 0 || ImmS < ImmR) && STI.hasFeature(AArch64::HasV8_2aOps)) {
219 // BFC takes precedence over its entire range, slightly differently to BFI.
220 int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32;
221 int LSB = (BitWidth - ImmR) % BitWidth;
222 int Width = ImmS + 1;
223
224 O << "\tbfc\t";
225 printRegName(O, Op0.getReg());
226 O << ", ";
227 markup(O, Markup::Immediate) << "#" << LSB;
228 O << ", ";
229 markup(O, Markup::Immediate) << "#" << Width;
230 printAnnotation(O, Annot);
231 return;
232 } else if (ImmS < ImmR) {
233 // BFI alias
234 int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32;
235 int LSB = (BitWidth - ImmR) % BitWidth;
236 int Width = ImmS + 1;
237
238 O << "\tbfi\t";
239 printRegName(O, Op0.getReg());
240 O << ", ";
241 printRegName(O, Op2.getReg());
242 O << ", ";
243 markup(O, Markup::Immediate) << "#" << LSB;
244 O << ", ";
245 markup(O, Markup::Immediate) << "#" << Width;
246 printAnnotation(O, Annot);
247 return;
248 }
249
250 int LSB = ImmR;
251 int Width = ImmS - ImmR + 1;
252 // Otherwise BFXIL the preferred form
253 O << "\tbfxil\t";
254 printRegName(O, Op0.getReg());
255 O << ", ";
256 printRegName(O, Op2.getReg());
257 O << ", ";
258 markup(O, Markup::Immediate) << "#" << LSB;
259 O << ", ";
260 markup(O, Markup::Immediate) << "#" << Width;
261 printAnnotation(O, Annot);
262 return;
263 }
264
265 // Symbolic operands for MOVZ, MOVN and MOVK already imply a shift
266 // (e.g. :gottprel_g1: is always going to be "lsl #16") so it should not be
267 // printed.
268 if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi ||
269 Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) &&
270 MI->getOperand(1).isExpr()) {
271 if (Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi)
272 O << "\tmovz\t";
273 else
274 O << "\tmovn\t";
275
276 printRegName(O, MI->getOperand(0).getReg());
277 O << ", ";
278 {
279 WithMarkup M = markup(O, Markup::Immediate);
280 O << "#";
281 MAI.printExpr(O, *MI->getOperand(1).getExpr());
282 }
283 return;
284 }
285
286 if ((Opcode == AArch64::MOVKXi || Opcode == AArch64::MOVKWi) &&
287 MI->getOperand(2).isExpr()) {
288 O << "\tmovk\t";
289 printRegName(O, MI->getOperand(0).getReg());
290 O << ", ";
291 {
292 WithMarkup M = markup(O, Markup::Immediate);
293 O << "#";
294 MAI.printExpr(O, *MI->getOperand(2).getExpr());
295 }
296 return;
297 }
298
299 auto PrintMovImm = [&](uint64_t Value, int RegWidth) {
300 int64_t SExtVal = SignExtend64(Value, RegWidth);
301 O << "\tmov\t";
302 printRegName(O, MI->getOperand(0).getReg());
303 O << ", ";
304 markup(O, Markup::Immediate) << "#" << formatImm(SExtVal);
305 if (CommentStream) {
306 // Do the opposite to that used for instruction operands.
307 if (getPrintImmHex())
308 *CommentStream << '=' << formatDec(SExtVal) << '\n';
309 else {
310 uint64_t Mask = maskTrailingOnes<uint64_t>(RegWidth);
311 *CommentStream << '=' << formatHex(SExtVal & Mask) << '\n';
312 }
313 }
314 };
315
316 // MOVZ, MOVN and "ORR wzr, #imm" instructions are aliases for MOV, but their
317 // domains overlap so they need to be prioritized. The chain is "MOVZ lsl #0 >
318 // MOVZ lsl #N > MOVN lsl #0 > MOVN lsl #N > ORR". The highest instruction
319 // that can represent the move is the MOV alias, and the rest get printed
320 // normally.
321 if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi) &&
322 MI->getOperand(1).isImm() && MI->getOperand(2).isImm()) {
323 int RegWidth = Opcode == AArch64::MOVZXi ? 64 : 32;
324 int Shift = MI->getOperand(2).getImm();
325 uint64_t Value = (uint64_t)MI->getOperand(1).getImm() << Shift;
326
327 if (AArch64_AM::isMOVZMovAlias(Value, Shift,
328 Opcode == AArch64::MOVZXi ? 64 : 32)) {
329 PrintMovImm(Value, RegWidth);
330 return;
331 }
332 }
333
334 if ((Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) &&
335 MI->getOperand(1).isImm() && MI->getOperand(2).isImm()) {
336 int RegWidth = Opcode == AArch64::MOVNXi ? 64 : 32;
337 int Shift = MI->getOperand(2).getImm();
338 uint64_t Value = ~((uint64_t)MI->getOperand(1).getImm() << Shift);
339 if (RegWidth == 32)
340 Value = Value & 0xffffffff;
341
342 if (AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth)) {
343 PrintMovImm(Value, RegWidth);
344 return;
345 }
346 }
347
348 if ((Opcode == AArch64::ORRXri || Opcode == AArch64::ORRWri) &&
349 (MI->getOperand(1).getReg() == AArch64::XZR ||
350 MI->getOperand(1).getReg() == AArch64::WZR) &&
351 MI->getOperand(2).isImm()) {
352 int RegWidth = Opcode == AArch64::ORRXri ? 64 : 32;
353 uint64_t Value = AArch64_AM::decodeLogicalImmediate(
354 MI->getOperand(2).getImm(), RegWidth);
355 if (!AArch64_AM::isAnyMOVWMovAlias(Value, RegWidth)) {
356 PrintMovImm(Value, RegWidth);
357 return;
358 }
359 }
360
361 if (Opcode == AArch64::SPACE) {
362 O << '\t' << MAI.getCommentString() << " SPACE "
363 << MI->getOperand(1).getImm();
364 printAnnotation(O, Annot);
365 return;
366 }
367
368 // Instruction TSB is specified as a one operand instruction, but 'csync' is
369 // not encoded, so for printing it is treated as a special case here:
370 if (Opcode == AArch64::TSB) {
371 O << "\ttsb\tcsync";
372 return;
373 }
374
375 if (!PrintAliases || !printAliasInstr(MI, Address, STI, O))
376 printInstruction(MI, Address, STI, O);
377
378 printAnnotation(O, Annot);
379
380 if (atomicBarrierDroppedOnZero(Opcode) &&
381 (MI->getOperand(0).getReg() == AArch64::XZR ||
382 MI->getOperand(0).getReg() == AArch64::WZR)) {
383 printAnnotation(O, "acquire semantics dropped since destination is zero");
384 }
385}
386
387static bool isTblTbxInstruction(unsigned Opcode, StringRef &Layout,
388 bool &IsTbx) {
389 switch (Opcode) {
390 case AArch64::TBXv8i8One:
391 case AArch64::TBXv8i8Two:
392 case AArch64::TBXv8i8Three:
393 case AArch64::TBXv8i8Four:
394 IsTbx = true;
395 Layout = ".8b";
396 return true;
397 case AArch64::TBLv8i8One:
398 case AArch64::TBLv8i8Two:
399 case AArch64::TBLv8i8Three:
400 case AArch64::TBLv8i8Four:
401 IsTbx = false;
402 Layout = ".8b";
403 return true;
404 case AArch64::TBXv16i8One:
405 case AArch64::TBXv16i8Two:
406 case AArch64::TBXv16i8Three:
407 case AArch64::TBXv16i8Four:
408 IsTbx = true;
409 Layout = ".16b";
410 return true;
411 case AArch64::TBLv16i8One:
412 case AArch64::TBLv16i8Two:
413 case AArch64::TBLv16i8Three:
414 case AArch64::TBLv16i8Four:
415 IsTbx = false;
416 Layout = ".16b";
417 return true;
418 default:
419 return false;
420 }
421}
422
423struct LdStNInstrDesc {
424 unsigned Opcode;
425 const char *Mnemonic;
426 const char *Layout;
427 int ListOperand;
428 bool HasLane;
429 int NaturalOffset;
430};
431
432static const LdStNInstrDesc LdStNInstInfo[] = {
433 { AArch64::LD1i8, "ld1", ".b", 1, true, 0 },
434 { AArch64::LD1i16, "ld1", ".h", 1, true, 0 },
435 { AArch64::LD1i32, "ld1", ".s", 1, true, 0 },
436 { AArch64::LD1i64, "ld1", ".d", 1, true, 0 },
437 { AArch64::LD1i8_POST, "ld1", ".b", 2, true, 1 },
438 { AArch64::LD1i16_POST, "ld1", ".h", 2, true, 2 },
439 { AArch64::LD1i32_POST, "ld1", ".s", 2, true, 4 },
440 { AArch64::LD1i64_POST, "ld1", ".d", 2, true, 8 },
441 { AArch64::LD1Rv16b, "ld1r", ".16b", 0, false, 0 },
442 { AArch64::LD1Rv8h, "ld1r", ".8h", 0, false, 0 },
443 { AArch64::LD1Rv4s, "ld1r", ".4s", 0, false, 0 },
444 { AArch64::LD1Rv2d, "ld1r", ".2d", 0, false, 0 },
445 { AArch64::LD1Rv8b, "ld1r", ".8b", 0, false, 0 },
446 { AArch64::LD1Rv4h, "ld1r", ".4h", 0, false, 0 },
447 { AArch64::LD1Rv2s, "ld1r", ".2s", 0, false, 0 },
448 { AArch64::LD1Rv1d, "ld1r", ".1d", 0, false, 0 },
449 { AArch64::LD1Rv16b_POST, "ld1r", ".16b", 1, false, 1 },
450 { AArch64::LD1Rv8h_POST, "ld1r", ".8h", 1, false, 2 },
451 { AArch64::LD1Rv4s_POST, "ld1r", ".4s", 1, false, 4 },
452 { AArch64::LD1Rv2d_POST, "ld1r", ".2d", 1, false, 8 },
453 { AArch64::LD1Rv8b_POST, "ld1r", ".8b", 1, false, 1 },
454 { AArch64::LD1Rv4h_POST, "ld1r", ".4h", 1, false, 2 },
455 { AArch64::LD1Rv2s_POST, "ld1r", ".2s", 1, false, 4 },
456 { AArch64::LD1Rv1d_POST, "ld1r", ".1d", 1, false, 8 },
457 { AArch64::LD1Onev16b, "ld1", ".16b", 0, false, 0 },
458 { AArch64::LD1Onev8h, "ld1", ".8h", 0, false, 0 },
459 { AArch64::LD1Onev4s, "ld1", ".4s", 0, false, 0 },
460 { AArch64::LD1Onev2d, "ld1", ".2d", 0, false, 0 },
461 { AArch64::LD1Onev8b, "ld1", ".8b", 0, false, 0 },
462 { AArch64::LD1Onev4h, "ld1", ".4h", 0, false, 0 },
463 { AArch64::LD1Onev2s, "ld1", ".2s", 0, false, 0 },
464 { AArch64::LD1Onev1d, "ld1", ".1d", 0, false, 0 },
465 { AArch64::LD1Onev16b_POST, "ld1", ".16b", 1, false, 16 },
466 { AArch64::LD1Onev8h_POST, "ld1", ".8h", 1, false, 16 },
467 { AArch64::LD1Onev4s_POST, "ld1", ".4s", 1, false, 16 },
468 { AArch64::LD1Onev2d_POST, "ld1", ".2d", 1, false, 16 },
469 { AArch64::LD1Onev8b_POST, "ld1", ".8b", 1, false, 8 },
470 { AArch64::LD1Onev4h_POST, "ld1", ".4h", 1, false, 8 },
471 { AArch64::LD1Onev2s_POST, "ld1", ".2s", 1, false, 8 },
472 { AArch64::LD1Onev1d_POST, "ld1", ".1d", 1, false, 8 },
473 { AArch64::LD1Twov16b, "ld1", ".16b", 0, false, 0 },
474 { AArch64::LD1Twov8h, "ld1", ".8h", 0, false, 0 },
475 { AArch64::LD1Twov4s, "ld1", ".4s", 0, false, 0 },
476 { AArch64::LD1Twov2d, "ld1", ".2d", 0, false, 0 },
477 { AArch64::LD1Twov8b, "ld1", ".8b", 0, false, 0 },
478 { AArch64::LD1Twov4h, "ld1", ".4h", 0, false, 0 },
479 { AArch64::LD1Twov2s, "ld1", ".2s", 0, false, 0 },
480 { AArch64::LD1Twov1d, "ld1", ".1d", 0, false, 0 },
481 { AArch64::LD1Twov16b_POST, "ld1", ".16b", 1, false, 32 },
482 { AArch64::LD1Twov8h_POST, "ld1", ".8h", 1, false, 32 },
483 { AArch64::LD1Twov4s_POST, "ld1", ".4s", 1, false, 32 },
484 { AArch64::LD1Twov2d_POST, "ld1", ".2d", 1, false, 32 },
485 { AArch64::LD1Twov8b_POST, "ld1", ".8b", 1, false, 16 },
486 { AArch64::LD1Twov4h_POST, "ld1", ".4h", 1, false, 16 },
487 { AArch64::LD1Twov2s_POST, "ld1", ".2s", 1, false, 16 },
488 { AArch64::LD1Twov1d_POST, "ld1", ".1d", 1, false, 16 },
489 { AArch64::LD1Threev16b, "ld1", ".16b", 0, false, 0 },
490 { AArch64::LD1Threev8h, "ld1", ".8h", 0, false, 0 },
491 { AArch64::LD1Threev4s, "ld1", ".4s", 0, false, 0 },
492 { AArch64::LD1Threev2d, "ld1", ".2d", 0, false, 0 },
493 { AArch64::LD1Threev8b, "ld1", ".8b", 0, false, 0 },
494 { AArch64::LD1Threev4h, "ld1", ".4h", 0, false, 0 },
495 { AArch64::LD1Threev2s, "ld1", ".2s", 0, false, 0 },
496 { AArch64::LD1Threev1d, "ld1", ".1d", 0, false, 0 },
497 { AArch64::LD1Threev16b_POST, "ld1", ".16b", 1, false, 48 },
498 { AArch64::LD1Threev8h_POST, "ld1", ".8h", 1, false, 48 },
499 { AArch64::LD1Threev4s_POST, "ld1", ".4s", 1, false, 48 },
500 { AArch64::LD1Threev2d_POST, "ld1", ".2d", 1, false, 48 },
501 { AArch64::LD1Threev8b_POST, "ld1", ".8b", 1, false, 24 },
502 { AArch64::LD1Threev4h_POST, "ld1", ".4h", 1, false, 24 },
503 { AArch64::LD1Threev2s_POST, "ld1", ".2s", 1, false, 24 },
504 { AArch64::LD1Threev1d_POST, "ld1", ".1d", 1, false, 24 },
505 { AArch64::LD1Fourv16b, "ld1", ".16b", 0, false, 0 },
506 { AArch64::LD1Fourv8h, "ld1", ".8h", 0, false, 0 },
507 { AArch64::LD1Fourv4s, "ld1", ".4s", 0, false, 0 },
508 { AArch64::LD1Fourv2d, "ld1", ".2d", 0, false, 0 },
509 { AArch64::LD1Fourv8b, "ld1", ".8b", 0, false, 0 },
510 { AArch64::LD1Fourv4h, "ld1", ".4h", 0, false, 0 },
511 { AArch64::LD1Fourv2s, "ld1", ".2s", 0, false, 0 },
512 { AArch64::LD1Fourv1d, "ld1", ".1d", 0, false, 0 },
513 { AArch64::LD1Fourv16b_POST, "ld1", ".16b", 1, false, 64 },
514 { AArch64::LD1Fourv8h_POST, "ld1", ".8h", 1, false, 64 },
515 { AArch64::LD1Fourv4s_POST, "ld1", ".4s", 1, false, 64 },
516 { AArch64::LD1Fourv2d_POST, "ld1", ".2d", 1, false, 64 },
517 { AArch64::LD1Fourv8b_POST, "ld1", ".8b", 1, false, 32 },
518 { AArch64::LD1Fourv4h_POST, "ld1", ".4h", 1, false, 32 },
519 { AArch64::LD1Fourv2s_POST, "ld1", ".2s", 1, false, 32 },
520 { AArch64::LD1Fourv1d_POST, "ld1", ".1d", 1, false, 32 },
521 { AArch64::LD2i8, "ld2", ".b", 1, true, 0 },
522 { AArch64::LD2i16, "ld2", ".h", 1, true, 0 },
523 { AArch64::LD2i32, "ld2", ".s", 1, true, 0 },
524 { AArch64::LD2i64, "ld2", ".d", 1, true, 0 },
525 { AArch64::LD2i8_POST, "ld2", ".b", 2, true, 2 },
526 { AArch64::LD2i16_POST, "ld2", ".h", 2, true, 4 },
527 { AArch64::LD2i32_POST, "ld2", ".s", 2, true, 8 },
528 { AArch64::LD2i64_POST, "ld2", ".d", 2, true, 16 },
529 { AArch64::LD2Rv16b, "ld2r", ".16b", 0, false, 0 },
530 { AArch64::LD2Rv8h, "ld2r", ".8h", 0, false, 0 },
531 { AArch64::LD2Rv4s, "ld2r", ".4s", 0, false, 0 },
532 { AArch64::LD2Rv2d, "ld2r", ".2d", 0, false, 0 },
533 { AArch64::LD2Rv8b, "ld2r", ".8b", 0, false, 0 },
534 { AArch64::LD2Rv4h, "ld2r", ".4h", 0, false, 0 },
535 { AArch64::LD2Rv2s, "ld2r", ".2s", 0, false, 0 },
536 { AArch64::LD2Rv1d, "ld2r", ".1d", 0, false, 0 },
537 { AArch64::LD2Rv16b_POST, "ld2r", ".16b", 1, false, 2 },
538 { AArch64::LD2Rv8h_POST, "ld2r", ".8h", 1, false, 4 },
539 { AArch64::LD2Rv4s_POST, "ld2r", ".4s", 1, false, 8 },
540 { AArch64::LD2Rv2d_POST, "ld2r", ".2d", 1, false, 16 },
541 { AArch64::LD2Rv8b_POST, "ld2r", ".8b", 1, false, 2 },
542 { AArch64::LD2Rv4h_POST, "ld2r", ".4h", 1, false, 4 },
543 { AArch64::LD2Rv2s_POST, "ld2r", ".2s", 1, false, 8 },
544 { AArch64::LD2Rv1d_POST, "ld2r", ".1d", 1, false, 16 },
545 { AArch64::LD2Twov16b, "ld2", ".16b", 0, false, 0 },
546 { AArch64::LD2Twov8h, "ld2", ".8h", 0, false, 0 },
547 { AArch64::LD2Twov4s, "ld2", ".4s", 0, false, 0 },
548 { AArch64::LD2Twov2d, "ld2", ".2d", 0, false, 0 },
549 { AArch64::LD2Twov8b, "ld2", ".8b", 0, false, 0 },
550 { AArch64::LD2Twov4h, "ld2", ".4h", 0, false, 0 },
551 { AArch64::LD2Twov2s, "ld2", ".2s", 0, false, 0 },
552 { AArch64::LD2Twov16b_POST, "ld2", ".16b", 1, false, 32 },
553 { AArch64::LD2Twov8h_POST, "ld2", ".8h", 1, false, 32 },
554 { AArch64::LD2Twov4s_POST, "ld2", ".4s", 1, false, 32 },
555 { AArch64::LD2Twov2d_POST, "ld2", ".2d", 1, false, 32 },
556 { AArch64::LD2Twov8b_POST, "ld2", ".8b", 1, false, 16 },
557 { AArch64::LD2Twov4h_POST, "ld2", ".4h", 1, false, 16 },
558 { AArch64::LD2Twov2s_POST, "ld2", ".2s", 1, false, 16 },
559 { AArch64::LD3i8, "ld3", ".b", 1, true, 0 },
560 { AArch64::LD3i16, "ld3", ".h", 1, true, 0 },
561 { AArch64::LD3i32, "ld3", ".s", 1, true, 0 },
562 { AArch64::LD3i64, "ld3", ".d", 1, true, 0 },
563 { AArch64::LD3i8_POST, "ld3", ".b", 2, true, 3 },
564 { AArch64::LD3i16_POST, "ld3", ".h", 2, true, 6 },
565 { AArch64::LD3i32_POST, "ld3", ".s", 2, true, 12 },
566 { AArch64::LD3i64_POST, "ld3", ".d", 2, true, 24 },
567 { AArch64::LD3Rv16b, "ld3r", ".16b", 0, false, 0 },
568 { AArch64::LD3Rv8h, "ld3r", ".8h", 0, false, 0 },
569 { AArch64::LD3Rv4s, "ld3r", ".4s", 0, false, 0 },
570 { AArch64::LD3Rv2d, "ld3r", ".2d", 0, false, 0 },
571 { AArch64::LD3Rv8b, "ld3r", ".8b", 0, false, 0 },
572 { AArch64::LD3Rv4h, "ld3r", ".4h", 0, false, 0 },
573 { AArch64::LD3Rv2s, "ld3r", ".2s", 0, false, 0 },
574 { AArch64::LD3Rv1d, "ld3r", ".1d", 0, false, 0 },
575 { AArch64::LD3Rv16b_POST, "ld3r", ".16b", 1, false, 3 },
576 { AArch64::LD3Rv8h_POST, "ld3r", ".8h", 1, false, 6 },
577 { AArch64::LD3Rv4s_POST, "ld3r", ".4s", 1, false, 12 },
578 { AArch64::LD3Rv2d_POST, "ld3r", ".2d", 1, false, 24 },
579 { AArch64::LD3Rv8b_POST, "ld3r", ".8b", 1, false, 3 },
580 { AArch64::LD3Rv4h_POST, "ld3r", ".4h", 1, false, 6 },
581 { AArch64::LD3Rv2s_POST, "ld3r", ".2s", 1, false, 12 },
582 { AArch64::LD3Rv1d_POST, "ld3r", ".1d", 1, false, 24 },
583 { AArch64::LD3Threev16b, "ld3", ".16b", 0, false, 0 },
584 { AArch64::LD3Threev8h, "ld3", ".8h", 0, false, 0 },
585 { AArch64::LD3Threev4s, "ld3", ".4s", 0, false, 0 },
586 { AArch64::LD3Threev2d, "ld3", ".2d", 0, false, 0 },
587 { AArch64::LD3Threev8b, "ld3", ".8b", 0, false, 0 },
588 { AArch64::LD3Threev4h, "ld3", ".4h", 0, false, 0 },
589 { AArch64::LD3Threev2s, "ld3", ".2s", 0, false, 0 },
590 { AArch64::LD3Threev16b_POST, "ld3", ".16b", 1, false, 48 },
591 { AArch64::LD3Threev8h_POST, "ld3", ".8h", 1, false, 48 },
592 { AArch64::LD3Threev4s_POST, "ld3", ".4s", 1, false, 48 },
593 { AArch64::LD3Threev2d_POST, "ld3", ".2d", 1, false, 48 },
594 { AArch64::LD3Threev8b_POST, "ld3", ".8b", 1, false, 24 },
595 { AArch64::LD3Threev4h_POST, "ld3", ".4h", 1, false, 24 },
596 { AArch64::LD3Threev2s_POST, "ld3", ".2s", 1, false, 24 },
597 { AArch64::LD4i8, "ld4", ".b", 1, true, 0 },
598 { AArch64::LD4i16, "ld4", ".h", 1, true, 0 },
599 { AArch64::LD4i32, "ld4", ".s", 1, true, 0 },
600 { AArch64::LD4i64, "ld4", ".d", 1, true, 0 },
601 { AArch64::LD4i8_POST, "ld4", ".b", 2, true, 4 },
602 { AArch64::LD4i16_POST, "ld4", ".h", 2, true, 8 },
603 { AArch64::LD4i32_POST, "ld4", ".s", 2, true, 16 },
604 { AArch64::LD4i64_POST, "ld4", ".d", 2, true, 32 },
605 { AArch64::LD4Rv16b, "ld4r", ".16b", 0, false, 0 },
606 { AArch64::LD4Rv8h, "ld4r", ".8h", 0, false, 0 },
607 { AArch64::LD4Rv4s, "ld4r", ".4s", 0, false, 0 },
608 { AArch64::LD4Rv2d, "ld4r", ".2d", 0, false, 0 },
609 { AArch64::LD4Rv8b, "ld4r", ".8b", 0, false, 0 },
610 { AArch64::LD4Rv4h, "ld4r", ".4h", 0, false, 0 },
611 { AArch64::LD4Rv2s, "ld4r", ".2s", 0, false, 0 },
612 { AArch64::LD4Rv1d, "ld4r", ".1d", 0, false, 0 },
613 { AArch64::LD4Rv16b_POST, "ld4r", ".16b", 1, false, 4 },
614 { AArch64::LD4Rv8h_POST, "ld4r", ".8h", 1, false, 8 },
615 { AArch64::LD4Rv4s_POST, "ld4r", ".4s", 1, false, 16 },
616 { AArch64::LD4Rv2d_POST, "ld4r", ".2d", 1, false, 32 },
617 { AArch64::LD4Rv8b_POST, "ld4r", ".8b", 1, false, 4 },
618 { AArch64::LD4Rv4h_POST, "ld4r", ".4h", 1, false, 8 },
619 { AArch64::LD4Rv2s_POST, "ld4r", ".2s", 1, false, 16 },
620 { AArch64::LD4Rv1d_POST, "ld4r", ".1d", 1, false, 32 },
621 { AArch64::LD4Fourv16b, "ld4", ".16b", 0, false, 0 },
622 { AArch64::LD4Fourv8h, "ld4", ".8h", 0, false, 0 },
623 { AArch64::LD4Fourv4s, "ld4", ".4s", 0, false, 0 },
624 { AArch64::LD4Fourv2d, "ld4", ".2d", 0, false, 0 },
625 { AArch64::LD4Fourv8b, "ld4", ".8b", 0, false, 0 },
626 { AArch64::LD4Fourv4h, "ld4", ".4h", 0, false, 0 },
627 { AArch64::LD4Fourv2s, "ld4", ".2s", 0, false, 0 },
628 { AArch64::LD4Fourv16b_POST, "ld4", ".16b", 1, false, 64 },
629 { AArch64::LD4Fourv8h_POST, "ld4", ".8h", 1, false, 64 },
630 { AArch64::LD4Fourv4s_POST, "ld4", ".4s", 1, false, 64 },
631 { AArch64::LD4Fourv2d_POST, "ld4", ".2d", 1, false, 64 },
632 { AArch64::LD4Fourv8b_POST, "ld4", ".8b", 1, false, 32 },
633 { AArch64::LD4Fourv4h_POST, "ld4", ".4h", 1, false, 32 },
634 { AArch64::LD4Fourv2s_POST, "ld4", ".2s", 1, false, 32 },
635 { AArch64::ST1i8, "st1", ".b", 0, true, 0 },
636 { AArch64::ST1i16, "st1", ".h", 0, true, 0 },
637 { AArch64::ST1i32, "st1", ".s", 0, true, 0 },
638 { AArch64::ST1i64, "st1", ".d", 0, true, 0 },
639 { AArch64::ST1i8_POST, "st1", ".b", 1, true, 1 },
640 { AArch64::ST1i16_POST, "st1", ".h", 1, true, 2 },
641 { AArch64::ST1i32_POST, "st1", ".s", 1, true, 4 },
642 { AArch64::ST1i64_POST, "st1", ".d", 1, true, 8 },
643 { AArch64::ST1Onev16b, "st1", ".16b", 0, false, 0 },
644 { AArch64::ST1Onev8h, "st1", ".8h", 0, false, 0 },
645 { AArch64::ST1Onev4s, "st1", ".4s", 0, false, 0 },
646 { AArch64::ST1Onev2d, "st1", ".2d", 0, false, 0 },
647 { AArch64::ST1Onev8b, "st1", ".8b", 0, false, 0 },
648 { AArch64::ST1Onev4h, "st1", ".4h", 0, false, 0 },
649 { AArch64::ST1Onev2s, "st1", ".2s", 0, false, 0 },
650 { AArch64::ST1Onev1d, "st1", ".1d", 0, false, 0 },
651 { AArch64::ST1Onev16b_POST, "st1", ".16b", 1, false, 16 },
652 { AArch64::ST1Onev8h_POST, "st1", ".8h", 1, false, 16 },
653 { AArch64::ST1Onev4s_POST, "st1", ".4s", 1, false, 16 },
654 { AArch64::ST1Onev2d_POST, "st1", ".2d", 1, false, 16 },
655 { AArch64::ST1Onev8b_POST, "st1", ".8b", 1, false, 8 },
656 { AArch64::ST1Onev4h_POST, "st1", ".4h", 1, false, 8 },
657 { AArch64::ST1Onev2s_POST, "st1", ".2s", 1, false, 8 },
658 { AArch64::ST1Onev1d_POST, "st1", ".1d", 1, false, 8 },
659 { AArch64::ST1Twov16b, "st1", ".16b", 0, false, 0 },
660 { AArch64::ST1Twov8h, "st1", ".8h", 0, false, 0 },
661 { AArch64::ST1Twov4s, "st1", ".4s", 0, false, 0 },
662 { AArch64::ST1Twov2d, "st1", ".2d", 0, false, 0 },
663 { AArch64::ST1Twov8b, "st1", ".8b", 0, false, 0 },
664 { AArch64::ST1Twov4h, "st1", ".4h", 0, false, 0 },
665 { AArch64::ST1Twov2s, "st1", ".2s", 0, false, 0 },
666 { AArch64::ST1Twov1d, "st1", ".1d", 0, false, 0 },
667 { AArch64::ST1Twov16b_POST, "st1", ".16b", 1, false, 32 },
668 { AArch64::ST1Twov8h_POST, "st1", ".8h", 1, false, 32 },
669 { AArch64::ST1Twov4s_POST, "st1", ".4s", 1, false, 32 },
670 { AArch64::ST1Twov2d_POST, "st1", ".2d", 1, false, 32 },
671 { AArch64::ST1Twov8b_POST, "st1", ".8b", 1, false, 16 },
672 { AArch64::ST1Twov4h_POST, "st1", ".4h", 1, false, 16 },
673 { AArch64::ST1Twov2s_POST, "st1", ".2s", 1, false, 16 },
674 { AArch64::ST1Twov1d_POST, "st1", ".1d", 1, false, 16 },
675 { AArch64::ST1Threev16b, "st1", ".16b", 0, false, 0 },
676 { AArch64::ST1Threev8h, "st1", ".8h", 0, false, 0 },
677 { AArch64::ST1Threev4s, "st1", ".4s", 0, false, 0 },
678 { AArch64::ST1Threev2d, "st1", ".2d", 0, false, 0 },
679 { AArch64::ST1Threev8b, "st1", ".8b", 0, false, 0 },
680 { AArch64::ST1Threev4h, "st1", ".4h", 0, false, 0 },
681 { AArch64::ST1Threev2s, "st1", ".2s", 0, false, 0 },
682 { AArch64::ST1Threev1d, "st1", ".1d", 0, false, 0 },
683 { AArch64::ST1Threev16b_POST, "st1", ".16b", 1, false, 48 },
684 { AArch64::ST1Threev8h_POST, "st1", ".8h", 1, false, 48 },
685 { AArch64::ST1Threev4s_POST, "st1", ".4s", 1, false, 48 },
686 { AArch64::ST1Threev2d_POST, "st1", ".2d", 1, false, 48 },
687 { AArch64::ST1Threev8b_POST, "st1", ".8b", 1, false, 24 },
688 { AArch64::ST1Threev4h_POST, "st1", ".4h", 1, false, 24 },
689 { AArch64::ST1Threev2s_POST, "st1", ".2s", 1, false, 24 },
690 { AArch64::ST1Threev1d_POST, "st1", ".1d", 1, false, 24 },
691 { AArch64::ST1Fourv16b, "st1", ".16b", 0, false, 0 },
692 { AArch64::ST1Fourv8h, "st1", ".8h", 0, false, 0 },
693 { AArch64::ST1Fourv4s, "st1", ".4s", 0, false, 0 },
694 { AArch64::ST1Fourv2d, "st1", ".2d", 0, false, 0 },
695 { AArch64::ST1Fourv8b, "st1", ".8b", 0, false, 0 },
696 { AArch64::ST1Fourv4h, "st1", ".4h", 0, false, 0 },
697 { AArch64::ST1Fourv2s, "st1", ".2s", 0, false, 0 },
698 { AArch64::ST1Fourv1d, "st1", ".1d", 0, false, 0 },
699 { AArch64::ST1Fourv16b_POST, "st1", ".16b", 1, false, 64 },
700 { AArch64::ST1Fourv8h_POST, "st1", ".8h", 1, false, 64 },
701 { AArch64::ST1Fourv4s_POST, "st1", ".4s", 1, false, 64 },
702 { AArch64::ST1Fourv2d_POST, "st1", ".2d", 1, false, 64 },
703 { AArch64::ST1Fourv8b_POST, "st1", ".8b", 1, false, 32 },
704 { AArch64::ST1Fourv4h_POST, "st1", ".4h", 1, false, 32 },
705 { AArch64::ST1Fourv2s_POST, "st1", ".2s", 1, false, 32 },
706 { AArch64::ST1Fourv1d_POST, "st1", ".1d", 1, false, 32 },
707 { AArch64::ST2i8, "st2", ".b", 0, true, 0 },
708 { AArch64::ST2i16, "st2", ".h", 0, true, 0 },
709 { AArch64::ST2i32, "st2", ".s", 0, true, 0 },
710 { AArch64::ST2i64, "st2", ".d", 0, true, 0 },
711 { AArch64::ST2i8_POST, "st2", ".b", 1, true, 2 },
712 { AArch64::ST2i16_POST, "st2", ".h", 1, true, 4 },
713 { AArch64::ST2i32_POST, "st2", ".s", 1, true, 8 },
714 { AArch64::ST2i64_POST, "st2", ".d", 1, true, 16 },
715 { AArch64::ST2Twov16b, "st2", ".16b", 0, false, 0 },
716 { AArch64::ST2Twov8h, "st2", ".8h", 0, false, 0 },
717 { AArch64::ST2Twov4s, "st2", ".4s", 0, false, 0 },
718 { AArch64::ST2Twov2d, "st2", ".2d", 0, false, 0 },
719 { AArch64::ST2Twov8b, "st2", ".8b", 0, false, 0 },
720 { AArch64::ST2Twov4h, "st2", ".4h", 0, false, 0 },
721 { AArch64::ST2Twov2s, "st2", ".2s", 0, false, 0 },
722 { AArch64::ST2Twov16b_POST, "st2", ".16b", 1, false, 32 },
723 { AArch64::ST2Twov8h_POST, "st2", ".8h", 1, false, 32 },
724 { AArch64::ST2Twov4s_POST, "st2", ".4s", 1, false, 32 },
725 { AArch64::ST2Twov2d_POST, "st2", ".2d", 1, false, 32 },
726 { AArch64::ST2Twov8b_POST, "st2", ".8b", 1, false, 16 },
727 { AArch64::ST2Twov4h_POST, "st2", ".4h", 1, false, 16 },
728 { AArch64::ST2Twov2s_POST, "st2", ".2s", 1, false, 16 },
729 { AArch64::ST3i8, "st3", ".b", 0, true, 0 },
730 { AArch64::ST3i16, "st3", ".h", 0, true, 0 },
731 { AArch64::ST3i32, "st3", ".s", 0, true, 0 },
732 { AArch64::ST3i64, "st3", ".d", 0, true, 0 },
733 { AArch64::ST3i8_POST, "st3", ".b", 1, true, 3 },
734 { AArch64::ST3i16_POST, "st3", ".h", 1, true, 6 },
735 { AArch64::ST3i32_POST, "st3", ".s", 1, true, 12 },
736 { AArch64::ST3i64_POST, "st3", ".d", 1, true, 24 },
737 { AArch64::ST3Threev16b, "st3", ".16b", 0, false, 0 },
738 { AArch64::ST3Threev8h, "st3", ".8h", 0, false, 0 },
739 { AArch64::ST3Threev4s, "st3", ".4s", 0, false, 0 },
740 { AArch64::ST3Threev2d, "st3", ".2d", 0, false, 0 },
741 { AArch64::ST3Threev8b, "st3", ".8b", 0, false, 0 },
742 { AArch64::ST3Threev4h, "st3", ".4h", 0, false, 0 },
743 { AArch64::ST3Threev2s, "st3", ".2s", 0, false, 0 },
744 { AArch64::ST3Threev16b_POST, "st3", ".16b", 1, false, 48 },
745 { AArch64::ST3Threev8h_POST, "st3", ".8h", 1, false, 48 },
746 { AArch64::ST3Threev4s_POST, "st3", ".4s", 1, false, 48 },
747 { AArch64::ST3Threev2d_POST, "st3", ".2d", 1, false, 48 },
748 { AArch64::ST3Threev8b_POST, "st3", ".8b", 1, false, 24 },
749 { AArch64::ST3Threev4h_POST, "st3", ".4h", 1, false, 24 },
750 { AArch64::ST3Threev2s_POST, "st3", ".2s", 1, false, 24 },
751 { AArch64::ST4i8, "st4", ".b", 0, true, 0 },
752 { AArch64::ST4i16, "st4", ".h", 0, true, 0 },
753 { AArch64::ST4i32, "st4", ".s", 0, true, 0 },
754 { AArch64::ST4i64, "st4", ".d", 0, true, 0 },
755 { AArch64::ST4i8_POST, "st4", ".b", 1, true, 4 },
756 { AArch64::ST4i16_POST, "st4", ".h", 1, true, 8 },
757 { AArch64::ST4i32_POST, "st4", ".s", 1, true, 16 },
758 { AArch64::ST4i64_POST, "st4", ".d", 1, true, 32 },
759 { AArch64::ST4Fourv16b, "st4", ".16b", 0, false, 0 },
760 { AArch64::ST4Fourv8h, "st4", ".8h", 0, false, 0 },
761 { AArch64::ST4Fourv4s, "st4", ".4s", 0, false, 0 },
762 { AArch64::ST4Fourv2d, "st4", ".2d", 0, false, 0 },
763 { AArch64::ST4Fourv8b, "st4", ".8b", 0, false, 0 },
764 { AArch64::ST4Fourv4h, "st4", ".4h", 0, false, 0 },
765 { AArch64::ST4Fourv2s, "st4", ".2s", 0, false, 0 },
766 { AArch64::ST4Fourv16b_POST, "st4", ".16b", 1, false, 64 },
767 { AArch64::ST4Fourv8h_POST, "st4", ".8h", 1, false, 64 },
768 { AArch64::ST4Fourv4s_POST, "st4", ".4s", 1, false, 64 },
769 { AArch64::ST4Fourv2d_POST, "st4", ".2d", 1, false, 64 },
770 { AArch64::ST4Fourv8b_POST, "st4", ".8b", 1, false, 32 },
771 { AArch64::ST4Fourv4h_POST, "st4", ".4h", 1, false, 32 },
772 { AArch64::ST4Fourv2s_POST, "st4", ".2s", 1, false, 32 },
773};
774
775static const LdStNInstrDesc *getLdStNInstrDesc(unsigned Opcode) {
776 for (const auto &Info : LdStNInstInfo)
777 if (Info.Opcode == Opcode)
778 return &Info;
779
780 return nullptr;
781}
782
783void AArch64AppleInstPrinter::printInst(const MCInst *MI, uint64_t Address,
784 StringRef Annot,
785 const MCSubtargetInfo &STI,
786 raw_ostream &O) {
787 unsigned Opcode = MI->getOpcode();
788 StringRef Layout;
789
790 bool IsTbx;
791 if (isTblTbxInstruction(MI->getOpcode(), Layout, IsTbx)) {
792 O << "\t" << (IsTbx ? "tbx" : "tbl") << Layout << '\t';
793 printRegName(O, MI->getOperand(0).getReg(), AArch64::vreg);
794 O << ", ";
795
796 unsigned ListOpNum = IsTbx ? 2 : 1;
797 printVectorList(MI, ListOpNum, STI, O, "");
798
799 O << ", ";
800 printRegName(O, MI->getOperand(ListOpNum + 1).getReg(), AArch64::vreg);
801 printAnnotation(O, Annot);
802 return;
803 }
804
805 if (const LdStNInstrDesc *LdStDesc = getLdStNInstrDesc(Opcode)) {
806 O << "\t" << LdStDesc->Mnemonic << LdStDesc->Layout << '\t';
807
808 // Now onto the operands: first a vector list with possible lane
809 // specifier. E.g. { v0 }[2]
810 int OpNum = LdStDesc->ListOperand;
811 printVectorList(MI, OpNum++, STI, O, "");
812
813 if (LdStDesc->HasLane)
814 O << '[' << MI->getOperand(OpNum++).getImm() << ']';
815
816 // Next the address: [xN]
817 MCRegister AddrReg = MI->getOperand(OpNum++).getReg();
818 O << ", [";
819 printRegName(O, AddrReg);
820 O << ']';
821
822 // Finally, there might be a post-indexed offset.
823 if (LdStDesc->NaturalOffset != 0) {
824 MCRegister Reg = MI->getOperand(OpNum++).getReg();
825 if (Reg != AArch64::XZR) {
826 O << ", ";
827 printRegName(O, Reg);
828 } else {
829 assert(LdStDesc->NaturalOffset && "no offset on post-inc instruction?");
830 O << ", ";
831 markup(O, Markup::Immediate) << "#" << LdStDesc->NaturalOffset;
832 }
833 }
834
835 printAnnotation(O, Annot);
836 return;
837 }
838
839 AArch64InstPrinter::printInst(MI, Address, Annot, STI, O);
840}
841
842StringRef AArch64AppleInstPrinter::getRegName(MCRegister Reg) const {
843 return getRegisterName(Reg);
844}
845
846bool AArch64InstPrinter::printRangePrefetchAlias(const MCInst *MI,
847 const MCSubtargetInfo &STI,
848 raw_ostream &O,
849 StringRef Annot) {
850 unsigned Opcode = MI->getOpcode();
851
852#ifndef NDEBUG
853 assert(((Opcode == AArch64::PRFMroX) || (Opcode == AArch64::PRFMroW)) &&
854 "Invalid opcode for RPRFM alias!");
855#endif
856
857 unsigned PRFOp = MI->getOperand(0).getImm();
858 unsigned Mask = 0x18; // 0b11000
859 if ((PRFOp & Mask) != Mask)
860 return false; // Rt != '11xxx', it's a PRFM instruction.
861
862 MCRegister Rm = MI->getOperand(2).getReg();
863
864 // "Rm" must be a 64-bit GPR for RPRFM.
865 if (MRI.getRegClass(AArch64::GPR32RegClassID).contains(Rm))
866 Rm = MRI.getMatchingSuperReg(Rm, AArch64::sub_32,
867 &MRI.getRegClass(AArch64::GPR64RegClassID));
868
869 unsigned SignExtend = MI->getOperand(3).getImm(); // encoded in "option<2>".
870 unsigned Shift = MI->getOperand(4).getImm(); // encoded in "S".
871
872 assert((SignExtend <= 1) && "sign extend should be a single bit!");
873 assert((Shift <= 1) && "Shift should be a single bit!");
874
875 unsigned Option0 = (Opcode == AArch64::PRFMroX) ? 1 : 0;
876
877 // encoded in "option<2>:option<0>:S:Rt<2:0>".
878 unsigned RPRFOp =
879 (SignExtend << 5) | (Option0 << 4) | (Shift << 3) | (PRFOp & 0x7);
880
881 O << "\trprfm ";
882 if (auto RPRFM = AArch64RPRFM::lookupRPRFMByEncoding(RPRFOp))
883 O << RPRFM->Name << ", ";
884 else
885 O << "#" << formatImm(RPRFOp) << ", ";
886 O << getRegisterName(Rm);
887 O << ", [";
888 printOperand(MI, 1, STI, O); // "Rn".
889 O << "]";
890
891 printAnnotation(O, Annot);
892
893 return true;
894}
895
896bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
897 const MCSubtargetInfo &STI,
898 raw_ostream &O) {
899#ifndef NDEBUG
900 unsigned Opcode = MI->getOpcode();
901 assert(Opcode == AArch64::SYSxt && "Invalid opcode for SYS alias!");
902#endif
903
904 const MCOperand &Op1 = MI->getOperand(0);
905 const MCOperand &Cn = MI->getOperand(1);
906 const MCOperand &Cm = MI->getOperand(2);
907 const MCOperand &Op2 = MI->getOperand(3);
908
909 unsigned Op1Val = Op1.getImm();
910 unsigned CnVal = Cn.getImm();
911 unsigned CmVal = Cm.getImm();
912 unsigned Op2Val = Op2.getImm();
913
914 uint16_t Encoding = Op2Val;
915 Encoding |= CmVal << 3;
916 Encoding |= CnVal << 7;
917 Encoding |= Op1Val << 11;
918
919 bool NeedsReg;
920 std::string Ins;
921 std::string Name;
922
923 if (CnVal == 7) {
924 switch (CmVal) {
925 default: return false;
926 // Maybe IC, maybe Prediction Restriction
927 case 1:
928 switch (Op1Val) {
929 default: return false;
930 case 0: goto Search_IC;
931 case 3: goto Search_PRCTX;
932 }
933 // Prediction Restriction aliases
934 case 3: {
935 Search_PRCTX:
936 if (Op1Val != 3 || CnVal != 7 || CmVal != 3)
937 return false;
938
939 const auto Requires =
940 Op2Val == 6 ? AArch64::FeatureSPECRES2 : AArch64::FeaturePredRes;
941 if (!(STI.hasFeature(AArch64::FeatureAll) || STI.hasFeature(Requires)))
942 return false;
943
944 NeedsReg = true;
945 switch (Op2Val) {
946 default: return false;
947 case 4: Ins = "cfp\t"; break;
948 case 5: Ins = "dvp\t"; break;
949 case 6: Ins = "cosp\t"; break;
950 case 7: Ins = "cpp\t"; break;
951 }
952 Name = "RCTX";
953 }
954 break;
955 // IC aliases
956 case 5: {
957 Search_IC:
958 const AArch64IC::IC *IC = AArch64IC::lookupICByEncoding(Encoding);
959 if (!IC || !IC->haveFeatures(STI.getFeatureBits()))
960 return false;
961
962 NeedsReg = IC->NeedsReg;
963 Ins = "ic\t";
964 Name = std::string(IC->Name);
965 }
966 break;
967 // DC aliases
968 case 4: case 6: case 10: case 11: case 12: case 13: case 14:
969 {
970 const AArch64DC::DC *DC = AArch64DC::lookupDCByEncoding(Encoding);
971 if (!DC || !DC->haveFeatures(STI.getFeatureBits()))
972 return false;
973
974 NeedsReg = true;
975 Ins = "dc\t";
976 Name = std::string(DC->Name);
977 }
978 break;
979 // AT aliases
980 case 8: case 9: {
981 const AArch64AT::AT *AT = AArch64AT::lookupATByEncoding(Encoding);
982 if (!AT || !AT->haveFeatures(STI.getFeatureBits()))
983 return false;
984
985 NeedsReg = true;
986 Ins = "at\t";
987 Name = std::string(AT->Name);
988 }
989 break;
990 // Overlaps with AT and DC
991 case 15: {
992 const AArch64AT::AT *AT = AArch64AT::lookupATByEncoding(Encoding);
993 const AArch64DC::DC *DC = AArch64DC::lookupDCByEncoding(Encoding);
994 if (AT && AT->haveFeatures(STI.getFeatureBits())) {
995 NeedsReg = true;
996 Ins = "at\t";
997 Name = std::string(AT->Name);
998 } else if (DC && DC->haveFeatures(STI.getFeatureBits())) {
999 NeedsReg = true;
1000 Ins = "dc\t";
1001 Name = std::string(DC->Name);
1002 } else {
1003 return false;
1004 }
1005 } break;
1006 }
1007 } else if (CnVal == 8 || CnVal == 9) {
1008 // TLBI aliases
1009 const AArch64TLBI::TLBI *TLBI = AArch64TLBI::lookupTLBIByEncoding(Encoding);
1010 if (!TLBI || !TLBI->haveFeatures(STI.getFeatureBits()))
1011 return false;
1012
1013 NeedsReg = TLBI->NeedsReg;
1014 Ins = "tlbi\t";
1015 Name = std::string(TLBI->Name);
1016 }
1017 else
1018 return false;
1019
1020 StringRef Reg = getRegisterName(MI->getOperand(4).getReg());
1021 bool NotXZR = Reg != "xzr";
1022
1023 // If a mandatory is not specified in the TableGen
1024 // (i.e. no register operand should be present), and the register value
1025 // is not xzr/x31, then disassemble to a SYS alias instead.
1026 if (NotXZR && !NeedsReg)
1027 return false;
1028
1029 std::string Str = Ins + Name;
1030 llvm::transform(Str, Str.begin(), ::tolower);
1031
1032 O << '\t' << Str;
1033
1034 if (NeedsReg)
1035 O << ", " << Reg;
1036
1037 return true;
1038}
1039
1040bool AArch64InstPrinter::printSyspAlias(const MCInst *MI,
1041 const MCSubtargetInfo &STI,
1042 raw_ostream &O) {
1043#ifndef NDEBUG
1044 unsigned Opcode = MI->getOpcode();
1045 assert((Opcode == AArch64::SYSPxt || Opcode == AArch64::SYSPxt_XZR) &&
1046 "Invalid opcode for SYSP alias!");
1047#endif
1048
1049 const MCOperand &Op1 = MI->getOperand(0);
1050 const MCOperand &Cn = MI->getOperand(1);
1051 const MCOperand &Cm = MI->getOperand(2);
1052 const MCOperand &Op2 = MI->getOperand(3);
1053
1054 unsigned Op1Val = Op1.getImm();
1055 unsigned CnVal = Cn.getImm();
1056 unsigned CmVal = Cm.getImm();
1057 unsigned Op2Val = Op2.getImm();
1058
1059 uint16_t Encoding = Op2Val;
1060 Encoding |= CmVal << 3;
1061 Encoding |= CnVal << 7;
1062 Encoding |= Op1Val << 11;
1063
1064 std::string Ins;
1065 std::string Name;
1066
1067 if (CnVal == 8 || CnVal == 9) {
1068 // TLBIP aliases
1069
1070 if (CnVal == 9) {
1071 if (!STI.hasFeature(AArch64::FeatureXS))
1072 return false;
1073 Encoding &= ~(1 << 7);
1074 }
1075
1076 const AArch64TLBI::TLBI *TLBI = AArch64TLBI::lookupTLBIByEncoding(Encoding);
1077 if (!TLBI || !TLBI->haveFeatures(STI.getFeatureBits()))
1078 return false;
1079
1080 Ins = "tlbip\t";
1081 Name = std::string(TLBI->Name);
1082 if (CnVal == 9)
1083 Name += "nXS";
1084 } else
1085 return false;
1086
1087 std::string Str = Ins + Name;
1088 llvm::transform(Str, Str.begin(), ::tolower);
1089
1090 O << '\t' << Str;
1091 O << ", ";
1092 if (MI->getOperand(4).getReg() == AArch64::XZR)
1093 printSyspXzrPair(MI, 4, STI, O);
1094 else
1095 printGPRSeqPairsClassOperand<64>(MI, 4, STI, O);
1096
1097 return true;
1098}
1099
1100template <int EltSize>
1101void AArch64InstPrinter::printMatrix(const MCInst *MI, unsigned OpNum,
1102 const MCSubtargetInfo &STI,
1103 raw_ostream &O) {
1104 const MCOperand &RegOp = MI->getOperand(OpNum);
1105 assert(RegOp.isReg() && "Unexpected operand type!");
1106
1107 printRegName(O, RegOp.getReg());
1108 switch (EltSize) {
1109 case 0:
1110 break;
1111 case 8:
1112 O << ".b";
1113 break;
1114 case 16:
1115 O << ".h";
1116 break;
1117 case 32:
1118 O << ".s";
1119 break;
1120 case 64:
1121 O << ".d";
1122 break;
1123 case 128:
1124 O << ".q";
1125 break;
1126 default:
1127 llvm_unreachable("Unsupported element size");
1128 }
1129}
1130
1131template <bool IsVertical>
1132void AArch64InstPrinter::printMatrixTileVector(const MCInst *MI, unsigned OpNum,
1133 const MCSubtargetInfo &STI,
1134 raw_ostream &O) {
1135 const MCOperand &RegOp = MI->getOperand(OpNum);
1136 assert(RegOp.isReg() && "Unexpected operand type!");
1137 StringRef RegName = getRegisterName(RegOp.getReg());
1138
1139 // Insert the horizontal/vertical flag before the suffix.
1140 StringRef Base, Suffix;
1141 std::tie(Base, Suffix) = RegName.split('.');
1142 O << Base << (IsVertical ? "v" : "h") << '.' << Suffix;
1143}
1144
1145void AArch64InstPrinter::printMatrixTile(const MCInst *MI, unsigned OpNum,
1146 const MCSubtargetInfo &STI,
1147 raw_ostream &O) {
1148 const MCOperand &RegOp = MI->getOperand(OpNum);
1149 assert(RegOp.isReg() && "Unexpected operand type!");
1150 printRegName(O, RegOp.getReg());
1151}
1152
1153void AArch64InstPrinter::printSVCROp(const MCInst *MI, unsigned OpNum,
1154 const MCSubtargetInfo &STI,
1155 raw_ostream &O) {
1156 const MCOperand &MO = MI->getOperand(OpNum);
1157 assert(MO.isImm() && "Unexpected operand type!");
1158 unsigned svcrop = MO.getImm();
1159 const auto *SVCR = AArch64SVCR::lookupSVCRByEncoding(svcrop);
1160 assert(SVCR && "Unexpected SVCR operand!");
1161 O << SVCR->Name;
1162}
1163
1164void AArch64InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
1165 const MCSubtargetInfo &STI,
1166 raw_ostream &O) {
1167 const MCOperand &Op = MI->getOperand(OpNo);
1168 if (Op.isReg()) {
1169 printRegName(O, Op.getReg());
1170 } else if (Op.isImm()) {
1171 printImm(MI, OpNo, STI, O);
1172 } else {
1173 assert(Op.isExpr() && "unknown operand kind in printOperand");
1174 MAI.printExpr(O, *Op.getExpr());
1175 }
1176}
1177
1178void AArch64InstPrinter::printImm(const MCInst *MI, unsigned OpNo,
1179 const MCSubtargetInfo &STI,
1180 raw_ostream &O) {
1181 const MCOperand &Op = MI->getOperand(OpNo);
1182 markup(O, Markup::Immediate) << "#" << formatImm(Op.getImm());
1183}
1184
1185void AArch64InstPrinter::printImmHex(const MCInst *MI, unsigned OpNo,
1186 const MCSubtargetInfo &STI,
1187 raw_ostream &O) {
1188 const MCOperand &Op = MI->getOperand(OpNo);
1189 markup(O, Markup::Immediate) << format("#%#llx", Op.getImm());
1190}
1191
1192template<int Size>
1193void AArch64InstPrinter::printSImm(const MCInst *MI, unsigned OpNo,
1194 const MCSubtargetInfo &STI,
1195 raw_ostream &O) {
1196 const MCOperand &Op = MI->getOperand(OpNo);
1197 if (Size == 8)
1198 markup(O, Markup::Immediate) << "#" << formatImm((signed char)Op.getImm());
1199 else if (Size == 16)
1200 markup(O, Markup::Immediate) << "#" << formatImm((signed short)Op.getImm());
1201 else
1202 markup(O, Markup::Immediate) << "#" << formatImm(Op.getImm());
1203}
1204
1205void AArch64InstPrinter::printPostIncOperand(const MCInst *MI, unsigned OpNo,
1206 unsigned Imm, raw_ostream &O) {
1207 const MCOperand &Op = MI->getOperand(OpNo);
1208 if (Op.isReg()) {
1209 MCRegister Reg = Op.getReg();
1210 if (Reg == AArch64::XZR)
1211 markup(O, Markup::Immediate) << "#" << Imm;
1212 else
1213 printRegName(O, Reg);
1214 } else
1215 llvm_unreachable("unknown operand kind in printPostIncOperand64");
1216}
1217
1218void AArch64InstPrinter::printVRegOperand(const MCInst *MI, unsigned OpNo,
1219 const MCSubtargetInfo &STI,
1220 raw_ostream &O) {
1221 const MCOperand &Op = MI->getOperand(OpNo);
1222 assert(Op.isReg() && "Non-register vreg operand!");
1223 printRegName(O, Op.getReg(), AArch64::vreg);
1224}
1225
1226void AArch64InstPrinter::printSysCROperand(const MCInst *MI, unsigned OpNo,
1227 const MCSubtargetInfo &STI,
1228 raw_ostream &O) {
1229 const MCOperand &Op = MI->getOperand(OpNo);
1230 assert(Op.isImm() && "System instruction C[nm] operands must be immediates!");
1231 O << "c" << Op.getImm();
1232}
1233
1234void AArch64InstPrinter::printAddSubImm(const MCInst *MI, unsigned OpNum,
1235 const MCSubtargetInfo &STI,
1236 raw_ostream &O) {
1237 const MCOperand &MO = MI->getOperand(OpNum);
1238 if (MO.isImm()) {
1239 unsigned Val = (MO.getImm() & 0xfff);
1240 assert(Val == MO.getImm() && "Add/sub immediate out of range!");
1241 unsigned Shift =
1242 AArch64_AM::getShiftValue(MI->getOperand(OpNum + 1).getImm());
1243 markup(O, Markup::Immediate) << '#' << formatImm(Val);
1244 if (Shift != 0) {
1245 printShifter(MI, OpNum + 1, STI, O);
1246 if (CommentStream)
1247 *CommentStream << '=' << formatImm(Val << Shift) << '\n';
1248 }
1249 } else {
1250 assert(MO.isExpr() && "Unexpected operand type!");
1251 MAI.printExpr(O, *MO.getExpr());
1252 printShifter(MI, OpNum + 1, STI, O);
1253 }
1254}
1255
1256template <typename T>
1257void AArch64InstPrinter::printLogicalImm(const MCInst *MI, unsigned OpNum,
1258 const MCSubtargetInfo &STI,
1259 raw_ostream &O) {
1260 uint64_t Val = MI->getOperand(OpNum).getImm();
1261 WithMarkup M = markup(O, Markup::Immediate);
1262 O << "#0x";
1263 O.write_hex(AArch64_AM::decodeLogicalImmediate(Val, 8 * sizeof(T)));
1264}
1265
1266void AArch64InstPrinter::printShifter(const MCInst *MI, unsigned OpNum,
1267 const MCSubtargetInfo &STI,
1268 raw_ostream &O) {
1269 unsigned Val = MI->getOperand(OpNum).getImm();
1270 // LSL #0 should not be printed.
1271 if (AArch64_AM::getShiftType(Val) == AArch64_AM::LSL &&
1272 AArch64_AM::getShiftValue(Val) == 0)
1273 return;
1274 O << ", " << AArch64_AM::getShiftExtendName(AArch64_AM::getShiftType(Val))
1275 << " ";
1276 markup(O, Markup::Immediate) << "#" << AArch64_AM::getShiftValue(Val);
1277}
1278
1279void AArch64InstPrinter::printShiftedRegister(const MCInst *MI, unsigned OpNum,
1280 const MCSubtargetInfo &STI,
1281 raw_ostream &O) {
1282 printRegName(O, MI->getOperand(OpNum).getReg());
1283 printShifter(MI, OpNum + 1, STI, O);
1284}
1285
1286void AArch64InstPrinter::printExtendedRegister(const MCInst *MI, unsigned OpNum,
1287 const MCSubtargetInfo &STI,
1288 raw_ostream &O) {
1289 printRegName(O, MI->getOperand(OpNum).getReg());
1290 printArithExtend(MI, OpNum + 1, STI, O);
1291}
1292
1293void AArch64InstPrinter::printArithExtend(const MCInst *MI, unsigned OpNum,
1294 const MCSubtargetInfo &STI,
1295 raw_ostream &O) {
1296 unsigned Val = MI->getOperand(OpNum).getImm();
1297 AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getArithExtendType(Val);
1298 unsigned ShiftVal = AArch64_AM::getArithShiftValue(Val);
1299
1300 // If the destination or first source register operand is [W]SP, print
1301 // UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing at
1302 // all.
1303 if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) {
1304 MCRegister Dest = MI->getOperand(0).getReg();
1305 MCRegister Src1 = MI->getOperand(1).getReg();
1306 if ( ((Dest == AArch64::SP || Src1 == AArch64::SP) &&
1307 ExtType == AArch64_AM::UXTX) ||
1308 ((Dest == AArch64::WSP || Src1 == AArch64::WSP) &&
1309 ExtType == AArch64_AM::UXTW) ) {
1310 if (ShiftVal != 0) {
1311 O << ", lsl ";
1312 markup(O, Markup::Immediate) << "#" << ShiftVal;
1313 }
1314 return;
1315 }
1316 }
1317 O << ", " << AArch64_AM::getShiftExtendName(ExtType);
1318 if (ShiftVal != 0) {
1319 O << " ";
1320 markup(O, Markup::Immediate) << "#" << ShiftVal;
1321 }
1322}
1323
1324void AArch64InstPrinter::printMemExtendImpl(bool SignExtend, bool DoShift,
1325 unsigned Width, char SrcRegKind,
1326 raw_ostream &O) {
1327 // sxtw, sxtx, uxtw or lsl (== uxtx)
1328 bool IsLSL = !SignExtend && SrcRegKind == 'x';
1329 if (IsLSL)
1330 O << "lsl";
1331 else
1332 O << (SignExtend ? 's' : 'u') << "xt" << SrcRegKind;
1333
1334 if (DoShift || IsLSL) {
1335 O << " ";
1336 markup(O, Markup::Immediate) << "#" << Log2_32(Width / 8);
1337 }
1338}
1339
1340void AArch64InstPrinter::printMemExtend(const MCInst *MI, unsigned OpNum,
1341 raw_ostream &O, char SrcRegKind,
1342 unsigned Width) {
1343 bool SignExtend = MI->getOperand(OpNum).getImm();
1344 bool DoShift = MI->getOperand(OpNum + 1).getImm();
1345 printMemExtendImpl(SignExtend, DoShift, Width, SrcRegKind, O);
1346}
1347
1348template <bool SignExtend, int ExtWidth, char SrcRegKind, char Suffix>
1349void AArch64InstPrinter::printRegWithShiftExtend(const MCInst *MI,
1350 unsigned OpNum,
1351 const MCSubtargetInfo &STI,
1352 raw_ostream &O) {
1353 printOperand(MI, OpNum, STI, O);
1354 if (Suffix == 's' || Suffix == 'd')
1355 O << '.' << Suffix;
1356 else
1357 assert(Suffix == 0 && "Unsupported suffix size");
1358
1359 bool DoShift = ExtWidth != 8;
1360 if (SignExtend || DoShift || SrcRegKind == 'w') {
1361 O << ", ";
1362 printMemExtendImpl(SignExtend, DoShift, ExtWidth, SrcRegKind, O);
1363 }
1364}
1365
1366template <int EltSize>
1367void AArch64InstPrinter::printPredicateAsCounter(const MCInst *MI,
1368 unsigned OpNum,
1369 const MCSubtargetInfo &STI,
1370 raw_ostream &O) {
1371 MCRegister Reg = MI->getOperand(OpNum).getReg();
1372 if (Reg < AArch64::PN0 || Reg > AArch64::PN15)
1373 llvm_unreachable("Unsupported predicate-as-counter register");
1374 O << "pn" << Reg - AArch64::PN0;
1375
1376 switch (EltSize) {
1377 case 0:
1378 break;
1379 case 8:
1380 O << ".b";
1381 break;
1382 case 16:
1383 O << ".h";
1384 break;
1385 case 32:
1386 O << ".s";
1387 break;
1388 case 64:
1389 O << ".d";
1390 break;
1391 default:
1392 llvm_unreachable("Unsupported element size");
1393 }
1394}
1395
1396void AArch64InstPrinter::printCondCode(const MCInst *MI, unsigned OpNum,
1397 const MCSubtargetInfo &STI,
1398 raw_ostream &O) {
1399 AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm();
1400 O << AArch64CC::getCondCodeName(CC);
1401}
1402
1403void AArch64InstPrinter::printInverseCondCode(const MCInst *MI, unsigned OpNum,
1404 const MCSubtargetInfo &STI,
1405 raw_ostream &O) {
1406 AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm();
1407 O << AArch64CC::getCondCodeName(AArch64CC::getInvertedCondCode(CC));
1408}
1409
1410void AArch64InstPrinter::printAMNoIndex(const MCInst *MI, unsigned OpNum,
1411 const MCSubtargetInfo &STI,
1412 raw_ostream &O) {
1413 O << '[';
1414 printRegName(O, MI->getOperand(OpNum).getReg());
1415 O << ']';
1416}
1417
1418template <int Scale>
1419void AArch64InstPrinter::printImmScale(const MCInst *MI, unsigned OpNum,
1420 const MCSubtargetInfo &STI,
1421 raw_ostream &O) {
1422 markup(O, Markup::Immediate)
1423 << '#' << formatImm(Scale * MI->getOperand(OpNum).getImm());
1424}
1425
1426template <int Scale, int Offset>
1427void AArch64InstPrinter::printImmRangeScale(const MCInst *MI, unsigned OpNum,
1428 const MCSubtargetInfo &STI,
1429 raw_ostream &O) {
1430 unsigned FirstImm = Scale * MI->getOperand(OpNum).getImm();
1431 O << formatImm(FirstImm);
1432 O << ":" << formatImm(FirstImm + Offset);
1433}
1434
1435void AArch64InstPrinter::printUImm12Offset(const MCInst *MI, unsigned OpNum,
1436 unsigned Scale, raw_ostream &O) {
1437 const MCOperand MO = MI->getOperand(OpNum);
1438 if (MO.isImm()) {
1439 markup(O, Markup::Immediate) << '#' << formatImm(MO.getImm() * Scale);
1440 } else {
1441 assert(MO.isExpr() && "Unexpected operand type!");
1442 MAI.printExpr(O, *MO.getExpr());
1443 }
1444}
1445
1446void AArch64InstPrinter::printAMIndexedWB(const MCInst *MI, unsigned OpNum,
1447 unsigned Scale, raw_ostream &O) {
1448 const MCOperand MO1 = MI->getOperand(OpNum + 1);
1449 O << '[';
1450 printRegName(O, MI->getOperand(OpNum).getReg());
1451 if (MO1.isImm()) {
1452 O << ", ";
1453 markup(O, Markup::Immediate) << "#" << formatImm(MO1.getImm() * Scale);
1454 } else {
1455 assert(MO1.isExpr() && "Unexpected operand type!");
1456 O << ", ";
1457 MAI.printExpr(O, *MO1.getExpr());
1458 }
1459 O << ']';
1460}
1461
1462void AArch64InstPrinter::printRPRFMOperand(const MCInst *MI, unsigned OpNum,
1463 const MCSubtargetInfo &STI,
1464 raw_ostream &O) {
1465 unsigned prfop = MI->getOperand(OpNum).getImm();
1466 if (auto PRFM = AArch64RPRFM::lookupRPRFMByEncoding(prfop)) {
1467 O << PRFM->Name;
1468 return;
1469 }
1470
1471 O << '#' << formatImm(prfop);
1472}
1473
1474template <bool IsSVEPrefetch>
1475void AArch64InstPrinter::printPrefetchOp(const MCInst *MI, unsigned OpNum,
1476 const MCSubtargetInfo &STI,
1477 raw_ostream &O) {
1478 unsigned prfop = MI->getOperand(OpNum).getImm();
1479 if (IsSVEPrefetch) {
1480 if (auto PRFM = AArch64SVEPRFM::lookupSVEPRFMByEncoding(prfop)) {
1481 O << PRFM->Name;
1482 return;
1483 }
1484 } else {
1485 auto PRFM = AArch64PRFM::lookupPRFMByEncoding(prfop);
1486 if (PRFM && PRFM->haveFeatures(STI.getFeatureBits())) {
1487 O << PRFM->Name;
1488 return;
1489 }
1490 }
1491
1492 markup(O, Markup::Immediate) << '#' << formatImm(prfop);
1493}
1494
1495void AArch64InstPrinter::printPSBHintOp(const MCInst *MI, unsigned OpNum,
1496 const MCSubtargetInfo &STI,
1497 raw_ostream &O) {
1498 unsigned psbhintop = MI->getOperand(OpNum).getImm();
1499 auto PSB = AArch64PSBHint::lookupPSBByEncoding(psbhintop);
1500 if (PSB)
1501 O << PSB->Name;
1502 else
1503 markup(O, Markup::Immediate) << '#' << formatImm(psbhintop);
1504}
1505
1506void AArch64InstPrinter::printBTIHintOp(const MCInst *MI, unsigned OpNum,
1507 const MCSubtargetInfo &STI,
1508 raw_ostream &O) {
1509 unsigned btihintop = MI->getOperand(OpNum).getImm() ^ 32;
1510 auto BTI = AArch64BTIHint::lookupBTIByEncoding(btihintop);
1511 if (BTI)
1512 O << BTI->Name;
1513 else
1514 markup(O, Markup::Immediate) << '#' << formatImm(btihintop);
1515}
1516
1517void AArch64InstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1518 const MCSubtargetInfo &STI,
1519 raw_ostream &O) {
1520 const MCOperand &MO = MI->getOperand(OpNum);
1521 float FPImm = MO.isDFPImm() ? bit_cast<double>(MO.getDFPImm())
1522 : AArch64_AM::getFPImmFloat(MO.getImm());
1523
1524 // 8 decimal places are enough to perfectly represent permitted floats.
1525 markup(O, Markup::Immediate) << format("#%.8f", FPImm);
1526}
1527
1528static MCRegister getNextVectorRegister(MCRegister Reg, unsigned Stride = 1) {
1529 while (Stride--) {
1530 switch (Reg.id()) {
1531 default:
1532 llvm_unreachable("Vector register expected!");
1533 case AArch64::Q0: Reg = AArch64::Q1; break;
1534 case AArch64::Q1: Reg = AArch64::Q2; break;
1535 case AArch64::Q2: Reg = AArch64::Q3; break;
1536 case AArch64::Q3: Reg = AArch64::Q4; break;
1537 case AArch64::Q4: Reg = AArch64::Q5; break;
1538 case AArch64::Q5: Reg = AArch64::Q6; break;
1539 case AArch64::Q6: Reg = AArch64::Q7; break;
1540 case AArch64::Q7: Reg = AArch64::Q8; break;
1541 case AArch64::Q8: Reg = AArch64::Q9; break;
1542 case AArch64::Q9: Reg = AArch64::Q10; break;
1543 case AArch64::Q10: Reg = AArch64::Q11; break;
1544 case AArch64::Q11: Reg = AArch64::Q12; break;
1545 case AArch64::Q12: Reg = AArch64::Q13; break;
1546 case AArch64::Q13: Reg = AArch64::Q14; break;
1547 case AArch64::Q14: Reg = AArch64::Q15; break;
1548 case AArch64::Q15: Reg = AArch64::Q16; break;
1549 case AArch64::Q16: Reg = AArch64::Q17; break;
1550 case AArch64::Q17: Reg = AArch64::Q18; break;
1551 case AArch64::Q18: Reg = AArch64::Q19; break;
1552 case AArch64::Q19: Reg = AArch64::Q20; break;
1553 case AArch64::Q20: Reg = AArch64::Q21; break;
1554 case AArch64::Q21: Reg = AArch64::Q22; break;
1555 case AArch64::Q22: Reg = AArch64::Q23; break;
1556 case AArch64::Q23: Reg = AArch64::Q24; break;
1557 case AArch64::Q24: Reg = AArch64::Q25; break;
1558 case AArch64::Q25: Reg = AArch64::Q26; break;
1559 case AArch64::Q26: Reg = AArch64::Q27; break;
1560 case AArch64::Q27: Reg = AArch64::Q28; break;
1561 case AArch64::Q28: Reg = AArch64::Q29; break;
1562 case AArch64::Q29: Reg = AArch64::Q30; break;
1563 case AArch64::Q30: Reg = AArch64::Q31; break;
1564 // Vector lists can wrap around.
1565 case AArch64::Q31:
1566 Reg = AArch64::Q0;
1567 break;
1568 case AArch64::Z0: Reg = AArch64::Z1; break;
1569 case AArch64::Z1: Reg = AArch64::Z2; break;
1570 case AArch64::Z2: Reg = AArch64::Z3; break;
1571 case AArch64::Z3: Reg = AArch64::Z4; break;
1572 case AArch64::Z4: Reg = AArch64::Z5; break;
1573 case AArch64::Z5: Reg = AArch64::Z6; break;
1574 case AArch64::Z6: Reg = AArch64::Z7; break;
1575 case AArch64::Z7: Reg = AArch64::Z8; break;
1576 case AArch64::Z8: Reg = AArch64::Z9; break;
1577 case AArch64::Z9: Reg = AArch64::Z10; break;
1578 case AArch64::Z10: Reg = AArch64::Z11; break;
1579 case AArch64::Z11: Reg = AArch64::Z12; break;
1580 case AArch64::Z12: Reg = AArch64::Z13; break;
1581 case AArch64::Z13: Reg = AArch64::Z14; break;
1582 case AArch64::Z14: Reg = AArch64::Z15; break;
1583 case AArch64::Z15: Reg = AArch64::Z16; break;
1584 case AArch64::Z16: Reg = AArch64::Z17; break;
1585 case AArch64::Z17: Reg = AArch64::Z18; break;
1586 case AArch64::Z18: Reg = AArch64::Z19; break;
1587 case AArch64::Z19: Reg = AArch64::Z20; break;
1588 case AArch64::Z20: Reg = AArch64::Z21; break;
1589 case AArch64::Z21: Reg = AArch64::Z22; break;
1590 case AArch64::Z22: Reg = AArch64::Z23; break;
1591 case AArch64::Z23: Reg = AArch64::Z24; break;
1592 case AArch64::Z24: Reg = AArch64::Z25; break;
1593 case AArch64::Z25: Reg = AArch64::Z26; break;
1594 case AArch64::Z26: Reg = AArch64::Z27; break;
1595 case AArch64::Z27: Reg = AArch64::Z28; break;
1596 case AArch64::Z28: Reg = AArch64::Z29; break;
1597 case AArch64::Z29: Reg = AArch64::Z30; break;
1598 case AArch64::Z30: Reg = AArch64::Z31; break;
1599 // Vector lists can wrap around.
1600 case AArch64::Z31:
1601 Reg = AArch64::Z0;
1602 break;
1603 case AArch64::P0: Reg = AArch64::P1; break;
1604 case AArch64::P1: Reg = AArch64::P2; break;
1605 case AArch64::P2: Reg = AArch64::P3; break;
1606 case AArch64::P3: Reg = AArch64::P4; break;
1607 case AArch64::P4: Reg = AArch64::P5; break;
1608 case AArch64::P5: Reg = AArch64::P6; break;
1609 case AArch64::P6: Reg = AArch64::P7; break;
1610 case AArch64::P7: Reg = AArch64::P8; break;
1611 case AArch64::P8: Reg = AArch64::P9; break;
1612 case AArch64::P9: Reg = AArch64::P10; break;
1613 case AArch64::P10: Reg = AArch64::P11; break;
1614 case AArch64::P11: Reg = AArch64::P12; break;
1615 case AArch64::P12: Reg = AArch64::P13; break;
1616 case AArch64::P13: Reg = AArch64::P14; break;
1617 case AArch64::P14: Reg = AArch64::P15; break;
1618 // Vector lists can wrap around.
1619 case AArch64::P15: Reg = AArch64::P0; break;
1620 }
1621 }
1622 return Reg;
1623}
1624
1625template<unsigned size>
1626void AArch64InstPrinter::printGPRSeqPairsClassOperand(const MCInst *MI,
1627 unsigned OpNum,
1628 const MCSubtargetInfo &STI,
1629 raw_ostream &O) {
1630 static_assert(size == 64 || size == 32,
1631 "Template parameter must be either 32 or 64");
1632 MCRegister Reg = MI->getOperand(OpNum).getReg();
1633
1634 unsigned Sube = (size == 32) ? AArch64::sube32 : AArch64::sube64;
1635 unsigned Subo = (size == 32) ? AArch64::subo32 : AArch64::subo64;
1636
1637 MCRegister Even = MRI.getSubReg(Reg, Sube);
1638 MCRegister Odd = MRI.getSubReg(Reg, Subo);
1639 printRegName(O, Even);
1640 O << ", ";
1641 printRegName(O, Odd);
1642}
1643
1644void AArch64InstPrinter::printMatrixTileList(const MCInst *MI, unsigned OpNum,
1645 const MCSubtargetInfo &STI,
1646 raw_ostream &O) {
1647 unsigned MaxRegs = 8;
1648 unsigned RegMask = MI->getOperand(OpNum).getImm();
1649
1650 unsigned NumRegs = 0;
1651 for (unsigned I = 0; I < MaxRegs; ++I)
1652 if ((RegMask & (1 << I)) != 0)
1653 ++NumRegs;
1654
1655 O << "{";
1656 unsigned Printed = 0;
1657 for (unsigned I = 0; I < MaxRegs; ++I) {
1658 unsigned Reg = RegMask & (1 << I);
1659 if (Reg == 0)
1660 continue;
1661 printRegName(O, AArch64::ZAD0 + I);
1662 if (Printed + 1 != NumRegs)
1663 O << ", ";
1664 ++Printed;
1665 }
1666 O << "}";
1667}
1668
1669void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
1670 const MCSubtargetInfo &STI,
1671 raw_ostream &O,
1672 StringRef LayoutSuffix) {
1673 MCRegister Reg = MI->getOperand(OpNum).getReg();
1674
1675 O << "{ ";
1676
1677 // Work out how many registers there are in the list (if there is an actual
1678 // list).
1679 unsigned NumRegs = 1;
1680 if (MRI.getRegClass(AArch64::DDRegClassID).contains(Reg) ||
1681 MRI.getRegClass(AArch64::ZPR2RegClassID).contains(Reg) ||
1682 MRI.getRegClass(AArch64::QQRegClassID).contains(Reg) ||
1683 MRI.getRegClass(AArch64::PPR2RegClassID).contains(Reg) ||
1684 MRI.getRegClass(AArch64::ZPR2StridedRegClassID).contains(Reg))
1685 NumRegs = 2;
1686 else if (MRI.getRegClass(AArch64::DDDRegClassID).contains(Reg) ||
1687 MRI.getRegClass(AArch64::ZPR3RegClassID).contains(Reg) ||
1688 MRI.getRegClass(AArch64::QQQRegClassID).contains(Reg))
1689 NumRegs = 3;
1690 else if (MRI.getRegClass(AArch64::DDDDRegClassID).contains(Reg) ||
1691 MRI.getRegClass(AArch64::ZPR4RegClassID).contains(Reg) ||
1692 MRI.getRegClass(AArch64::QQQQRegClassID).contains(Reg) ||
1693 MRI.getRegClass(AArch64::ZPR4StridedRegClassID).contains(Reg))
1694 NumRegs = 4;
1695
1696 unsigned Stride = 1;
1697 if (MRI.getRegClass(AArch64::ZPR2StridedRegClassID).contains(Reg))
1698 Stride = 8;
1699 else if (MRI.getRegClass(AArch64::ZPR4StridedRegClassID).contains(Reg))
1700 Stride = 4;
1701
1702 // Now forget about the list and find out what the first register is.
1703 if (MCRegister FirstReg = MRI.getSubReg(Reg, AArch64::dsub0))
1704 Reg = FirstReg;
1705 else if (MCRegister FirstReg = MRI.getSubReg(Reg, AArch64::qsub0))
1706 Reg = FirstReg;
1707 else if (MCRegister FirstReg = MRI.getSubReg(Reg, AArch64::zsub0))
1708 Reg = FirstReg;
1709 else if (MCRegister FirstReg = MRI.getSubReg(Reg, AArch64::psub0))
1710 Reg = FirstReg;
1711
1712 // If it's a D-reg, we need to promote it to the equivalent Q-reg before
1713 // printing (otherwise getRegisterName fails).
1714 if (MRI.getRegClass(AArch64::FPR64RegClassID).contains(Reg)) {
1715 const MCRegisterClass &FPR128RC =
1716 MRI.getRegClass(AArch64::FPR128RegClassID);
1717 Reg = MRI.getMatchingSuperReg(Reg, AArch64::dsub, &FPR128RC);
1718 }
1719
1720 if ((MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg) ||
1721 MRI.getRegClass(AArch64::PPRRegClassID).contains(Reg)) &&
1722 NumRegs > 1 && Stride == 1 &&
1723 // Do not print the range when the last register is lower than the first.
1724 // Because it is a wrap-around register.
1725 Reg < getNextVectorRegister(Reg, NumRegs - 1)) {
1726 printRegName(O, Reg);
1727 O << LayoutSuffix;
1728 if (NumRegs > 1) {
1729 // Set of two sve registers should be separated by ','
1730 StringRef split_char = NumRegs == 2 ? ", " : " - ";
1731 O << split_char;
1732 printRegName(O, (getNextVectorRegister(Reg, NumRegs - 1)));
1733 O << LayoutSuffix;
1734 }
1735 } else {
1736 for (unsigned i = 0; i < NumRegs;
1737 ++i, Reg = getNextVectorRegister(Reg, Stride)) {
1738 // wrap-around sve register
1739 if (MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg) ||
1740 MRI.getRegClass(AArch64::PPRRegClassID).contains(Reg))
1741 printRegName(O, Reg);
1742 else
1743 printRegName(O, Reg, AArch64::vreg);
1744 O << LayoutSuffix;
1745 if (i + 1 != NumRegs)
1746 O << ", ";
1747 }
1748 }
1749 O << " }";
1750}
1751
1752void
1753AArch64InstPrinter::printImplicitlyTypedVectorList(const MCInst *MI,
1754 unsigned OpNum,
1755 const MCSubtargetInfo &STI,
1756 raw_ostream &O) {
1757 printVectorList(MI, OpNum, STI, O, "");
1758}
1759
1760template <unsigned NumLanes, char LaneKind>
1761void AArch64InstPrinter::printTypedVectorList(const MCInst *MI, unsigned OpNum,
1762 const MCSubtargetInfo &STI,
1763 raw_ostream &O) {
1764 if (LaneKind == 0) {
1765 printVectorList(MI, OpNum, STI, O, "");
1766 return;
1767 }
1768 std::string Suffix(".");
1769 if (NumLanes)
1770 Suffix += itostr(NumLanes) + LaneKind;
1771 else
1772 Suffix += LaneKind;
1773
1774 printVectorList(MI, OpNum, STI, O, Suffix);
1775}
1776
1777template <unsigned Scale>
1778void AArch64InstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1779 const MCSubtargetInfo &STI,
1780 raw_ostream &O) {
1781 O << "[" << Scale * MI->getOperand(OpNum).getImm() << "]";
1782}
1783
1784template <unsigned Scale>
1785void AArch64InstPrinter::printMatrixIndex(const MCInst *MI, unsigned OpNum,
1786 const MCSubtargetInfo &STI,
1787 raw_ostream &O) {
1788 O << Scale * MI->getOperand(OpNum).getImm();
1789}
1790
1791void AArch64InstPrinter::printAlignedLabel(const MCInst *MI, uint64_t Address,
1792 unsigned OpNum,
1793 const MCSubtargetInfo &STI,
1794 raw_ostream &O) {
1795 // Do not print the numeric target address when symbolizing.
1796 if (SymbolizeOperands)
1797 return;
1798
1799 const MCOperand &Op = MI->getOperand(OpNum);
1800
1801 // If the label has already been resolved to an immediate offset (say, when
1802 // we're running the disassembler), just print the immediate.
1803 if (Op.isImm()) {
1804 int64_t Offset = Op.getImm() * 4;
1805 if (PrintBranchImmAsAddress)
1806 markup(O, Markup::Target) << formatHex(Address + Offset);
1807 else
1808 markup(O, Markup::Immediate) << "#" << formatImm(Offset);
1809 return;
1810 }
1811
1812 // If the branch target is simply an address then print it in hex.
1813 const MCConstantExpr *BranchTarget =
1814 dyn_cast<MCConstantExpr>(MI->getOperand(OpNum).getExpr());
1815 int64_t TargetAddress;
1816 if (BranchTarget && BranchTarget->evaluateAsAbsolute(TargetAddress)) {
1817 markup(O, Markup::Target) << formatHex((uint64_t)TargetAddress);
1818 } else {
1819 // Otherwise, just print the expression.
1820 MAI.printExpr(O, *MI->getOperand(OpNum).getExpr());
1821 }
1822}
1823
1824void AArch64InstPrinter::printAdrAdrpLabel(const MCInst *MI, uint64_t Address,
1825 unsigned OpNum,
1826 const MCSubtargetInfo &STI,
1827 raw_ostream &O) {
1828 // Do not print the numeric target address when symbolizing.
1829 // However, do print for ADRP, as this is typically used together with an ADD
1830 // or an immediate-offset ldr/str and the label is likely at the wrong point.
1831 if (SymbolizeOperands && MI->getOpcode() != AArch64::ADRP)
1832 return;
1833
1834 const MCOperand &Op = MI->getOperand(OpNum);
1835
1836 // If the label has already been resolved to an immediate offset (say, when
1837 // we're running the disassembler), just print the immediate.
1838 if (Op.isImm()) {
1839 int64_t Offset = Op.getImm();
1840 if (MI->getOpcode() == AArch64::ADRP) {
1841 Offset = Offset * 4096;
1842 Address = Address & -4096;
1843 }
1844 WithMarkup M = markup(O, Markup::Immediate);
1845 if (PrintBranchImmAsAddress)
1846 markup(O, Markup::Target) << formatHex(Address + Offset);
1847 else
1848 markup(O, Markup::Immediate) << "#" << Offset;
1849 return;
1850 }
1851
1852 // Otherwise, just print the expression.
1853 MAI.printExpr(O, *MI->getOperand(OpNum).getExpr());
1854}
1855
1856void AArch64InstPrinter::printBarrierOption(const MCInst *MI, unsigned OpNo,
1857 const MCSubtargetInfo &STI,
1858 raw_ostream &O) {
1859 unsigned Val = MI->getOperand(OpNo).getImm();
1860 unsigned Opcode = MI->getOpcode();
1861
1862 StringRef Name;
1863 if (Opcode == AArch64::ISB) {
1864 auto ISB = AArch64ISB::lookupISBByEncoding(Val);
1865 Name = ISB ? ISB->Name : "";
1866 } else if (Opcode == AArch64::TSB) {
1867 auto TSB = AArch64TSB::lookupTSBByEncoding(Val);
1868 Name = TSB ? TSB->Name : "";
1869 } else {
1870 auto DB = AArch64DB::lookupDBByEncoding(Val);
1871 Name = DB ? DB->Name : "";
1872 }
1873 if (!Name.empty())
1874 O << Name;
1875 else
1876 markup(O, Markup::Immediate) << "#" << Val;
1877}
1878
1879void AArch64InstPrinter::printBarriernXSOption(const MCInst *MI, unsigned OpNo,
1880 const MCSubtargetInfo &STI,
1881 raw_ostream &O) {
1882 unsigned Val = MI->getOperand(OpNo).getImm();
1883 assert(MI->getOpcode() == AArch64::DSBnXS);
1884
1885 StringRef Name;
1886 auto DB = AArch64DBnXS::lookupDBnXSByEncoding(Val);
1887 Name = DB ? DB->Name : "";
1888
1889 if (!Name.empty())
1890 O << Name;
1891 else
1892 markup(O, Markup::Immediate) << "#" << Val;
1893}
1894
1895static bool isValidSysReg(const AArch64SysReg::SysReg &Reg, bool Read,
1896 const MCSubtargetInfo &STI) {
1897 return (Read ? Reg.Readable : Reg.Writeable) &&
1898 Reg.haveFeatures(STI.getFeatureBits());
1899}
1900
1901// Looks up a system register either by encoding. Some system
1902// registers share the same encoding between different architectures,
1903// to work around this tablegen will return a range of registers with the same
1904// encodings. We need to check each register in the range to see if it valid.
1905static const AArch64SysReg::SysReg *lookupSysReg(unsigned Val, bool Read,
1906 const MCSubtargetInfo &STI) {
1907 auto Range = AArch64SysReg::lookupSysRegByEncoding(Val);
1908 for (auto &Reg : Range) {
1909 if (isValidSysReg(Reg, Read, STI))
1910 return &Reg;
1911 }
1912
1913 return nullptr;
1914}
1915
1916void AArch64InstPrinter::printMRSSystemRegister(const MCInst *MI, unsigned OpNo,
1917 const MCSubtargetInfo &STI,
1918 raw_ostream &O) {
1919 unsigned Val = MI->getOperand(OpNo).getImm();
1920
1921 // Horrible hack for the one register that has identical encodings but
1922 // different names in MSR and MRS. Because of this, one of MRS and MSR is
1923 // going to get the wrong entry
1924 if (Val == AArch64SysReg::DBGDTRRX_EL0) {
1925 O << "DBGDTRRX_EL0";
1926 return;
1927 }
1928
1929 // Horrible hack for two different registers having the same encoding.
1930 if (Val == AArch64SysReg::TRCEXTINSELR) {
1931 O << "TRCEXTINSELR";
1932 return;
1933 }
1934
1935 const AArch64SysReg::SysReg *Reg = lookupSysReg(Val, true /*Read*/, STI);
1936
1937 if (Reg)
1938 O << Reg->Name;
1939 else
1940 O << AArch64SysReg::genericRegisterString(Val);
1941}
1942
1943void AArch64InstPrinter::printMSRSystemRegister(const MCInst *MI, unsigned OpNo,
1944 const MCSubtargetInfo &STI,
1945 raw_ostream &O) {
1946 unsigned Val = MI->getOperand(OpNo).getImm();
1947
1948 // Horrible hack for the one register that has identical encodings but
1949 // different names in MSR and MRS. Because of this, one of MRS and MSR is
1950 // going to get the wrong entry
1951 if (Val == AArch64SysReg::DBGDTRTX_EL0) {
1952 O << "DBGDTRTX_EL0";
1953 return;
1954 }
1955
1956 // Horrible hack for two different registers having the same encoding.
1957 if (Val == AArch64SysReg::TRCEXTINSELR) {
1958 O << "TRCEXTINSELR";
1959 return;
1960 }
1961
1962 const AArch64SysReg::SysReg *Reg = lookupSysReg(Val, false /*Read*/, STI);
1963
1964 if (Reg)
1965 O << Reg->Name;
1966 else
1967 O << AArch64SysReg::genericRegisterString(Val);
1968}
1969
1970void AArch64InstPrinter::printSystemPStateField(const MCInst *MI, unsigned OpNo,
1971 const MCSubtargetInfo &STI,
1972 raw_ostream &O) {
1973 unsigned Val = MI->getOperand(OpNo).getImm();
1974
1975 auto PStateImm15 = AArch64PState::lookupPStateImm0_15ByEncoding(Val);
1976 auto PStateImm1 = AArch64PState::lookupPStateImm0_1ByEncoding(Val);
1977 if (PStateImm15 && PStateImm15->haveFeatures(STI.getFeatureBits()))
1978 O << PStateImm15->Name;
1979 else if (PStateImm1 && PStateImm1->haveFeatures(STI.getFeatureBits()))
1980 O << PStateImm1->Name;
1981 else
1982 O << "#" << formatImm(Val);
1983}
1984
1985void AArch64InstPrinter::printSIMDType10Operand(const MCInst *MI, unsigned OpNo,
1986 const MCSubtargetInfo &STI,
1987 raw_ostream &O) {
1988 unsigned RawVal = MI->getOperand(OpNo).getImm();
1989 uint64_t Val = AArch64_AM::decodeAdvSIMDModImmType10(RawVal);
1990 markup(O, Markup::Immediate) << format("#%#016llx", Val);
1991}
1992
1993template<int64_t Angle, int64_t Remainder>
1994void AArch64InstPrinter::printComplexRotationOp(const MCInst *MI, unsigned OpNo,
1995 const MCSubtargetInfo &STI,
1996 raw_ostream &O) {
1997 unsigned Val = MI->getOperand(OpNo).getImm();
1998 markup(O, Markup::Immediate) << "#" << (Val * Angle) + Remainder;
1999}
2000
2001void AArch64InstPrinter::printSVEPattern(const MCInst *MI, unsigned OpNum,
2002 const MCSubtargetInfo &STI,
2003 raw_ostream &O) {
2004 unsigned Val = MI->getOperand(OpNum).getImm();
2005 if (auto Pat = AArch64SVEPredPattern::lookupSVEPREDPATByEncoding(Val))
2006 O << Pat->Name;
2007 else
2008 markup(O, Markup::Immediate) << '#' << formatImm(Val);
2009}
2010
2011void AArch64InstPrinter::printSVEVecLenSpecifier(const MCInst *MI,
2012 unsigned OpNum,
2013 const MCSubtargetInfo &STI,
2014 raw_ostream &O) {
2015 unsigned Val = MI->getOperand(OpNum).getImm();
2016 // Pattern has only 1 bit
2017 if (Val > 1)
2018 llvm_unreachable("Invalid vector length specifier");
2019 if (auto Pat =
2020 AArch64SVEVecLenSpecifier::lookupSVEVECLENSPECIFIERByEncoding(Val))
2021 O << Pat->Name;
2022 else
2023 llvm_unreachable("Invalid vector length specifier");
2024}
2025
2026template <char suffix>
2027void AArch64InstPrinter::printSVERegOp(const MCInst *MI, unsigned OpNum,
2028 const MCSubtargetInfo &STI,
2029 raw_ostream &O) {
2030 switch (suffix) {
2031 case 0:
2032 case 'b':
2033 case 'h':
2034 case 's':
2035 case 'd':
2036 case 'q':
2037 break;
2038 default: llvm_unreachable("Invalid kind specifier.");
2039 }
2040
2041 MCRegister Reg = MI->getOperand(OpNum).getReg();
2042 printRegName(O, Reg);
2043 if (suffix != 0)
2044 O << '.' << suffix;
2045}
2046
2047template <typename T>
2048void AArch64InstPrinter::printImmSVE(T Value, raw_ostream &O) {
2049 std::make_unsigned_t<T> HexValue = Value;
2050
2051 if (getPrintImmHex())
2052 markup(O, Markup::Immediate) << '#' << formatHex((uint64_t)HexValue);
2053 else
2054 markup(O, Markup::Immediate) << '#' << formatDec(Value);
2055
2056 if (CommentStream) {
2057 // Do the opposite to that used for instruction operands.
2058 if (getPrintImmHex())
2059 *CommentStream << '=' << formatDec(HexValue) << '\n';
2060 else
2061 *CommentStream << '=' << formatHex((uint64_t)Value) << '\n';
2062 }
2063}
2064
2065template <typename T>
2066void AArch64InstPrinter::printImm8OptLsl(const MCInst *MI, unsigned OpNum,
2067 const MCSubtargetInfo &STI,
2068 raw_ostream &O) {
2069 unsigned UnscaledVal = MI->getOperand(OpNum).getImm();
2070 unsigned Shift = MI->getOperand(OpNum + 1).getImm();
2071 assert(AArch64_AM::getShiftType(Shift) == AArch64_AM::LSL &&
2072 "Unexpected shift type!");
2073
2074 // #0 lsl #8 is never pretty printed
2075 if ((UnscaledVal == 0) && (AArch64_AM::getShiftValue(Shift) != 0)) {
2076 markup(O, Markup::Immediate) << '#' << formatImm(UnscaledVal);
2077 printShifter(MI, OpNum + 1, STI, O);
2078 return;
2079 }
2080
2081 T Val;
2082 if (std::is_signed<T>())
2083 Val = (int8_t)UnscaledVal * (1 << AArch64_AM::getShiftValue(Shift));
2084 else
2085 Val = (uint8_t)UnscaledVal * (1 << AArch64_AM::getShiftValue(Shift));
2086
2087 printImmSVE(Val, O);
2088}
2089
2090template <typename T>
2091void AArch64InstPrinter::printSVELogicalImm(const MCInst *MI, unsigned OpNum,
2092 const MCSubtargetInfo &STI,
2093 raw_ostream &O) {
2094 typedef std::make_signed_t<T> SignedT;
2095 typedef std::make_unsigned_t<T> UnsignedT;
2096
2097 uint64_t Val = MI->getOperand(OpNum).getImm();
2098 UnsignedT PrintVal = AArch64_AM::decodeLogicalImmediate(Val, 64);
2099
2100 // Prefer the default format for 16bit values, hex otherwise.
2101 if ((int16_t)PrintVal == (SignedT)PrintVal)
2102 printImmSVE((T)PrintVal, O);
2103 else if ((uint16_t)PrintVal == PrintVal)
2104 printImmSVE(PrintVal, O);
2105 else
2106 markup(O, Markup::Immediate) << '#' << formatHex((uint64_t)PrintVal);
2107}
2108
2109template <int Width>
2110void AArch64InstPrinter::printZPRasFPR(const MCInst *MI, unsigned OpNum,
2111 const MCSubtargetInfo &STI,
2112 raw_ostream &O) {
2113 unsigned Base;
2114 switch (Width) {
2115 case 8: Base = AArch64::B0; break;
2116 case 16: Base = AArch64::H0; break;
2117 case 32: Base = AArch64::S0; break;
2118 case 64: Base = AArch64::D0; break;
2119 case 128: Base = AArch64::Q0; break;
2120 default:
2121 llvm_unreachable("Unsupported width");
2122 }
2123 MCRegister Reg = MI->getOperand(OpNum).getReg();
2124 printRegName(O, Reg - AArch64::Z0 + Base);
2125}
2126
2127template <unsigned ImmIs0, unsigned ImmIs1>
2128void AArch64InstPrinter::printExactFPImm(const MCInst *MI, unsigned OpNum,
2129 const MCSubtargetInfo &STI,
2130 raw_ostream &O) {
2131 auto *Imm0Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmIs0);
2132 auto *Imm1Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmIs1);
2133 unsigned Val = MI->getOperand(OpNum).getImm();
2134 markup(O, Markup::Immediate)
2135 << "#" << (Val ? Imm1Desc->Repr : Imm0Desc->Repr);
2136}
2137
2138void AArch64InstPrinter::printGPR64as32(const MCInst *MI, unsigned OpNum,
2139 const MCSubtargetInfo &STI,
2140 raw_ostream &O) {
2141 MCRegister Reg = MI->getOperand(OpNum).getReg();
2142 printRegName(O, getWRegFromXReg(Reg));
2143}
2144
2145void AArch64InstPrinter::printGPR64x8(const MCInst *MI, unsigned OpNum,
2146 const MCSubtargetInfo &STI,
2147 raw_ostream &O) {
2148 MCRegister Reg = MI->getOperand(OpNum).getReg();
2149 printRegName(O, MRI.getSubReg(Reg, AArch64::x8sub_0));
2150}
2151
2152void AArch64InstPrinter::printSyspXzrPair(const MCInst *MI, unsigned OpNum,
2153 const MCSubtargetInfo &STI,
2154 raw_ostream &O) {
2155 MCRegister Reg = MI->getOperand(OpNum).getReg();
2156 assert(Reg == AArch64::XZR &&
2157 "MC representation of SyspXzrPair should be XZR");
2158 O << getRegisterName(Reg) << ", " << getRegisterName(Reg);
2159}
2160
2161void AArch64InstPrinter::printPHintOp(const MCInst *MI, unsigned OpNum,
2162 const MCSubtargetInfo &STI,
2163 raw_ostream &O) {
2164 unsigned Op = MI->getOperand(OpNum).getImm();
2165 auto PH = AArch64PHint::lookupPHintByEncoding(Op);
2166 if (PH)
2167 O << PH->Name;
2168 else
2169 markup(O, Markup::Immediate) << '#' << formatImm(Op);
2170}
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:103
getNextVectorRegister
static MCRegister getNextVectorRegister(MCRegister Reg, unsigned Stride=1)
Definition: AArch64InstPrinter.cpp:1528
lookupSysReg
static const AArch64SysReg::SysReg * lookupSysReg(unsigned Val, bool Read, const MCSubtargetInfo &STI)
Definition: AArch64InstPrinter.cpp:1905
getLdStNInstrDesc
static const LdStNInstrDesc * getLdStNInstrDesc(unsigned Opcode)
Definition: AArch64InstPrinter.cpp:775
LdStNInstInfo
static const LdStNInstrDesc LdStNInstInfo[]
Definition: AArch64InstPrinter.cpp:432
isValidSysReg
static bool isValidSysReg(const AArch64SysReg::SysReg &Reg, bool Read, const MCSubtargetInfo &STI)
Definition: AArch64InstPrinter.cpp:1895
isTblTbxInstruction
static bool isTblTbxInstruction(unsigned Opcode, StringRef &Layout, bool &IsTbx)
Definition: AArch64InstPrinter.cpp:387
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
Name
std::string Name
Definition: ELFObjHandler.cpp:77
Size
uint64_t Size
Definition: ELFObjHandler.cpp:81
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:110
RegName
#define RegName(no)
I
#define I(x, y, z)
Definition: MD5.cpp:58
Range
ConstantRange Range(APInt(BitWidth, Low), APInt(BitWidth, High))
OS
raw_pwrite_stream & OS
Definition: SampleProfWriter.cpp:51
StringExtras.h
This file contains some functions that are useful when dealing with strings.
llvm::AArch64AppleInstPrinter::printInst
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
Definition: AArch64InstPrinter.cpp:783
llvm::AArch64AppleInstPrinter::AArch64AppleInstPrinter
AArch64AppleInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
Definition: AArch64InstPrinter.cpp:48
llvm::AArch64AppleInstPrinter::getRegisterName
static const char * getRegisterName(MCRegister Reg, unsigned AltIdx=AArch64::NoRegAltName)
llvm::AArch64AppleInstPrinter::getRegName
StringRef getRegName(MCRegister Reg) const override
Definition: AArch64InstPrinter.cpp:842
llvm::AArch64InstPrinter::printMRSSystemRegister
void printMRSSystemRegister(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1916
llvm::AArch64InstPrinter::printImm
void printImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1178
llvm::AArch64InstPrinter::printAlignedLabel
void printAlignedLabel(const MCInst *MI, uint64_t Address, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1791
llvm::AArch64InstPrinter::printAMIndexedWB
void printAMIndexedWB(const MCInst *MI, unsigned OpNum, unsigned Scale, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1446
llvm::AArch64InstPrinter::printMatrix
void printMatrix(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1101
llvm::AArch64InstPrinter::printAdrAdrpLabel
void printAdrAdrpLabel(const MCInst *MI, uint64_t Address, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1824
llvm::AArch64InstPrinter::printPrefetchOp
void printPrefetchOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1475
llvm::AArch64InstPrinter::printZPRasFPR
void printZPRasFPR(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:2110
llvm::AArch64InstPrinter::printInstruction
virtual void printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
llvm::AArch64InstPrinter::printAMNoIndex
void printAMNoIndex(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1410
llvm::AArch64InstPrinter::printUImm12Offset
void printUImm12Offset(const MCInst *MI, unsigned OpNum, unsigned Scale, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1435
llvm::AArch64InstPrinter::printSVCROp
void printSVCROp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1153
llvm::AArch64InstPrinter::AArch64InstPrinter
AArch64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
Definition: AArch64InstPrinter.cpp:43
llvm::AArch64InstPrinter::printCondCode
void printCondCode(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1396
llvm::AArch64InstPrinter::printBarriernXSOption
void printBarriernXSOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1879
llvm::AArch64InstPrinter::printSystemPStateField
void printSystemPStateField(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1970
llvm::AArch64InstPrinter::printShifter
void printShifter(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1266
llvm::AArch64InstPrinter::printPSBHintOp
void printPSBHintOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1495
llvm::AArch64InstPrinter::printGPR64x8
void printGPR64x8(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:2145
llvm::AArch64InstPrinter::printSIMDType10Operand
void printSIMDType10Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1985
llvm::AArch64InstPrinter::getRegName
virtual StringRef getRegName(MCRegister Reg) const
Definition: AArch64InstPrinter.cpp:70
llvm::AArch64InstPrinter::printMemExtend
void printMemExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O, char SrcRegKind, unsigned Width)
Definition: AArch64InstPrinter.cpp:1340
llvm::AArch64InstPrinter::printMatrixTileVector
void printMatrixTileVector(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1132
llvm::AArch64InstPrinter::printSysAlias
bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:896
llvm::AArch64InstPrinter::printSysCROperand
void printSysCROperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1226
llvm::AArch64InstPrinter::applyTargetSpecificCLOption
bool applyTargetSpecificCLOption(StringRef Opt) override
Customize the printer according to a command line option.
Definition: AArch64InstPrinter.cpp:53
llvm::AArch64InstPrinter::printRPRFMOperand
void printRPRFMOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1462
llvm::AArch64InstPrinter::printVectorList
void printVectorList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O, StringRef LayoutSuffix)
Definition: AArch64InstPrinter.cpp:1669
llvm::AArch64InstPrinter::printImplicitlyTypedVectorList
void printImplicitlyTypedVectorList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Print a list of vector registers where the type suffix is implicit (i.e.
Definition: AArch64InstPrinter.cpp:1753
llvm::AArch64InstPrinter::printGPRSeqPairsClassOperand
void printGPRSeqPairsClassOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1626
llvm::AArch64InstPrinter::printExtendedRegister
void printExtendedRegister(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1286
llvm::AArch64InstPrinter::printRangePrefetchAlias
bool printRangePrefetchAlias(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O, StringRef Annot)
Definition: AArch64InstPrinter.cpp:846
llvm::AArch64InstPrinter::printMSRSystemRegister
void printMSRSystemRegister(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1943
llvm::AArch64InstPrinter::printSVERegOp
void printSVERegOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:2027
llvm::AArch64InstPrinter::printPHintOp
void printPHintOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:2161
llvm::AArch64InstPrinter::printMatrixTile
void printMatrixTile(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1145
llvm::AArch64InstPrinter::printFPImmOperand
void printFPImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1517
llvm::AArch64InstPrinter::printMemExtendImpl
void printMemExtendImpl(bool SignExtend, bool DoShift, unsigned Width, char SrcRegKind, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1324
llvm::AArch64InstPrinter::printSVEVecLenSpecifier
void printSVEVecLenSpecifier(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:2011
llvm::AArch64InstPrinter::printBTIHintOp
void printBTIHintOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1506
llvm::AArch64InstPrinter::printSyspXzrPair
void printSyspXzrPair(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:2152
llvm::AArch64InstPrinter::printArithExtend
void printArithExtend(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1293
llvm::AArch64InstPrinter::printOperand
void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1164
llvm::AArch64InstPrinter::printAliasInstr
virtual bool printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
llvm::AArch64InstPrinter::printImmScale
void printImmScale(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1419
llvm::AArch64InstPrinter::printSImm
void printSImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1193
llvm::AArch64InstPrinter::printAddSubImm
void printAddSubImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1234
llvm::AArch64InstPrinter::printImmSVE
void printImmSVE(T Value, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:2048
llvm::AArch64InstPrinter::printShiftedRegister
void printShiftedRegister(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1279
llvm::AArch64InstPrinter::printComplexRotationOp
void printComplexRotationOp(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1994
llvm::AArch64InstPrinter::printGPR64as32
void printGPR64as32(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:2138
llvm::AArch64InstPrinter::printSyspAlias
bool printSyspAlias(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1040
llvm::AArch64InstPrinter::printRegName
void printRegName(raw_ostream &OS, MCRegister Reg) override
Print the assembler register name.
Definition: AArch64InstPrinter.cpp:61
llvm::AArch64InstPrinter::printMatrixTileList
void printMatrixTileList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1644
llvm::AArch64InstPrinter::printMatrixIndex
void printMatrixIndex(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1785
llvm::AArch64InstPrinter::printImmRangeScale
void printImmRangeScale(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1427
llvm::AArch64InstPrinter::printTypedVectorList
void printTypedVectorList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1761
llvm::AArch64InstPrinter::printInst
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
Definition: AArch64InstPrinter.cpp:74
llvm::AArch64InstPrinter::printLogicalImm
void printLogicalImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1257
llvm::AArch64InstPrinter::printSVEPattern
void printSVEPattern(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:2001
llvm::AArch64InstPrinter::getRegisterName
static const char * getRegisterName(MCRegister Reg, unsigned AltIdx=AArch64::NoRegAltName)
llvm::AArch64InstPrinter::printVRegOperand
void printVRegOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1218
llvm::AArch64InstPrinter::printPostIncOperand
void printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1205
llvm::AArch64InstPrinter::printPredicateAsCounter
void printPredicateAsCounter(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1367
llvm::AArch64InstPrinter::printVectorIndex
void printVectorIndex(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1778
llvm::AArch64InstPrinter::printImm8OptLsl
void printImm8OptLsl(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:2066
llvm::AArch64InstPrinter::printRegWithShiftExtend
void printRegWithShiftExtend(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1349
llvm::AArch64InstPrinter::printImmHex
void printImmHex(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1185
llvm::AArch64InstPrinter::printInverseCondCode
void printInverseCondCode(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1403
llvm::AArch64InstPrinter::printExactFPImm
void printExactFPImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:2128
llvm::AArch64InstPrinter::printBarrierOption
void printBarrierOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1856
llvm::AArch64InstPrinter::printSVELogicalImm
void printSVELogicalImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:2091
llvm::DWARFExpression::Operation
This class represents an Operation in the Expression.
Definition: DWARFExpression.h:33
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:64
llvm::MCAsmInfo::printExpr
void printExpr(raw_ostream &, const MCExpr &) const
Definition: MCAsmInfo.cpp:153
llvm::MCAsmInfo::getCommentString
StringRef getCommentString() const
Definition: MCAsmInfo.h:538
llvm::MCInstPrinter
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:46
llvm::MCInstPrinter::markup
WithMarkup markup(raw_ostream &OS, Markup M)
Definition: MCInstPrinter.cpp:227
llvm::MCInstPrinter::formatHex
format_object< int64_t > formatHex(int64_t Value) const
Definition: MCInstPrinter.cpp:190
llvm::MCInstPrinter::CommentStream
raw_ostream * CommentStream
A stream that comments can be emitted to if desired.
Definition: MCInstPrinter.h:51
llvm::MCInstPrinter::getPrintImmHex
bool getPrintImmHex() const
Definition: MCInstPrinter.h:163
llvm::MCInstPrinter::SymbolizeOperands
bool SymbolizeOperands
If true, symbolize branch target and memory reference operands.
Definition: MCInstPrinter.h:78
llvm::MCInstPrinter::formatDec
format_object< int64_t > formatDec(int64_t Value) const
Utility functions to print decimal/hexadecimal values.
Definition: MCInstPrinter.cpp:186
llvm::MCInstPrinter::MRI
const MCRegisterInfo & MRI
Definition: MCInstPrinter.h:54
llvm::MCInstPrinter::printAnnotation
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
Definition: MCInstPrinter.cpp:50
llvm::MCInstPrinter::MAI
const MCAsmInfo & MAI
Definition: MCInstPrinter.h:52
llvm::MCInstPrinter::formatImm
format_object< int64_t > formatImm(int64_t Value) const
Utility function to print immediates in decimal or hex.
Definition: MCInstPrinter.h:176
llvm::MCInstPrinter::PrintBranchImmAsAddress
bool PrintBranchImmAsAddress
If true, a branch immediate (e.g.
Definition: MCInstPrinter.h:75
llvm::MCInstPrinter::PrintAliases
bool PrintAliases
True if we prefer aliases (e.g. nop) to raw mnemonics.
Definition: MCInstPrinter.h:64
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:188
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:27
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:40
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:84
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:66
llvm::MCOperand::isReg
bool isReg() const
Definition: MCInst.h:65
llvm::MCOperand::getReg
MCRegister getReg() const
Returns the register number.
Definition: MCInst.h:73
llvm::MCOperand::isDFPImm
bool isDFPImm() const
Definition: MCInst.h:68
llvm::MCOperand::getExpr
const MCExpr * getExpr() const
Definition: MCInst.h:118
llvm::MCOperand::getDFPImm
uint64_t getDFPImm() const
Definition: MCInst.h:104
llvm::MCOperand::isExpr
bool isExpr() const
Definition: MCInst.h:69
llvm::MCRegisterClass
MCRegisterClass - Base class of TargetRegisterClass.
Definition: MCRegisterInfo.h:36
llvm::MCRegisterClass::contains
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
Definition: MCRegisterInfo.h:74
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:150
llvm::MCRegisterInfo::getMatchingSuperReg
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition: MCRegisterInfo.cpp:108
llvm::MCRegisterInfo::getRegClass
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: MCRegisterInfo.h:467
llvm::MCRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: MCRegisterInfo.cpp:116
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:77
llvm::MCSubtargetInfo::hasFeature
bool hasFeature(unsigned Feature) const
Definition: MCSubtargetInfo.h:122
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:115
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:55
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
uint16_t
uint64_t
uint8_t
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:164
llvm::AArch64CC::getCondCodeName
static const char * getCondCodeName(CondCode Code)
Definition: AArch64BaseInfo.h:281
llvm::AArch64CC::getInvertedCondCode
static CondCode getInvertedCondCode(CondCode Code)
Definition: AArch64BaseInfo.h:303
llvm::AArch64PHint::lookupPHintByEncoding
const PHint * lookupPHintByEncoding(uint16_t)
llvm::AArch64SysReg::genericRegisterString
std::string genericRegisterString(uint32_t Bits)
Definition: AArch64BaseInfo.cpp:169
llvm::AArch64_AM::isMOVNMovAlias
static bool isMOVNMovAlias(uint64_t Value, int Shift, int RegWidth)
Definition: AArch64AddressingModes.h:850
llvm::AArch64_AM::decodeLogicalImmediate
static uint64_t decodeLogicalImmediate(uint64_t val, unsigned regSize)
decodeLogicalImmediate - Decode a logical immediate value in the form "N:immr:imms" (where the immr a...
Definition: AArch64AddressingModes.h:293
llvm::AArch64_AM::getShiftValue
static unsigned getShiftValue(unsigned Imm)
getShiftValue - Extract the shift value.
Definition: AArch64AddressingModes.h:85
llvm::AArch64_AM::isAnyMOVWMovAlias
static bool isAnyMOVWMovAlias(uint64_t Value, int RegWidth)
Definition: AArch64AddressingModes.h:862
llvm::AArch64_AM::getArithShiftValue
static unsigned getArithShiftValue(unsigned Imm)
getArithShiftValue - get the arithmetic shift value.
Definition: AArch64AddressingModes.h:118
llvm::AArch64_AM::getFPImmFloat
static float getFPImmFloat(unsigned Imm)
Definition: AArch64AddressingModes.h:343
llvm::AArch64_AM::isMOVZMovAlias
static bool isMOVZMovAlias(uint64_t Value, int Shift, int RegWidth)
Definition: AArch64AddressingModes.h:839
llvm::AArch64_AM::ShiftExtendType
ShiftExtendType
Definition: AArch64AddressingModes.h:32
llvm::AArch64_AM::LSL
@ LSL
Definition: AArch64AddressingModes.h:34
llvm::AArch64_AM::UXTW
@ UXTW
Definition: AArch64AddressingModes.h:42
llvm::AArch64_AM::UXTX
@ UXTX
Definition: AArch64AddressingModes.h:43
llvm::AArch64_AM::getShiftExtendName
static const char * getShiftExtendName(AArch64_AM::ShiftExtendType ST)
getShiftName - Get the string encoding for the shift type.
Definition: AArch64AddressingModes.h:52
llvm::AArch64_AM::decodeAdvSIMDModImmType10
static uint64_t decodeAdvSIMDModImmType10(uint8_t Imm)
Definition: AArch64AddressingModes.h:663
llvm::AArch64_AM::getArithExtendType
static AArch64_AM::ShiftExtendType getArithExtendType(unsigned Imm)
Definition: AArch64AddressingModes.h:138
llvm::AArch64_AM::getShiftType
static AArch64_AM::ShiftExtendType getShiftType(unsigned Imm)
getShiftType - Extract the shift type.
Definition: AArch64AddressingModes.h:73
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::Offset
@ Offset
Definition: DWP.cpp:477
llvm::size
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition: STLExtras.h:1702
llvm::Read
@ Read
Definition: CodeGenData.h:108
llvm::transform
OutputIt transform(R &&Range, OutputIt d_first, UnaryFunction F)
Wrapper function around std::transform to apply a function to a range and store the result elsewhere.
Definition: STLExtras.h:1987
llvm::Log2_32
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:336
llvm::atomicBarrierDroppedOnZero
static bool atomicBarrierDroppedOnZero(unsigned Opcode)
Definition: AArch64BaseInfo.h:207
llvm::format
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:126
llvm::getWRegFromXReg
static MCRegister getWRegFromXReg(MCRegister Reg)
Definition: AArch64BaseInfo.h:30
llvm::BitWidth
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:223
llvm::SignExtend64
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition: MathExtras.h:577
raw_ostream.h
llvm::SysAlias::haveFeatures
bool haveFeatures(FeatureBitset ActiveFeatures) const
Definition: AArch64BaseInfo.h:396
llvm::SysAlias::Name
const char * Name
Definition: AArch64BaseInfo.h:388
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