LLVM 22.0.0git
ARMAsmBackend.h
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1//===-- ARMAsmBackend.h - ARM Assembler Backend -----------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLVM_LIB_TARGET_ARM_ARMASMBACKEND_H
10#define LLVM_LIB_TARGET_ARM_ARMASMBACKEND_H
11
17
18namespace llvm {
19
21public:
24
25 bool hasNOP(const MCSubtargetInfo *STI) const {
26 return STI->hasFeature(ARM::HasV6T2Ops);
27 }
28
29 std::optional<MCFixupKind> getFixupKind(StringRef Name) const override;
30
31 MCFixupKindInfo getFixupKindInfo(MCFixupKind Kind) const override;
32
34
35 unsigned adjustFixupValue(const MCAssembler &Asm, const MCFixup &Fixup,
37 bool IsResolved, MCContext &Ctx,
38 const MCSubtargetInfo *STI) const;
39
40 std::optional<bool> evaluateFixup(const MCFragment &, MCFixup &, MCValue &,
41 uint64_t &) override;
42 void applyFixup(const MCFragment &, const MCFixup &, const MCValue &Target,
43 uint8_t *Data, uint64_t Value, bool IsResolved) override;
44
45 unsigned getRelaxedOpcode(unsigned Op, const MCSubtargetInfo &STI) const;
46
48 const MCSubtargetInfo &STI) const override;
49
50 const char *reasonForFixupRelaxation(const MCFixup &Fixup,
51 uint64_t Value) const;
52
54 const MCValue &, uint64_t,
55 bool) const override;
56
57 void relaxInstruction(MCInst &Inst,
58 const MCSubtargetInfo &STI) const override;
59
61 const MCSubtargetInfo *STI) const override;
62
63 unsigned getPointerSize() const { return 4; }
64};
65} // end namespace llvm
66
67#endif
std::string Name
mir Rename Register Operands
PowerPC TLS Dynamic Call Fixup
raw_pwrite_stream & OS
const char * reasonForFixupRelaxation(const MCFixup &Fixup, uint64_t Value) const
unsigned getPointerSize() const
Definition: ARMAsmBackend.h:63
bool mayNeedRelaxation(unsigned Opcode, ArrayRef< MCOperand > Operands, const MCSubtargetInfo &STI) const override
Check whether the given instruction (encoded as Opcode+Operands) may need relaxation.
ARMAsmBackend(const Target &T, llvm::endianness Endian)
Definition: ARMAsmBackend.h:22
bool fixupNeedsRelaxationAdvanced(const MCFragment &, const MCFixup &, const MCValue &, uint64_t, bool) const override
Target specific predicate for whether a given fixup requires the associated instruction to be relaxed...
void applyFixup(const MCFragment &, const MCFixup &, const MCValue &Target, uint8_t *Data, uint64_t Value, bool IsResolved) override
bool hasNOP(const MCSubtargetInfo *STI) const
Definition: ARMAsmBackend.h:25
MCFixupKindInfo getFixupKindInfo(MCFixupKind Kind) const override
Get information on a fixup kind.
unsigned getRelaxedOpcode(unsigned Op, const MCSubtargetInfo &STI) const
std::optional< bool > evaluateFixup(const MCFragment &, MCFixup &, MCValue &, uint64_t &) override
unsigned adjustFixupValue(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, uint64_t Value, bool IsResolved, MCContext &Ctx, const MCSubtargetInfo *STI) const
bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const override
Write an (optimal) nop sequence of Count bytes to the given output.
std::optional< MCFixupKind > getFixupKind(StringRef Name) const override
Map a relocation name used in .reloc to a fixup kind.
void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const override
Relax the instruction in the given fragment to the next wider instruction.
bool shouldForceRelocation(const MCFixup &Fixup, const MCValue &Target)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
This class represents an Operation in the Expression.
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:55
const llvm::endianness Endian
Definition: MCAsmBackend.h:69
MCAssembler * Asm
Definition: MCAsmBackend.h:59
Context object for machine code objects.
Definition: MCContext.h:83
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:61
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:188
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:55
Target - Wrapper for Target specific information.
LLVM Value Representation.
Definition: Value.h:75
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
endianness
Definition: bit.h:71
Target independent information on a fixup kind.
Definition: MCAsmBackend.h:38