LLVM 21.0.0git
HexagonDisassembler.cpp
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1//===- HexagonDisassembler.cpp - Disassembler for Hexagon ISA -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "MCTargetDesc/HexagonBaseInfo.h"
10#include "MCTargetDesc/HexagonMCChecker.h"
11#include "MCTargetDesc/HexagonMCInstrInfo.h"
12#include "MCTargetDesc/HexagonMCTargetDesc.h"
13#include "TargetInfo/HexagonTargetInfo.h"
14#include "llvm/ADT/ArrayRef.h"
15#include "llvm/MC/MCContext.h"
16#include "llvm/MC/MCDecoderOps.h"
17#include "llvm/MC/MCDisassembler/MCDisassembler.h"
18#include "llvm/MC/MCExpr.h"
19#include "llvm/MC/MCInst.h"
20#include "llvm/MC/MCInstrInfo.h"
21#include "llvm/MC/MCRegisterInfo.h"
22#include "llvm/MC/MCSubtargetInfo.h"
23#include "llvm/MC/TargetRegistry.h"
24#include "llvm/Support/Endian.h"
25#include "llvm/Support/MathExtras.h"
26#include "llvm/Support/raw_ostream.h"
27#include <cassert>
28#include <cstddef>
29#include <cstdint>
30#include <memory>
31
32#define DEBUG_TYPE "hexagon-disassembler"
33
34using namespace llvm;
35using namespace Hexagon;
36
37using DecodeStatus = MCDisassembler::DecodeStatus;
38
39namespace {
40
41/// Hexagon disassembler for all Hexagon platforms.
42class HexagonDisassembler : public MCDisassembler {
43public:
44 std::unique_ptr<MCInstrInfo const> const MCII;
45 std::unique_ptr<MCInst *> CurrentBundle;
46 mutable MCInst const *CurrentExtender;
47
48 HexagonDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
49 MCInstrInfo const *MCII)
50 : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *),
51 CurrentExtender(nullptr) {}
52
53 DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB,
54 ArrayRef<uint8_t> Bytes, uint64_t Address,
55 raw_ostream &CStream, bool &Complete) const;
56 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
57 ArrayRef<uint8_t> Bytes, uint64_t Address,
58 raw_ostream &CStream) const override;
59 void remapInstruction(MCInst &Instr) const;
60};
61
62static uint64_t fullValue(HexagonDisassembler const &Disassembler, MCInst &MI,
63 int64_t Value) {
64 MCInstrInfo MCII = *Disassembler.MCII;
65 if (!Disassembler.CurrentExtender ||
66 MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI))
67 return Value;
68 unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
69 uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f;
70 int64_t Bits;
71 bool Success =
72 Disassembler.CurrentExtender->getOperand(0).getExpr()->evaluateAsAbsolute(
73 Bits);
74 assert(Success);
75 (void)Success;
76 uint64_t Upper26 = static_cast<uint64_t>(Bits);
77 uint64_t Operand = Upper26 | Lower6;
78 return Operand;
79}
80static HexagonDisassembler const &disassembler(const MCDisassembler *Decoder) {
81 return *static_cast<HexagonDisassembler const *>(Decoder);
82}
83template <size_t T>
84static void signedDecoder(MCInst &MI, unsigned tmp,
85 const MCDisassembler *Decoder) {
86 HexagonDisassembler const &Disassembler = disassembler(Decoder);
87 int64_t FullValue = fullValue(Disassembler, MI, SignExtend64<T>(tmp));
88 int64_t Extended = SignExtend64<32>(FullValue);
89 HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());
90}
91}
92
93// Forward declare these because the auto-generated code will reference them.
94// Definitions are further down.
95
96static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
97 uint64_t Address,
98 const MCDisassembler *Decoder);
99static DecodeStatus
100DecodeGeneralSubRegsRegisterClass(MCInst &Inst, unsigned RegNo,
101 uint64_t Address,
102 const MCDisassembler *Decoder);
103static DecodeStatus
104DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
105 const MCDisassembler *Decoder);
106static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
107 uint64_t Address,
108 const MCDisassembler *Decoder);
109static DecodeStatus
110DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
111 const MCDisassembler *Decoder);
112static DecodeStatus
113DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo,
114 uint64_t Address,
115 const MCDisassembler *Decoder);
116static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
117 uint64_t Address,
118 const MCDisassembler *Decoder);
119static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst, unsigned RegNo,
120 uint64_t Address,
121 const MCDisassembler *Decoder);
122static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
123 uint64_t Address,
124 const MCDisassembler *Decoder);
125static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
126 uint64_t Address,
127 const MCDisassembler *Decoder);
128static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
129 uint64_t Address,
130 const MCDisassembler *Decoder);
131static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo,
132 uint64_t Address,
133 const MCDisassembler *Decoder);
134static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo,
135 uint64_t Address,
136 const MCDisassembler *Decoder);
137static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
138 uint64_t Address,
139 const MCDisassembler *Decoder);
140static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
141 uint64_t Address,
142 const MCDisassembler *Decoder);
143static DecodeStatus
144DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
145 const MCDisassembler *Decoder);
146static DecodeStatus DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
147 uint64_t Address,
148 const MCDisassembler *Decoder);
149
150static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
151 uint64_t Address,
152 const MCDisassembler *Decoder);
153static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp,
154 uint64_t /*Address*/,
155 const MCDisassembler *Decoder);
156static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
157 const MCDisassembler *Decoder);
158#include "HexagonDepDecoders.inc"
159#include "HexagonGenDisassemblerTables.inc"
160
161static MCDisassembler *createHexagonDisassembler(const Target &T,
162 const MCSubtargetInfo &STI,
163 MCContext &Ctx) {
164 return new HexagonDisassembler(STI, Ctx, T.createMCInstrInfo());
165}
166
167extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonDisassembler() {
168 TargetRegistry::RegisterMCDisassembler(getTheHexagonTarget(),
169 createHexagonDisassembler);
170}
171
172DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
173 ArrayRef<uint8_t> Bytes,
174 uint64_t Address,
175 raw_ostream &CS) const {
176 CommentStream = &CS;
177
178 DecodeStatus Result = DecodeStatus::Success;
179 bool Complete = false;
180 Size = 0;
181
182 *CurrentBundle = &MI;
183 MI.setOpcode(Hexagon::BUNDLE);
184 MI.addOperand(MCOperand::createImm(0));
185 while (Result == Success && !Complete) {
186 if (Bytes.size() < HEXAGON_INSTR_SIZE)
187 return MCDisassembler::Fail;
188 MCInst *Inst = getContext().createMCInst();
189 Result = getSingleInstruction(*Inst, MI, Bytes, Address, CS, Complete);
190 MI.addOperand(MCOperand::createInst(Inst));
191 Size += HEXAGON_INSTR_SIZE;
192 Bytes = Bytes.slice(HEXAGON_INSTR_SIZE);
193 }
194 if (Result == MCDisassembler::Fail)
195 return Result;
196 if (Size > HEXAGON_MAX_PACKET_SIZE)
197 return MCDisassembler::Fail;
198
199 const auto ArchSTI = Hexagon_MC::getArchSubtarget(&STI);
200 const auto STI_ = (ArchSTI != nullptr) ? *ArchSTI : STI;
201 HexagonMCChecker Checker(getContext(), *MCII, STI_, MI,
202 *getContext().getRegisterInfo(), false);
203 if (!Checker.check())
204 return MCDisassembler::Fail;
205 remapInstruction(MI);
206 return MCDisassembler::Success;
207}
208
209void HexagonDisassembler::remapInstruction(MCInst &Instr) const {
210 for (auto I: HexagonMCInstrInfo::bundleInstructions(Instr)) {
211 auto &MI = const_cast<MCInst &>(*I.getInst());
212 switch (MI.getOpcode()) {
213 case Hexagon::S2_allocframe:
214 if (MI.getOperand(0).getReg() == Hexagon::R29) {
215 MI.setOpcode(Hexagon::S6_allocframe_to_raw);
216 MI.erase(MI.begin () + 1);
217 MI.erase(MI.begin ());
218 }
219 break;
220 case Hexagon::L2_deallocframe:
221 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
222 MI.getOperand(1).getReg() == Hexagon::R30) {
223 MI.setOpcode(L6_deallocframe_map_to_raw);
224 MI.erase(MI.begin () + 1);
225 MI.erase(MI.begin ());
226 }
227 break;
228 case Hexagon::L4_return:
229 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
230 MI.getOperand(1).getReg() == Hexagon::R30) {
231 MI.setOpcode(L6_return_map_to_raw);
232 MI.erase(MI.begin () + 1);
233 MI.erase(MI.begin ());
234 }
235 break;
236 case Hexagon::L4_return_t:
237 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
238 MI.getOperand(2).getReg() == Hexagon::R30) {
239 MI.setOpcode(L4_return_map_to_raw_t);
240 MI.erase(MI.begin () + 2);
241 MI.erase(MI.begin ());
242 }
243 break;
244 case Hexagon::L4_return_f:
245 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
246 MI.getOperand(2).getReg() == Hexagon::R30) {
247 MI.setOpcode(L4_return_map_to_raw_f);
248 MI.erase(MI.begin () + 2);
249 MI.erase(MI.begin ());
250 }
251 break;
252 case Hexagon::L4_return_tnew_pt:
253 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
254 MI.getOperand(2).getReg() == Hexagon::R30) {
255 MI.setOpcode(L4_return_map_to_raw_tnew_pt);
256 MI.erase(MI.begin () + 2);
257 MI.erase(MI.begin ());
258 }
259 break;
260 case Hexagon::L4_return_fnew_pt:
261 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
262 MI.getOperand(2).getReg() == Hexagon::R30) {
263 MI.setOpcode(L4_return_map_to_raw_fnew_pt);
264 MI.erase(MI.begin () + 2);
265 MI.erase(MI.begin ());
266 }
267 break;
268 case Hexagon::L4_return_tnew_pnt:
269 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
270 MI.getOperand(2).getReg() == Hexagon::R30) {
271 MI.setOpcode(L4_return_map_to_raw_tnew_pnt);
272 MI.erase(MI.begin () + 2);
273 MI.erase(MI.begin ());
274 }
275 break;
276 case Hexagon::L4_return_fnew_pnt:
277 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
278 MI.getOperand(2).getReg() == Hexagon::R30) {
279 MI.setOpcode(L4_return_map_to_raw_fnew_pnt);
280 MI.erase(MI.begin () + 2);
281 MI.erase(MI.begin ());
282 }
283 break;
284 }
285 }
286}
287
288static void adjustDuplex(MCInst &MI, MCContext &Context) {
289 switch (MI.getOpcode()) {
290 case Hexagon::SA1_setin1:
291 MI.insert(MI.begin() + 1,
292 MCOperand::createExpr(MCConstantExpr::create(-1, Context)));
293 break;
294 case Hexagon::SA1_dec:
295 MI.insert(MI.begin() + 2,
296 MCOperand::createExpr(MCConstantExpr::create(-1, Context)));
297 break;
298 default:
299 break;
300 }
301}
302
303DecodeStatus HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
304 ArrayRef<uint8_t> Bytes,
305 uint64_t Address,
306 raw_ostream &cs,
307 bool &Complete) const {
308 assert(Bytes.size() >= HEXAGON_INSTR_SIZE);
309
310 uint32_t Instruction = support::endian::read32le(Bytes.data());
311
312 auto BundleSize = HexagonMCInstrInfo::bundleSize(MCB);
313 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
314 HexagonII::INST_PARSE_LOOP_END) {
315 if (BundleSize == 0)
316 HexagonMCInstrInfo::setInnerLoop(MCB);
317 else if (BundleSize == 1)
318 HexagonMCInstrInfo::setOuterLoop(MCB);
319 else
320 return DecodeStatus::Fail;
321 }
322
323 CurrentExtender = HexagonMCInstrInfo::extenderForIndex(
324 MCB, HexagonMCInstrInfo::bundleSize(MCB));
325
326 DecodeStatus Result = DecodeStatus::Fail;
327 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
328 HexagonII::INST_PARSE_DUPLEX) {
329 unsigned duplexIClass;
330 uint8_t const *DecodeLow, *DecodeHigh;
331 duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1);
332 switch (duplexIClass) {
333 default:
334 return MCDisassembler::Fail;
335 case 0:
336 DecodeLow = DecoderTableSUBINSN_L132;
337 DecodeHigh = DecoderTableSUBINSN_L132;
338 break;
339 case 1:
340 DecodeLow = DecoderTableSUBINSN_L232;
341 DecodeHigh = DecoderTableSUBINSN_L132;
342 break;
343 case 2:
344 DecodeLow = DecoderTableSUBINSN_L232;
345 DecodeHigh = DecoderTableSUBINSN_L232;
346 break;
347 case 3:
348 DecodeLow = DecoderTableSUBINSN_A32;
349 DecodeHigh = DecoderTableSUBINSN_A32;
350 break;
351 case 4:
352 DecodeLow = DecoderTableSUBINSN_L132;
353 DecodeHigh = DecoderTableSUBINSN_A32;
354 break;
355 case 5:
356 DecodeLow = DecoderTableSUBINSN_L232;
357 DecodeHigh = DecoderTableSUBINSN_A32;
358 break;
359 case 6:
360 DecodeLow = DecoderTableSUBINSN_S132;
361 DecodeHigh = DecoderTableSUBINSN_A32;
362 break;
363 case 7:
364 DecodeLow = DecoderTableSUBINSN_S232;
365 DecodeHigh = DecoderTableSUBINSN_A32;
366 break;
367 case 8:
368 DecodeLow = DecoderTableSUBINSN_S132;
369 DecodeHigh = DecoderTableSUBINSN_L132;
370 break;
371 case 9:
372 DecodeLow = DecoderTableSUBINSN_S132;
373 DecodeHigh = DecoderTableSUBINSN_L232;
374 break;
375 case 10:
376 DecodeLow = DecoderTableSUBINSN_S132;
377 DecodeHigh = DecoderTableSUBINSN_S132;
378 break;
379 case 11:
380 DecodeLow = DecoderTableSUBINSN_S232;
381 DecodeHigh = DecoderTableSUBINSN_S132;
382 break;
383 case 12:
384 DecodeLow = DecoderTableSUBINSN_S232;
385 DecodeHigh = DecoderTableSUBINSN_L132;
386 break;
387 case 13:
388 DecodeLow = DecoderTableSUBINSN_S232;
389 DecodeHigh = DecoderTableSUBINSN_L232;
390 break;
391 case 14:
392 DecodeLow = DecoderTableSUBINSN_S232;
393 DecodeHigh = DecoderTableSUBINSN_S232;
394 break;
395 }
396 MI.setOpcode(Hexagon::DuplexIClass0 + duplexIClass);
397 MCInst *MILow = getContext().createMCInst();
398 MCInst *MIHigh = getContext().createMCInst();
399 auto TmpExtender = CurrentExtender;
400 CurrentExtender =
401 nullptr; // constant extenders in duplex must always be in slot 1
402 Result = decodeInstruction(DecodeLow, *MILow, Instruction & 0x1fff, Address,
403 this, STI);
404 CurrentExtender = TmpExtender;
405 if (Result != DecodeStatus::Success)
406 return DecodeStatus::Fail;
407 adjustDuplex(*MILow, getContext());
408 Result = decodeInstruction(
409 DecodeHigh, *MIHigh, (Instruction >> 16) & 0x1fff, Address, this, STI);
410 if (Result != DecodeStatus::Success)
411 return DecodeStatus::Fail;
412 adjustDuplex(*MIHigh, getContext());
413 MCOperand OPLow = MCOperand::createInst(MILow);
414 MCOperand OPHigh = MCOperand::createInst(MIHigh);
415 MI.addOperand(OPLow);
416 MI.addOperand(OPHigh);
417 Complete = true;
418 } else {
419 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
420 HexagonII::INST_PARSE_PACKET_END)
421 Complete = true;
422
423 if (CurrentExtender != nullptr)
424 Result = decodeInstruction(DecoderTableMustExtend32, MI, Instruction,
425 Address, this, STI);
426
427 if (Result != MCDisassembler::Success)
428 Result = decodeInstruction(DecoderTable32, MI, Instruction, Address, this,
429 STI);
430
431 if (Result != MCDisassembler::Success &&
432 STI.hasFeature(Hexagon::ExtensionHVX))
433 Result = decodeInstruction(DecoderTableEXT_mmvec32, MI, Instruction,
434 Address, this, STI);
435
436 }
437
438 switch (MI.getOpcode()) {
439 case Hexagon::J4_cmpeqn1_f_jumpnv_nt:
440 case Hexagon::J4_cmpeqn1_f_jumpnv_t:
441 case Hexagon::J4_cmpeqn1_fp0_jump_nt:
442 case Hexagon::J4_cmpeqn1_fp0_jump_t:
443 case Hexagon::J4_cmpeqn1_fp1_jump_nt:
444 case Hexagon::J4_cmpeqn1_fp1_jump_t:
445 case Hexagon::J4_cmpeqn1_t_jumpnv_nt:
446 case Hexagon::J4_cmpeqn1_t_jumpnv_t:
447 case Hexagon::J4_cmpeqn1_tp0_jump_nt:
448 case Hexagon::J4_cmpeqn1_tp0_jump_t:
449 case Hexagon::J4_cmpeqn1_tp1_jump_nt:
450 case Hexagon::J4_cmpeqn1_tp1_jump_t:
451 case Hexagon::J4_cmpgtn1_f_jumpnv_nt:
452 case Hexagon::J4_cmpgtn1_f_jumpnv_t:
453 case Hexagon::J4_cmpgtn1_fp0_jump_nt:
454 case Hexagon::J4_cmpgtn1_fp0_jump_t:
455 case Hexagon::J4_cmpgtn1_fp1_jump_nt:
456 case Hexagon::J4_cmpgtn1_fp1_jump_t:
457 case Hexagon::J4_cmpgtn1_t_jumpnv_nt:
458 case Hexagon::J4_cmpgtn1_t_jumpnv_t:
459 case Hexagon::J4_cmpgtn1_tp0_jump_nt:
460 case Hexagon::J4_cmpgtn1_tp0_jump_t:
461 case Hexagon::J4_cmpgtn1_tp1_jump_nt:
462 case Hexagon::J4_cmpgtn1_tp1_jump_t:
463 MI.insert(MI.begin() + 1,
464 MCOperand::createExpr(MCConstantExpr::create(-1, getContext())));
465 break;
466 default:
467 break;
468 }
469
470 if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) {
471 unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI);
472 MCOperand &MCO = MI.getOperand(OpIndex);
473 assert(MCO.isReg() && "New value consumers must be registers");
474 unsigned Register =
475 getContext().getRegisterInfo()->getEncodingValue(MCO.getReg());
476 if ((Register & 0x6) == 0)
477 // HexagonPRM 10.11 Bit 1-2 == 0 is reserved
478 return MCDisassembler::Fail;
479 unsigned Lookback = (Register & 0x6) >> 1;
480 unsigned Offset = 1;
481 bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI);
482 bool PrevVector = false;
483 auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle);
484 auto i = Instructions.end() - 1;
485 for (auto n = Instructions.begin() - 1;; --i, ++Offset) {
486 if (i == n)
487 // Couldn't find producer
488 return MCDisassembler::Fail;
489 bool CurrentVector = HexagonMCInstrInfo::isVector(*MCII, *i->getInst());
490 if (Vector && !CurrentVector)
491 // Skip scalars when calculating distances for vectors
492 ++Lookback;
493 if (HexagonMCInstrInfo::isImmext(*i->getInst()) && (Vector == PrevVector))
494 ++Lookback;
495 PrevVector = CurrentVector;
496 if (Offset == Lookback)
497 break;
498 }
499 auto const &Inst = *i->getInst();
500 bool SubregBit = (Register & 0x1) != 0;
501 if (HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) {
502 // If subreg bit is set we're selecting the second produced newvalue
503 MCRegister Producer =
504 SubregBit
505 ? HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg()
506 : HexagonMCInstrInfo::getNewValueOperand2(*MCII, Inst).getReg();
507 assert(Producer != Hexagon::NoRegister);
508 MCO.setReg(Producer);
509 } else if (HexagonMCInstrInfo::hasNewValue(*MCII, Inst)) {
510 MCRegister Producer =
511 HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg();
512
513 if (HexagonMCInstrInfo::IsVecRegPair(Producer)) {
514 const bool Rev = HexagonMCInstrInfo::IsReverseVecRegPair(Producer);
515 const unsigned ProdPairIndex =
516 Rev ? Producer - Hexagon::WR0 : Producer - Hexagon::W0;
517 if (Rev)
518 SubregBit = !SubregBit;
519 Producer = (ProdPairIndex << 1) + SubregBit + Hexagon::V0;
520 } else if (SubregBit)
521 // Hexagon PRM 10.11 New-value operands
522 // Nt[0] is reserved and should always be encoded as zero.
523 return MCDisassembler::Fail;
524 assert(Producer != Hexagon::NoRegister);
525 MCO.setReg(Producer);
526 } else
527 return MCDisassembler::Fail;
528 }
529
530 if (CurrentExtender != nullptr) {
531 MCInst const &Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI)
532 ? *MI.getOperand(1).getInst()
533 : MI;
534 if (!HexagonMCInstrInfo::isExtendable(*MCII, Inst) &&
535 !HexagonMCInstrInfo::isExtended(*MCII, Inst))
536 return MCDisassembler::Fail;
537 }
538 return Result;
539}
540
541static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo,
542 ArrayRef<MCPhysReg> Table) {
543 if (RegNo < Table.size()) {
544 Inst.addOperand(MCOperand::createReg(Table[RegNo]));
545 return MCDisassembler::Success;
546 }
547
548 return MCDisassembler::Fail;
549}
550
551static DecodeStatus
552DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
553 const MCDisassembler *Decoder) {
554 return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder);
555}
556
557static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
558 uint64_t Address,
559 const MCDisassembler *Decoder) {
560 static const MCPhysReg IntRegDecoderTable[] = {
561 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
562 Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
563 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
564 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
565 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,
566 Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,
567 Hexagon::R30, Hexagon::R31};
568
569 return DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable);
570}
571
572static DecodeStatus
573DecodeGeneralSubRegsRegisterClass(MCInst &Inst, unsigned RegNo,
574 uint64_t Address,
575 const MCDisassembler *Decoder) {
576 static const MCPhysReg GeneralSubRegDecoderTable[] = {
577 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3,
578 Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7,
579 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
580 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
581 };
582
583 return DecodeRegisterClass(Inst, RegNo, GeneralSubRegDecoderTable);
584}
585
586static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
587 uint64_t /*Address*/,
588 const MCDisassembler *Decoder) {
589 static const MCPhysReg HvxVRDecoderTable[] = {
590 Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4,
591 Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9,
592 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14,
593 Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19,
594 Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24,
595 Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29,
596 Hexagon::V30, Hexagon::V31};
597
598 return DecodeRegisterClass(Inst, RegNo, HvxVRDecoderTable);
599}
600
601static DecodeStatus
602DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
603 uint64_t /*Address*/,
604 const MCDisassembler *Decoder) {
605 static const MCPhysReg DoubleRegDecoderTable[] = {
606 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
607 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7,
608 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11,
609 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15};
610
611 return DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable);
612}
613
614static DecodeStatus
615DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo,
616 uint64_t /*Address*/,
617 const MCDisassembler *Decoder) {
618 static const MCPhysReg GeneralDoubleLow8RegDecoderTable[] = {
619 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
620 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11};
621
622 return DecodeRegisterClass(Inst, RegNo, GeneralDoubleLow8RegDecoderTable);
623}
624
625static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
626 uint64_t /*Address*/,
627 const MCDisassembler *Decoder) {
628 static const MCPhysReg HvxWRDecoderTable[] = {
629 Hexagon::W0, Hexagon::WR0, Hexagon::W1, Hexagon::WR1, Hexagon::W2,
630 Hexagon::WR2, Hexagon::W3, Hexagon::WR3, Hexagon::W4, Hexagon::WR4,
631 Hexagon::W5, Hexagon::WR5, Hexagon::W6, Hexagon::WR6, Hexagon::W7,
632 Hexagon::WR7, Hexagon::W8, Hexagon::WR8, Hexagon::W9, Hexagon::WR9,
633 Hexagon::W10, Hexagon::WR10, Hexagon::W11, Hexagon::WR11, Hexagon::W12,
634 Hexagon::WR12, Hexagon::W13, Hexagon::WR13, Hexagon::W14, Hexagon::WR14,
635 Hexagon::W15, Hexagon::WR15,
636 };
637
638 return DecodeRegisterClass(Inst, RegNo, HvxWRDecoderTable);
639}
640
641LLVM_ATTRIBUTE_UNUSED // Suppress warning temporarily.
642 static DecodeStatus
643 DecodeHvxVQRRegisterClass(MCInst &Inst, unsigned RegNo,
644 uint64_t /*Address*/,
645 const MCDisassembler *Decoder) {
646 static const MCPhysReg HvxVQRDecoderTable[] = {
647 Hexagon::VQ0, Hexagon::VQ1, Hexagon::VQ2, Hexagon::VQ3,
648 Hexagon::VQ4, Hexagon::VQ5, Hexagon::VQ6, Hexagon::VQ7};
649
650 return DecodeRegisterClass(Inst, RegNo >> 2, HvxVQRDecoderTable);
651}
652
653static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
654 uint64_t /*Address*/,
655 const MCDisassembler *Decoder) {
656 static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,
657 Hexagon::P2, Hexagon::P3};
658
659 return DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable);
660}
661
662static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
663 uint64_t /*Address*/,
664 const MCDisassembler *Decoder) {
665 static const MCPhysReg HvxQRDecoderTable[] = {Hexagon::Q0, Hexagon::Q1,
666 Hexagon::Q2, Hexagon::Q3};
667
668 return DecodeRegisterClass(Inst, RegNo, HvxQRDecoderTable);
669}
670
671static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
672 uint64_t /*Address*/,
673 const MCDisassembler *Decoder) {
674 using namespace Hexagon;
675
676 static const MCPhysReg CtrlRegDecoderTable[] = {
677 /* 0 */ SA0, LC0, SA1, LC1,
678 /* 4 */ P3_0, C5, M0, M1,
679 /* 8 */ USR, PC, UGP, GP,
680 /* 12 */ CS0, CS1, UPCYCLELO, UPCYCLEHI,
681 /* 16 */ FRAMELIMIT, FRAMEKEY, PKTCOUNTLO, PKTCOUNTHI,
682 /* 20 */ 0, 0, 0, 0,
683 /* 24 */ 0, 0, 0, 0,
684 /* 28 */ 0, 0, UTIMERLO, UTIMERHI
685 };
686
687 if (RegNo >= std::size(CtrlRegDecoderTable))
688 return MCDisassembler::Fail;
689
690 static_assert(NoRegister == 0, "Expecting NoRegister to be 0");
691 if (CtrlRegDecoderTable[RegNo] == NoRegister)
692 return MCDisassembler::Fail;
693
694 unsigned Register = CtrlRegDecoderTable[RegNo];
695 Inst.addOperand(MCOperand::createReg(Register));
696 return MCDisassembler::Success;
697}
698
699static DecodeStatus
700DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/,
701 const MCDisassembler *Decoder) {
702 using namespace Hexagon;
703
704 static const MCPhysReg CtrlReg64DecoderTable[] = {
705 /* 0 */ C1_0, 0, C3_2, 0,
706 /* 4 */ C5_4, 0, C7_6, 0,
707 /* 8 */ C9_8, 0, C11_10, 0,
708 /* 12 */ CS, 0, UPCYCLE, 0,
709 /* 16 */ C17_16, 0, PKTCOUNT, 0,
710 /* 20 */ 0, 0, 0, 0,
711 /* 24 */ 0, 0, 0, 0,
712 /* 28 */ 0, 0, UTIMER, 0
713 };
714
715 if (RegNo >= std::size(CtrlReg64DecoderTable))
716 return MCDisassembler::Fail;
717
718 static_assert(NoRegister == 0, "Expecting NoRegister to be 0");
719 if (CtrlReg64DecoderTable[RegNo] == NoRegister)
720 return MCDisassembler::Fail;
721
722 unsigned Register = CtrlReg64DecoderTable[RegNo];
723 Inst.addOperand(MCOperand::createReg(Register));
724 return MCDisassembler::Success;
725}
726
727static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
728 uint64_t /*Address*/,
729 const MCDisassembler *Decoder) {
730 unsigned Register = 0;
731 switch (RegNo) {
732 case 0:
733 Register = Hexagon::M0;
734 break;
735 case 1:
736 Register = Hexagon::M1;
737 break;
738 default:
739 return MCDisassembler::Fail;
740 }
741 Inst.addOperand(MCOperand::createReg(Register));
742 return MCDisassembler::Success;
743}
744
745static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
746 uint64_t /*Address*/,
747 const MCDisassembler *Decoder) {
748 HexagonDisassembler const &Disassembler = disassembler(Decoder);
749 int64_t FullValue = fullValue(Disassembler, MI, tmp);
750 assert(FullValue >= 0 && "Negative in unsigned decoder");
751 HexagonMCInstrInfo::addConstant(MI, FullValue, Disassembler.getContext());
752 return MCDisassembler::Success;
753}
754
755static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp,
756 uint64_t /*Address*/,
757 const MCDisassembler *Decoder) {
758 HexagonDisassembler const &Disassembler = disassembler(Decoder);
759 unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI);
760 tmp = SignExtend64(tmp, Bits);
761 signedDecoder<32>(MI, tmp, Decoder);
762 return MCDisassembler::Success;
763}
764
765// custom decoder for various jump/call immediates
766static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
767 const MCDisassembler *Decoder) {
768 HexagonDisassembler const &Disassembler = disassembler(Decoder);
769 unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI);
770 // r13_2 is not extendable, so if there are no extent bits, it's r13_2
771 if (Bits == 0)
772 Bits = 15;
773 uint64_t FullValue = fullValue(Disassembler, MI, SignExtend64(tmp, Bits));
774 uint32_t Extended = FullValue + Address;
775 if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, 0, 0,
776 4))
777 HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());
778 return MCDisassembler::Success;
779}
780
781static const uint16_t SysRegDecoderTable[] = {
782 Hexagon::SGP0, Hexagon::SGP1, Hexagon::STID,
783 Hexagon::ELR, Hexagon::BADVA0, Hexagon::BADVA1,
784 Hexagon::SSR, Hexagon::CCR, Hexagon::HTID,
785 Hexagon::BADVA, Hexagon::IMASK, Hexagon::S11,
786 Hexagon::S12, Hexagon::S13, Hexagon::S14,
787 Hexagon::S15, Hexagon::EVB, Hexagon::MODECTL,
788 Hexagon::SYSCFG, Hexagon::S19, Hexagon::S20,
789 Hexagon::VID, Hexagon::S22, Hexagon::S23,
790 Hexagon::S24, Hexagon::S25, Hexagon::S26,
791 Hexagon::CFGBASE, Hexagon::DIAG, Hexagon::REV,
792 Hexagon::PCYCLELO, Hexagon::PCYCLEHI, Hexagon::ISDBST,
793 Hexagon::ISDBCFG0, Hexagon::ISDBCFG1, Hexagon::S35,
794 Hexagon::BRKPTPC0, Hexagon::BRKPTCFG0, Hexagon::BRKPTPC1,
795 Hexagon::BRKPTCFG1, Hexagon::ISDBMBXIN, Hexagon::ISDBMBXOUT,
796 Hexagon::ISDBEN, Hexagon::ISDBGPR, Hexagon::S44,
797 Hexagon::S45, Hexagon::S46, Hexagon::S47,
798 Hexagon::PMUCNT0, Hexagon::PMUCNT1, Hexagon::PMUCNT2,
799 Hexagon::PMUCNT3, Hexagon::PMUEVTCFG, Hexagon::PMUCFG,
800 Hexagon::S54, Hexagon::S55, Hexagon::S56,
801 Hexagon::S57, Hexagon::S58, Hexagon::S59,
802 Hexagon::S60, Hexagon::S61, Hexagon::S62,
803 Hexagon::S63, Hexagon::S64, Hexagon::S65,
804 Hexagon::S66, Hexagon::S67, Hexagon::S68,
805 Hexagon::S69, Hexagon::S70, Hexagon::S71,
806 Hexagon::S72, Hexagon::S73, Hexagon::S74,
807 Hexagon::S75, Hexagon::S76, Hexagon::S77,
808 Hexagon::S78, Hexagon::S79, Hexagon::S80,
809};
810
811static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo,
812 uint64_t /*Address*/,
813 const MCDisassembler *Decoder) {
814 if (RegNo >= std::size(SysRegDecoderTable))
815 return MCDisassembler::Fail;
816
817 if (SysRegDecoderTable[RegNo] == Hexagon::NoRegister)
818 return MCDisassembler::Fail;
819
820 unsigned Register = SysRegDecoderTable[RegNo];
821 Inst.addOperand(MCOperand::createReg(Register));
822 return MCDisassembler::Success;
823}
824
825static const uint16_t SysReg64DecoderTable[] = {
826 Hexagon::SGP1_0, Hexagon::S3_2, Hexagon::S5_4, Hexagon::S7_6,
827 Hexagon::S9_8, Hexagon::S11_10, Hexagon::S13_12, Hexagon::S15_14,
828 Hexagon::S17_16, Hexagon::S19_18, Hexagon::S21_20, Hexagon::S23_22,
829 Hexagon::S25_24, Hexagon::S27_26, Hexagon::S29_28, Hexagon::S31_30,
830 Hexagon::S33_32, Hexagon::S35_34, Hexagon::S37_36, Hexagon::S39_38,
831 Hexagon::S41_40, Hexagon::S43_42, Hexagon::S45_44, Hexagon::S47_46,
832 Hexagon::S49_48, Hexagon::S51_50, Hexagon::S53_52, Hexagon::S55_54,
833 Hexagon::S57_56, Hexagon::S59_58, Hexagon::S61_60, Hexagon::S63_62,
834 Hexagon::S65_64, Hexagon::S67_66, Hexagon::S69_68, Hexagon::S71_70,
835 Hexagon::S73_72, Hexagon::S75_74, Hexagon::S77_76, Hexagon::S79_78,
836};
837
838static DecodeStatus
839DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/,
840 const MCDisassembler *Decoder) {
841 RegNo = RegNo >> 1;
842 if (RegNo >= std::size(SysReg64DecoderTable))
843 return MCDisassembler::Fail;
844
845 if (SysReg64DecoderTable[RegNo] == Hexagon::NoRegister)
846 return MCDisassembler::Fail;
847
848 unsigned Register = SysReg64DecoderTable[RegNo];
849 Inst.addOperand(MCOperand::createReg(Register));
850 return MCDisassembler::Success;
851}
852
853static DecodeStatus
854DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/,
855 const MCDisassembler *Decoder) {
856 using namespace Hexagon;
857
858 static const MCPhysReg GuestRegDecoderTable[] = {
859 /* 0 */ GELR, GSR, GOSP, G3,
860 /* 4 */ G4, G5, G6, G7,
861 /* 8 */ G8, G9, G10, G11,
862 /* 12 */ G12, G13, G14, G15,
863 /* 16 */ GPMUCNT4, GPMUCNT5, GPMUCNT6, GPMUCNT7,
864 /* 20 */ G20, G21, G22, G23,
865 /* 24 */ GPCYCLELO, GPCYCLEHI, GPMUCNT0, GPMUCNT1,
866 /* 28 */ GPMUCNT2, GPMUCNT3, G30, G31
867 };
868
869 if (RegNo >= std::size(GuestRegDecoderTable))
870 return MCDisassembler::Fail;
871 if (GuestRegDecoderTable[RegNo] == Hexagon::NoRegister)
872 return MCDisassembler::Fail;
873
874 unsigned Register = GuestRegDecoderTable[RegNo];
875 Inst.addOperand(MCOperand::createReg(Register));
876 return MCDisassembler::Success;
877}
878
879static DecodeStatus
880DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
881 uint64_t /*Address*/,
882 const MCDisassembler *Decoder) {
883 using namespace Hexagon;
884
885 static const MCPhysReg GuestReg64DecoderTable[] = {
886 /* 0 */ G1_0, 0, G3_2, 0,
887 /* 4 */ G5_4, 0, G7_6, 0,
888 /* 8 */ G9_8, 0, G11_10, 0,
889 /* 12 */ G13_12, 0, G15_14, 0,
890 /* 16 */ G17_16, 0, G19_18, 0,
891 /* 20 */ G21_20, 0, G23_22, 0,
892 /* 24 */ G25_24, 0, G27_26, 0,
893 /* 28 */ G29_28, 0, G31_30, 0
894 };
895
896 if (RegNo >= std::size(GuestReg64DecoderTable))
897 return MCDisassembler::Fail;
898 if (GuestReg64DecoderTable[RegNo] == Hexagon::NoRegister)
899 return MCDisassembler::Fail;
900
901 unsigned Register = GuestReg64DecoderTable[RegNo];
902 Inst.addOperand(MCOperand::createReg(Register));
903 return MCDisassembler::Success;
904}
Success
#define Success
Definition: AArch64Disassembler.cpp:220
LLVM_ATTRIBUTE_UNUSED
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:282
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:128
Size
uint64_t Size
Definition: ELFObjHandler.cpp:81
DecodeIntRegsLow8RegisterClass
static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:552
DecodeGuestRegsRegisterClass
static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:854
DecodeCtrRegsRegisterClass
static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:671
brtargetDecoder
static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:766
DecodePredRegsRegisterClass
static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:653
s32_0ImmDecoder
static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:755
LLVMInitializeHexagonDisassembler
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonDisassembler()
Definition: HexagonDisassembler.cpp:167
DecodeHvxVQRRegisterClass
static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:643
unsignedImmDecoder
static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:745
DecodeHvxVRRegisterClass
static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:586
createHexagonDisassembler
static MCDisassembler * createHexagonDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: HexagonDisassembler.cpp:161
DecodeSysRegs64RegisterClass
static DecodeStatus DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:839
DecodeModRegsRegisterClass
static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:727
SysReg64DecoderTable
static const uint16_t SysReg64DecoderTable[]
Definition: HexagonDisassembler.cpp:825
adjustDuplex
static void adjustDuplex(MCInst &MI, MCContext &Context)
Definition: HexagonDisassembler.cpp:288
DecodeRegisterClass
static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo, ArrayRef< MCPhysReg > Table)
Definition: HexagonDisassembler.cpp:541
DecodeSysRegsRegisterClass
static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:811
DecodeDoubleRegsRegisterClass
static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:602
SysRegDecoderTable
static const uint16_t SysRegDecoderTable[]
Definition: HexagonDisassembler.cpp:781
DecodeGeneralSubRegsRegisterClass
static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:573
DecodeHvxWRRegisterClass
static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:625
DecodeIntRegsRegisterClass
static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:557
DecodeHvxQRRegisterClass
static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:662
DecodeCtrRegs64RegisterClass
static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:700
DecodeGeneralDoubleLow8RegsRegisterClass
static DecodeStatus DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:615
DecodeGuestRegs64RegisterClass
static DecodeStatus DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:880
HEXAGON_MAX_PACKET_SIZE
#define HEXAGON_MAX_PACKET_SIZE
Definition: HexagonMCTargetDesc.h:36
HEXAGON_INSTR_SIZE
#define HEXAGON_INSTR_SIZE
Definition: HexagonMCTargetDesc.h:32
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:111
I
#define I(x, y, z)
Definition: MD5.cpp:58
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
OpIndex
unsigned OpIndex
Definition: SPIRVModuleAnalysis.cpp:63
IntRegDecoderTable
static const unsigned IntRegDecoderTable[]
Definition: SparcDisassembler.cpp:60
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:168
llvm::ArrayRef::data
const T * data() const
Definition: ArrayRef.h:165
llvm::ArrayRef::slice
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.
Definition: ArrayRef.h:198
llvm::HexagonMCChecker
Check for a valid bundle.
Definition: HexagonMCChecker.h:33
llvm::MCConstantExpr::create
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:222
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:83
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:84
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:108
llvm::MCDisassembler::getInstruction
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:185
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:211
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:37
llvm::MCOperand::createExpr
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:163
llvm::MCOperand::createReg
static MCOperand createReg(MCRegister Reg)
Definition: MCInst.h:135
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:142
llvm::MCOperand::setReg
void setReg(MCRegister Reg)
Set the register number.
Definition: MCInst.h:76
llvm::MCOperand::isReg
bool isReg() const
Definition: MCInst.h:62
llvm::MCOperand::getReg
MCRegister getReg() const
Returns the register number.
Definition: MCInst.h:70
llvm::MCOperand::createInst
static MCOperand createInst(const MCInst *Val)
Definition: MCInst.h:170
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:144
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
uint16_t
uint32_t
uint64_t
uint8_t
llvm::HexagonMCInstrInfo::addConstant
void addConstant(MCInst &MI, uint64_t Value, MCContext &Context)
Definition: HexagonMCInstrInfo.cpp:82
llvm::HexagonMCInstrInfo::IsReverseVecRegPair
bool IsReverseVecRegPair(MCRegister VecReg)
Definition: HexagonMCInstrInfo.cpp:699
llvm::HexagonMCInstrInfo::bundleSize
size_t bundleSize(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:116
llvm::HexagonMCInstrInfo::isDuplex
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:624
llvm::HexagonMCInstrInfo::getExtentBits
unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:340
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Definition: HexagonMCInstrInfo.cpp:670
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Definition: HexagonMCInstrInfo.cpp:379
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