LLVM 22.0.0git
HexagonDisassembler.cpp
Go to the documentation of this file.
1//===- HexagonDisassembler.cpp - Disassembler for Hexagon ISA -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "MCTargetDesc/HexagonBaseInfo.h"
10#include "MCTargetDesc/HexagonMCChecker.h"
11#include "MCTargetDesc/HexagonMCInstrInfo.h"
12#include "MCTargetDesc/HexagonMCTargetDesc.h"
13#include "TargetInfo/HexagonTargetInfo.h"
14#include "llvm/ADT/ArrayRef.h"
15#include "llvm/MC/MCContext.h"
16#include "llvm/MC/MCDecoder.h"
17#include "llvm/MC/MCDecoderOps.h"
18#include "llvm/MC/MCDisassembler/MCDisassembler.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCInstrInfo.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/MC/TargetRegistry.h"
25#include "llvm/Support/Compiler.h"
26#include "llvm/Support/Endian.h"
27#include "llvm/Support/MathExtras.h"
28#include "llvm/Support/raw_ostream.h"
29#include <cassert>
30#include <cstddef>
31#include <cstdint>
32#include <memory>
33
34#define DEBUG_TYPE "hexagon-disassembler"
35
36using namespace llvm;
37using namespace Hexagon;
38
39using DecodeStatus = MCDisassembler::DecodeStatus;
40
41namespace {
42
43/// Hexagon disassembler for all Hexagon platforms.
44class HexagonDisassembler : public MCDisassembler {
45public:
46 std::unique_ptr<MCInstrInfo const> const MCII;
47 mutable std::unique_ptr<MCInst> CurrentBundle;
48 mutable MCInst const *CurrentExtender;
49
50 HexagonDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
51 MCInstrInfo const *MCII)
52 : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(nullptr),
53 CurrentExtender(nullptr) {}
54
55 DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB,
56 ArrayRef<uint8_t> Bytes, uint64_t Address,
57 raw_ostream &CStream, bool &Complete) const;
58 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
59 ArrayRef<uint8_t> Bytes, uint64_t Address,
60 raw_ostream &CStream) const override;
61
62 DecodeStatus getInstructionBundle(MCInst &Instr, uint64_t &Size,
63 ArrayRef<uint8_t> Bytes, uint64_t Address,
64 raw_ostream &CStream) const override;
65
66 void remapInstruction(MCInst &Instr) const;
67
68private:
69 bool makeBundle(ArrayRef<uint8_t> Bytes, uint64_t Address,
70 uint64_t &BytesToSkip, raw_ostream &CS) const;
71
72 void resetBundle() const {
73 CurrentBundle.reset();
74 CurrentInstruction = nullptr;
75 }
76
77 mutable MCOperand *CurrentInstruction = nullptr;
78};
79
80static uint64_t fullValue(HexagonDisassembler const &Disassembler, MCInst &MI,
81 int64_t Value) {
82 MCInstrInfo MCII = *Disassembler.MCII;
83 if (!Disassembler.CurrentExtender ||
84 MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI))
85 return Value;
86 unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
87 uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f;
88 int64_t Bits;
89 bool Success =
90 Disassembler.CurrentExtender->getOperand(0).getExpr()->evaluateAsAbsolute(
91 Bits);
92 assert(Success);
93 (void)Success;
94 uint64_t Upper26 = static_cast<uint64_t>(Bits);
95 uint64_t Operand = Upper26 | Lower6;
96 return Operand;
97}
98static HexagonDisassembler const &disassembler(const MCDisassembler *Decoder) {
99 return *static_cast<HexagonDisassembler const *>(Decoder);
100}
101template <size_t T>
102static void signedDecoder(MCInst &MI, unsigned tmp,
103 const MCDisassembler *Decoder) {
104 HexagonDisassembler const &Disassembler = disassembler(Decoder);
105 int64_t FullValue = fullValue(Disassembler, MI, SignExtend64<T>(tmp));
106 int64_t Extended = SignExtend64<32>(FullValue);
107 HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());
108}
109}
110
111// Forward declare these because the auto-generated code will reference them.
112// Definitions are further down.
113
114static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
115 uint64_t Address,
116 const MCDisassembler *Decoder);
117static DecodeStatus
118DecodeGeneralSubRegsRegisterClass(MCInst &Inst, unsigned RegNo,
119 uint64_t Address,
120 const MCDisassembler *Decoder);
121static DecodeStatus
122DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
123 const MCDisassembler *Decoder);
124static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
125 uint64_t Address,
126 const MCDisassembler *Decoder);
127static DecodeStatus
128DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
129 const MCDisassembler *Decoder);
130static DecodeStatus
131DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo,
132 uint64_t Address,
133 const MCDisassembler *Decoder);
134static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
135 uint64_t Address,
136 const MCDisassembler *Decoder);
137static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst, unsigned RegNo,
138 uint64_t Address,
139 const MCDisassembler *Decoder);
140static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
141 uint64_t Address,
142 const MCDisassembler *Decoder);
143static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
144 uint64_t Address,
145 const MCDisassembler *Decoder);
146static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
147 uint64_t Address,
148 const MCDisassembler *Decoder);
149static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo,
150 uint64_t Address,
151 const MCDisassembler *Decoder);
152static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo,
153 uint64_t Address,
154 const MCDisassembler *Decoder);
155static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
156 uint64_t Address,
157 const MCDisassembler *Decoder);
158static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
159 uint64_t Address,
160 const MCDisassembler *Decoder);
161static DecodeStatus
162DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
163 const MCDisassembler *Decoder);
164static DecodeStatus DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
165 uint64_t Address,
166 const MCDisassembler *Decoder);
167
168static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
169 uint64_t Address,
170 const MCDisassembler *Decoder);
171static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp,
172 uint64_t /*Address*/,
173 const MCDisassembler *Decoder);
174static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
175 const MCDisassembler *Decoder);
176#include "HexagonDepDecoders.inc"
177#include "HexagonGenDisassemblerTables.inc"
178
179static MCDisassembler *createHexagonDisassembler(const Target &T,
180 const MCSubtargetInfo &STI,
181 MCContext &Ctx) {
182 return new HexagonDisassembler(STI, Ctx, T.createMCInstrInfo());
183}
184
185extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
186LLVMInitializeHexagonDisassembler() {
187 TargetRegistry::RegisterMCDisassembler(getTheHexagonTarget(),
188 createHexagonDisassembler);
189}
190
191bool HexagonDisassembler::makeBundle(ArrayRef<uint8_t> Bytes, uint64_t Address,
192 uint64_t &BytesToSkip,
193 raw_ostream &CS) const {
194 bool Complete = false;
195 DecodeStatus Result = DecodeStatus::Success;
196
197 CurrentBundle.reset(new MCInst);
198 CurrentBundle->setOpcode(Hexagon::BUNDLE);
199 CurrentBundle->addOperand(MCOperand::createImm(0));
200 while (Result == Success && !Complete) {
201 if (Bytes.size() < HEXAGON_INSTR_SIZE)
202 return false;
203 MCInst *Inst = getContext().createMCInst();
204 Result = getSingleInstruction(*Inst, *CurrentBundle, Bytes, Address, CS,
205 Complete);
206 CurrentBundle->addOperand(MCOperand::createInst(Inst));
207 BytesToSkip += HEXAGON_INSTR_SIZE;
208 Bytes = Bytes.slice(HEXAGON_INSTR_SIZE);
209 }
210 if (Result == MCDisassembler::Fail)
211 return false;
212 if (BytesToSkip > HEXAGON_MAX_PACKET_SIZE)
213 return false;
214
215 const auto ArchSTI = Hexagon_MC::getArchSubtarget(&STI);
216 const auto STI_ = (ArchSTI != nullptr) ? *ArchSTI : STI;
217 HexagonMCChecker Checker(getContext(), *MCII, STI_, *CurrentBundle,
218 *getContext().getRegisterInfo(), false);
219 if (!Checker.check())
220 return false;
221 remapInstruction(*CurrentBundle);
222 return true;
223}
224
225DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
226 ArrayRef<uint8_t> Bytes,
227 uint64_t Address,
228 raw_ostream &CS) const {
229 CommentStream = &CS;
230
231 Size = 0;
232 uint64_t BytesToSkip = 0;
233
234 if (!CurrentBundle) {
235 if (!makeBundle(Bytes, Address, BytesToSkip, CS)) {
236 Size = BytesToSkip;
237 resetBundle();
238 return MCDisassembler::Fail;
239 }
240 CurrentInstruction = (CurrentBundle->begin() + 1);
241 }
242
243 MI = *(CurrentInstruction->getInst());
244 Size = HEXAGON_INSTR_SIZE;
245 if (++CurrentInstruction == CurrentBundle->end())
246 resetBundle();
247 return MCDisassembler::Success;
248}
249
250DecodeStatus HexagonDisassembler::getInstructionBundle(MCInst &MI,
251 uint64_t &Size,
252 ArrayRef<uint8_t> Bytes,
253 uint64_t Address,
254 raw_ostream &CS) const {
255 CommentStream = &CS;
256 Size = 0;
257 uint64_t BytesToSkip = 0;
258 assert(!CurrentBundle);
259
260 if (!makeBundle(Bytes, Address, BytesToSkip, CS)) {
261 Size = BytesToSkip;
262 resetBundle();
263 return MCDisassembler::Fail;
264 }
265
266 MI = *CurrentBundle;
267 Size = HEXAGON_INSTR_SIZE * HexagonMCInstrInfo::bundleSize(MI);
268 resetBundle();
269
270 return Success;
271}
272
273void HexagonDisassembler::remapInstruction(MCInst &Instr) const {
274 for (auto I: HexagonMCInstrInfo::bundleInstructions(Instr)) {
275 auto &MI = const_cast<MCInst &>(*I.getInst());
276 switch (MI.getOpcode()) {
277 case Hexagon::S2_allocframe:
278 if (MI.getOperand(0).getReg() == Hexagon::R29) {
279 MI.setOpcode(Hexagon::S6_allocframe_to_raw);
280 MI.erase(MI.begin () + 1);
281 MI.erase(MI.begin ());
282 }
283 break;
284 case Hexagon::L2_deallocframe:
285 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
286 MI.getOperand(1).getReg() == Hexagon::R30) {
287 MI.setOpcode(L6_deallocframe_map_to_raw);
288 MI.erase(MI.begin () + 1);
289 MI.erase(MI.begin ());
290 }
291 break;
292 case Hexagon::L4_return:
293 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
294 MI.getOperand(1).getReg() == Hexagon::R30) {
295 MI.setOpcode(L6_return_map_to_raw);
296 MI.erase(MI.begin () + 1);
297 MI.erase(MI.begin ());
298 }
299 break;
300 case Hexagon::L4_return_t:
301 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
302 MI.getOperand(2).getReg() == Hexagon::R30) {
303 MI.setOpcode(L4_return_map_to_raw_t);
304 MI.erase(MI.begin () + 2);
305 MI.erase(MI.begin ());
306 }
307 break;
308 case Hexagon::L4_return_f:
309 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
310 MI.getOperand(2).getReg() == Hexagon::R30) {
311 MI.setOpcode(L4_return_map_to_raw_f);
312 MI.erase(MI.begin () + 2);
313 MI.erase(MI.begin ());
314 }
315 break;
316 case Hexagon::L4_return_tnew_pt:
317 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
318 MI.getOperand(2).getReg() == Hexagon::R30) {
319 MI.setOpcode(L4_return_map_to_raw_tnew_pt);
320 MI.erase(MI.begin () + 2);
321 MI.erase(MI.begin ());
322 }
323 break;
324 case Hexagon::L4_return_fnew_pt:
325 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
326 MI.getOperand(2).getReg() == Hexagon::R30) {
327 MI.setOpcode(L4_return_map_to_raw_fnew_pt);
328 MI.erase(MI.begin () + 2);
329 MI.erase(MI.begin ());
330 }
331 break;
332 case Hexagon::L4_return_tnew_pnt:
333 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
334 MI.getOperand(2).getReg() == Hexagon::R30) {
335 MI.setOpcode(L4_return_map_to_raw_tnew_pnt);
336 MI.erase(MI.begin () + 2);
337 MI.erase(MI.begin ());
338 }
339 break;
340 case Hexagon::L4_return_fnew_pnt:
341 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
342 MI.getOperand(2).getReg() == Hexagon::R30) {
343 MI.setOpcode(L4_return_map_to_raw_fnew_pnt);
344 MI.erase(MI.begin () + 2);
345 MI.erase(MI.begin ());
346 }
347 break;
348 }
349 }
350}
351
352static void adjustDuplex(MCInst &MI, MCContext &Context) {
353 switch (MI.getOpcode()) {
354 case Hexagon::SA1_setin1:
355 MI.insert(MI.begin() + 1,
356 MCOperand::createExpr(MCConstantExpr::create(-1, Context)));
357 break;
358 case Hexagon::SA1_dec:
359 MI.insert(MI.begin() + 2,
360 MCOperand::createExpr(MCConstantExpr::create(-1, Context)));
361 break;
362 default:
363 break;
364 }
365}
366
367DecodeStatus HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
368 ArrayRef<uint8_t> Bytes,
369 uint64_t Address,
370 raw_ostream &cs,
371 bool &Complete) const {
372 assert(Bytes.size() >= HEXAGON_INSTR_SIZE);
373
374 uint32_t Instruction = support::endian::read32le(Bytes.data());
375
376 auto BundleSize = HexagonMCInstrInfo::bundleSize(MCB);
377 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
378 HexagonII::INST_PARSE_LOOP_END) {
379 if (BundleSize == 0)
380 HexagonMCInstrInfo::setInnerLoop(MCB);
381 else if (BundleSize == 1)
382 HexagonMCInstrInfo::setOuterLoop(MCB);
383 else
384 return DecodeStatus::Fail;
385 }
386
387 CurrentExtender = HexagonMCInstrInfo::extenderForIndex(
388 MCB, HexagonMCInstrInfo::bundleSize(MCB));
389
390 DecodeStatus Result = DecodeStatus::Fail;
391 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
392 HexagonII::INST_PARSE_DUPLEX) {
393 unsigned duplexIClass;
394 uint8_t const *DecodeLow, *DecodeHigh;
395 duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1);
396 switch (duplexIClass) {
397 default:
398 return MCDisassembler::Fail;
399 case 0:
400 DecodeLow = DecoderTableSUBINSN_L132;
401 DecodeHigh = DecoderTableSUBINSN_L132;
402 break;
403 case 1:
404 DecodeLow = DecoderTableSUBINSN_L232;
405 DecodeHigh = DecoderTableSUBINSN_L132;
406 break;
407 case 2:
408 DecodeLow = DecoderTableSUBINSN_L232;
409 DecodeHigh = DecoderTableSUBINSN_L232;
410 break;
411 case 3:
412 DecodeLow = DecoderTableSUBINSN_A32;
413 DecodeHigh = DecoderTableSUBINSN_A32;
414 break;
415 case 4:
416 DecodeLow = DecoderTableSUBINSN_L132;
417 DecodeHigh = DecoderTableSUBINSN_A32;
418 break;
419 case 5:
420 DecodeLow = DecoderTableSUBINSN_L232;
421 DecodeHigh = DecoderTableSUBINSN_A32;
422 break;
423 case 6:
424 DecodeLow = DecoderTableSUBINSN_S132;
425 DecodeHigh = DecoderTableSUBINSN_A32;
426 break;
427 case 7:
428 DecodeLow = DecoderTableSUBINSN_S232;
429 DecodeHigh = DecoderTableSUBINSN_A32;
430 break;
431 case 8:
432 DecodeLow = DecoderTableSUBINSN_S132;
433 DecodeHigh = DecoderTableSUBINSN_L132;
434 break;
435 case 9:
436 DecodeLow = DecoderTableSUBINSN_S132;
437 DecodeHigh = DecoderTableSUBINSN_L232;
438 break;
439 case 10:
440 DecodeLow = DecoderTableSUBINSN_S132;
441 DecodeHigh = DecoderTableSUBINSN_S132;
442 break;
443 case 11:
444 DecodeLow = DecoderTableSUBINSN_S232;
445 DecodeHigh = DecoderTableSUBINSN_S132;
446 break;
447 case 12:
448 DecodeLow = DecoderTableSUBINSN_S232;
449 DecodeHigh = DecoderTableSUBINSN_L132;
450 break;
451 case 13:
452 DecodeLow = DecoderTableSUBINSN_S232;
453 DecodeHigh = DecoderTableSUBINSN_L232;
454 break;
455 case 14:
456 DecodeLow = DecoderTableSUBINSN_S232;
457 DecodeHigh = DecoderTableSUBINSN_S232;
458 break;
459 }
460 MI.setOpcode(Hexagon::DuplexIClass0 + duplexIClass);
461 MCInst *MILow = getContext().createMCInst();
462 MCInst *MIHigh = getContext().createMCInst();
463 auto TmpExtender = CurrentExtender;
464 CurrentExtender =
465 nullptr; // constant extenders in duplex must always be in slot 1
466 Result = decodeInstruction(DecodeLow, *MILow, Instruction & 0x1fff, Address,
467 this, STI);
468 CurrentExtender = TmpExtender;
469 if (Result != DecodeStatus::Success)
470 return DecodeStatus::Fail;
471 adjustDuplex(*MILow, getContext());
472 Result = decodeInstruction(
473 DecodeHigh, *MIHigh, (Instruction >> 16) & 0x1fff, Address, this, STI);
474 if (Result != DecodeStatus::Success)
475 return DecodeStatus::Fail;
476 adjustDuplex(*MIHigh, getContext());
477 MCOperand OPLow = MCOperand::createInst(MILow);
478 MCOperand OPHigh = MCOperand::createInst(MIHigh);
479 MI.addOperand(OPLow);
480 MI.addOperand(OPHigh);
481 Complete = true;
482 } else {
483 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
484 HexagonII::INST_PARSE_PACKET_END)
485 Complete = true;
486
487 if (CurrentExtender != nullptr)
488 Result = decodeInstruction(DecoderTableMustExtend32, MI, Instruction,
489 Address, this, STI);
490
491 if (Result != MCDisassembler::Success)
492 Result = decodeInstruction(DecoderTable32, MI, Instruction, Address, this,
493 STI);
494
495 if (Result != MCDisassembler::Success &&
496 STI.hasFeature(Hexagon::ExtensionHVX))
497 Result = decodeInstruction(DecoderTableEXT_mmvec32, MI, Instruction,
498 Address, this, STI);
499
500 }
501
502 switch (MI.getOpcode()) {
503 case Hexagon::J4_cmpeqn1_f_jumpnv_nt:
504 case Hexagon::J4_cmpeqn1_f_jumpnv_t:
505 case Hexagon::J4_cmpeqn1_fp0_jump_nt:
506 case Hexagon::J4_cmpeqn1_fp0_jump_t:
507 case Hexagon::J4_cmpeqn1_fp1_jump_nt:
508 case Hexagon::J4_cmpeqn1_fp1_jump_t:
509 case Hexagon::J4_cmpeqn1_t_jumpnv_nt:
510 case Hexagon::J4_cmpeqn1_t_jumpnv_t:
511 case Hexagon::J4_cmpeqn1_tp0_jump_nt:
512 case Hexagon::J4_cmpeqn1_tp0_jump_t:
513 case Hexagon::J4_cmpeqn1_tp1_jump_nt:
514 case Hexagon::J4_cmpeqn1_tp1_jump_t:
515 case Hexagon::J4_cmpgtn1_f_jumpnv_nt:
516 case Hexagon::J4_cmpgtn1_f_jumpnv_t:
517 case Hexagon::J4_cmpgtn1_fp0_jump_nt:
518 case Hexagon::J4_cmpgtn1_fp0_jump_t:
519 case Hexagon::J4_cmpgtn1_fp1_jump_nt:
520 case Hexagon::J4_cmpgtn1_fp1_jump_t:
521 case Hexagon::J4_cmpgtn1_t_jumpnv_nt:
522 case Hexagon::J4_cmpgtn1_t_jumpnv_t:
523 case Hexagon::J4_cmpgtn1_tp0_jump_nt:
524 case Hexagon::J4_cmpgtn1_tp0_jump_t:
525 case Hexagon::J4_cmpgtn1_tp1_jump_nt:
526 case Hexagon::J4_cmpgtn1_tp1_jump_t:
527 MI.insert(MI.begin() + 1,
528 MCOperand::createExpr(MCConstantExpr::create(-1, getContext())));
529 break;
530 case Hexagon::Y4_crswap10:
531 MI.addOperand(MCOperand::createReg(Hexagon::SGP1_0));
532 break;
533 default:
534 break;
535 }
536
537 if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) {
538 unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI);
539 MCOperand &MCO = MI.getOperand(OpIndex);
540 assert(MCO.isReg() && "New value consumers must be registers");
541 unsigned Register =
542 getContext().getRegisterInfo()->getEncodingValue(MCO.getReg());
543 if ((Register & 0x6) == 0)
544 // HexagonPRM 10.11 Bit 1-2 == 0 is reserved
545 return MCDisassembler::Fail;
546 unsigned Lookback = (Register & 0x6) >> 1;
547 unsigned Offset = 1;
548 bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI);
549 bool PrevVector = false;
550 auto Instructions = HexagonMCInstrInfo::bundleInstructions(*CurrentBundle);
551 auto i = Instructions.end() - 1;
552 for (auto n = Instructions.begin() - 1;; --i, ++Offset) {
553 if (i == n)
554 // Couldn't find producer
555 return MCDisassembler::Fail;
556 bool CurrentVector = HexagonMCInstrInfo::isVector(*MCII, *i->getInst());
557 if (Vector && !CurrentVector)
558 // Skip scalars when calculating distances for vectors
559 ++Lookback;
560 if (HexagonMCInstrInfo::isImmext(*i->getInst()) && (Vector == PrevVector))
561 ++Lookback;
562 PrevVector = CurrentVector;
563 if (Offset == Lookback)
564 break;
565 }
566 auto const &Inst = *i->getInst();
567 bool SubregBit = (Register & 0x1) != 0;
568 if (HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) {
569 // If subreg bit is set we're selecting the second produced newvalue
570 MCRegister Producer =
571 SubregBit
572 ? HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg()
573 : HexagonMCInstrInfo::getNewValueOperand2(*MCII, Inst).getReg();
574 assert(Producer != Hexagon::NoRegister);
575 MCO.setReg(Producer);
576 } else if (HexagonMCInstrInfo::hasNewValue(*MCII, Inst)) {
577 MCRegister Producer =
578 HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg();
579
580 if (HexagonMCInstrInfo::IsVecRegPair(Producer)) {
581 const bool Rev = HexagonMCInstrInfo::IsReverseVecRegPair(Producer);
582 const unsigned ProdPairIndex =
583 Rev ? Producer - Hexagon::WR0 : Producer - Hexagon::W0;
584 if (Rev)
585 SubregBit = !SubregBit;
586 Producer = (ProdPairIndex << 1) + SubregBit + Hexagon::V0;
587 } else if (SubregBit)
588 // Hexagon PRM 10.11 New-value operands
589 // Nt[0] is reserved and should always be encoded as zero.
590 return MCDisassembler::Fail;
591 assert(Producer != Hexagon::NoRegister);
592 MCO.setReg(Producer);
593 } else
594 return MCDisassembler::Fail;
595 }
596
597 if (CurrentExtender != nullptr) {
598 MCInst const &Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI)
599 ? *MI.getOperand(1).getInst()
600 : MI;
601 if (!HexagonMCInstrInfo::isExtendable(*MCII, Inst) &&
602 !HexagonMCInstrInfo::isExtended(*MCII, Inst))
603 return MCDisassembler::Fail;
604 }
605 return Result;
606}
607
608static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo,
609 ArrayRef<MCPhysReg> Table) {
610 if (RegNo < Table.size()) {
611 Inst.addOperand(MCOperand::createReg(Table[RegNo]));
612 return MCDisassembler::Success;
613 }
614
615 return MCDisassembler::Fail;
616}
617
618static DecodeStatus
619DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
620 const MCDisassembler *Decoder) {
621 return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder);
622}
623
624static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
625 uint64_t Address,
626 const MCDisassembler *Decoder) {
627 static const MCPhysReg IntRegDecoderTable[] = {
628 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
629 Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
630 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
631 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
632 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,
633 Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,
634 Hexagon::R30, Hexagon::R31};
635
636 return DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable);
637}
638
639static DecodeStatus
640DecodeGeneralSubRegsRegisterClass(MCInst &Inst, unsigned RegNo,
641 uint64_t Address,
642 const MCDisassembler *Decoder) {
643 static const MCPhysReg GeneralSubRegDecoderTable[] = {
644 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3,
645 Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7,
646 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
647 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
648 };
649
650 return DecodeRegisterClass(Inst, RegNo, GeneralSubRegDecoderTable);
651}
652
653static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
654 uint64_t /*Address*/,
655 const MCDisassembler *Decoder) {
656 static const MCPhysReg HvxVRDecoderTable[] = {
657 Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4,
658 Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9,
659 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14,
660 Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19,
661 Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24,
662 Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29,
663 Hexagon::V30, Hexagon::V31};
664
665 return DecodeRegisterClass(Inst, RegNo, HvxVRDecoderTable);
666}
667
668static DecodeStatus
669DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
670 uint64_t /*Address*/,
671 const MCDisassembler *Decoder) {
672 static const MCPhysReg DoubleRegDecoderTable[] = {
673 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
674 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7,
675 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11,
676 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15};
677
678 return DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable);
679}
680
681static DecodeStatus
682DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo,
683 uint64_t /*Address*/,
684 const MCDisassembler *Decoder) {
685 static const MCPhysReg GeneralDoubleLow8RegDecoderTable[] = {
686 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
687 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11};
688
689 return DecodeRegisterClass(Inst, RegNo, GeneralDoubleLow8RegDecoderTable);
690}
691
692static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
693 uint64_t /*Address*/,
694 const MCDisassembler *Decoder) {
695 static const MCPhysReg HvxWRDecoderTable[] = {
696 Hexagon::W0, Hexagon::WR0, Hexagon::W1, Hexagon::WR1, Hexagon::W2,
697 Hexagon::WR2, Hexagon::W3, Hexagon::WR3, Hexagon::W4, Hexagon::WR4,
698 Hexagon::W5, Hexagon::WR5, Hexagon::W6, Hexagon::WR6, Hexagon::W7,
699 Hexagon::WR7, Hexagon::W8, Hexagon::WR8, Hexagon::W9, Hexagon::WR9,
700 Hexagon::W10, Hexagon::WR10, Hexagon::W11, Hexagon::WR11, Hexagon::W12,
701 Hexagon::WR12, Hexagon::W13, Hexagon::WR13, Hexagon::W14, Hexagon::WR14,
702 Hexagon::W15, Hexagon::WR15,
703 };
704
705 return DecodeRegisterClass(Inst, RegNo, HvxWRDecoderTable);
706}
707
708LLVM_ATTRIBUTE_UNUSED // Suppress warning temporarily.
709 static DecodeStatus
710 DecodeHvxVQRRegisterClass(MCInst &Inst, unsigned RegNo,
711 uint64_t /*Address*/,
712 const MCDisassembler *Decoder) {
713 static const MCPhysReg HvxVQRDecoderTable[] = {
714 Hexagon::VQ0, Hexagon::VQ1, Hexagon::VQ2, Hexagon::VQ3,
715 Hexagon::VQ4, Hexagon::VQ5, Hexagon::VQ6, Hexagon::VQ7};
716
717 return DecodeRegisterClass(Inst, RegNo >> 2, HvxVQRDecoderTable);
718}
719
720static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
721 uint64_t /*Address*/,
722 const MCDisassembler *Decoder) {
723 static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,
724 Hexagon::P2, Hexagon::P3};
725
726 return DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable);
727}
728
729static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
730 uint64_t /*Address*/,
731 const MCDisassembler *Decoder) {
732 static const MCPhysReg HvxQRDecoderTable[] = {Hexagon::Q0, Hexagon::Q1,
733 Hexagon::Q2, Hexagon::Q3};
734
735 return DecodeRegisterClass(Inst, RegNo, HvxQRDecoderTable);
736}
737
738static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
739 uint64_t /*Address*/,
740 const MCDisassembler *Decoder) {
741 using namespace Hexagon;
742
743 static const MCPhysReg CtrlRegDecoderTable[] = {
744 /* 0 */ SA0, LC0, SA1, LC1,
745 /* 4 */ P3_0, C5, M0, M1,
746 /* 8 */ USR, PC, UGP, GP,
747 /* 12 */ CS0, CS1, UPCYCLELO, UPCYCLEHI,
748 /* 16 */ FRAMELIMIT, FRAMEKEY, PKTCOUNTLO, PKTCOUNTHI,
749 /* 20 */ 0, 0, 0, 0,
750 /* 24 */ 0, 0, 0, 0,
751 /* 28 */ 0, 0, UTIMERLO, UTIMERHI
752 };
753
754 if (RegNo >= std::size(CtrlRegDecoderTable))
755 return MCDisassembler::Fail;
756
757 static_assert(NoRegister == 0, "Expecting NoRegister to be 0");
758 if (CtrlRegDecoderTable[RegNo] == NoRegister)
759 return MCDisassembler::Fail;
760
761 unsigned Register = CtrlRegDecoderTable[RegNo];
762 Inst.addOperand(MCOperand::createReg(Register));
763 return MCDisassembler::Success;
764}
765
766static DecodeStatus
767DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/,
768 const MCDisassembler *Decoder) {
769 using namespace Hexagon;
770
771 static const MCPhysReg CtrlReg64DecoderTable[] = {
772 /* 0 */ C1_0, 0, C3_2, 0,
773 /* 4 */ C5_4, 0, C7_6, 0,
774 /* 8 */ C9_8, 0, C11_10, 0,
775 /* 12 */ CS, 0, UPCYCLE, 0,
776 /* 16 */ C17_16, 0, PKTCOUNT, 0,
777 /* 20 */ 0, 0, 0, 0,
778 /* 24 */ 0, 0, 0, 0,
779 /* 28 */ 0, 0, UTIMER, 0
780 };
781
782 if (RegNo >= std::size(CtrlReg64DecoderTable))
783 return MCDisassembler::Fail;
784
785 static_assert(NoRegister == 0, "Expecting NoRegister to be 0");
786 if (CtrlReg64DecoderTable[RegNo] == NoRegister)
787 return MCDisassembler::Fail;
788
789 unsigned Register = CtrlReg64DecoderTable[RegNo];
790 Inst.addOperand(MCOperand::createReg(Register));
791 return MCDisassembler::Success;
792}
793
794static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
795 uint64_t /*Address*/,
796 const MCDisassembler *Decoder) {
797 unsigned Register = 0;
798 switch (RegNo) {
799 case 0:
800 Register = Hexagon::M0;
801 break;
802 case 1:
803 Register = Hexagon::M1;
804 break;
805 default:
806 return MCDisassembler::Fail;
807 }
808 Inst.addOperand(MCOperand::createReg(Register));
809 return MCDisassembler::Success;
810}
811
812static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
813 uint64_t /*Address*/,
814 const MCDisassembler *Decoder) {
815 HexagonDisassembler const &Disassembler = disassembler(Decoder);
816 int64_t FullValue = fullValue(Disassembler, MI, tmp);
817 assert(FullValue >= 0 && "Negative in unsigned decoder");
818 HexagonMCInstrInfo::addConstant(MI, FullValue, Disassembler.getContext());
819 return MCDisassembler::Success;
820}
821
822static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp,
823 uint64_t /*Address*/,
824 const MCDisassembler *Decoder) {
825 HexagonDisassembler const &Disassembler = disassembler(Decoder);
826 unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI);
827 tmp = SignExtend64(tmp, Bits);
828 signedDecoder<32>(MI, tmp, Decoder);
829 return MCDisassembler::Success;
830}
831
832// custom decoder for various jump/call immediates
833static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
834 const MCDisassembler *Decoder) {
835 HexagonDisassembler const &Disassembler = disassembler(Decoder);
836 unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI);
837 // r13_2 is not extendable, so if there are no extent bits, it's r13_2
838 if (Bits == 0)
839 Bits = 15;
840 uint64_t FullValue = fullValue(Disassembler, MI, SignExtend64(tmp, Bits));
841 uint32_t Extended = FullValue + Address;
842 if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, 0, 0,
843 4))
844 HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());
845 return MCDisassembler::Success;
846}
847
848static const uint16_t SysRegDecoderTable[] = {
849 Hexagon::SGP0, Hexagon::SGP1, Hexagon::STID,
850 Hexagon::ELR, Hexagon::BADVA0, Hexagon::BADVA1,
851 Hexagon::SSR, Hexagon::CCR, Hexagon::HTID,
852 Hexagon::BADVA, Hexagon::IMASK, Hexagon::S11,
853 Hexagon::S12, Hexagon::S13, Hexagon::S14,
854 Hexagon::S15, Hexagon::EVB, Hexagon::MODECTL,
855 Hexagon::SYSCFG, Hexagon::S19, Hexagon::S20,
856 Hexagon::VID, Hexagon::S22, Hexagon::S23,
857 Hexagon::S24, Hexagon::S25, Hexagon::S26,
858 Hexagon::CFGBASE, Hexagon::DIAG, Hexagon::REV,
859 Hexagon::PCYCLELO, Hexagon::PCYCLEHI, Hexagon::ISDBST,
860 Hexagon::ISDBCFG0, Hexagon::ISDBCFG1, Hexagon::S35,
861 Hexagon::BRKPTPC0, Hexagon::BRKPTCFG0, Hexagon::BRKPTPC1,
862 Hexagon::BRKPTCFG1, Hexagon::ISDBMBXIN, Hexagon::ISDBMBXOUT,
863 Hexagon::ISDBEN, Hexagon::ISDBGPR, Hexagon::S44,
864 Hexagon::S45, Hexagon::S46, Hexagon::S47,
865 Hexagon::PMUCNT0, Hexagon::PMUCNT1, Hexagon::PMUCNT2,
866 Hexagon::PMUCNT3, Hexagon::PMUEVTCFG, Hexagon::PMUCFG,
867 Hexagon::S54, Hexagon::S55, Hexagon::S56,
868 Hexagon::S57, Hexagon::S58, Hexagon::S59,
869 Hexagon::S60, Hexagon::S61, Hexagon::S62,
870 Hexagon::S63, Hexagon::S64, Hexagon::S65,
871 Hexagon::S66, Hexagon::S67, Hexagon::S68,
872 Hexagon::S69, Hexagon::S70, Hexagon::S71,
873 Hexagon::S72, Hexagon::S73, Hexagon::S74,
874 Hexagon::S75, Hexagon::S76, Hexagon::S77,
875 Hexagon::S78, Hexagon::S79, Hexagon::S80,
876};
877
878static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo,
879 uint64_t /*Address*/,
880 const MCDisassembler *Decoder) {
881 if (RegNo >= std::size(SysRegDecoderTable))
882 return MCDisassembler::Fail;
883
884 if (SysRegDecoderTable[RegNo] == Hexagon::NoRegister)
885 return MCDisassembler::Fail;
886
887 unsigned Register = SysRegDecoderTable[RegNo];
888 Inst.addOperand(MCOperand::createReg(Register));
889 return MCDisassembler::Success;
890}
891
892static const uint16_t SysReg64DecoderTable[] = {
893 Hexagon::SGP1_0, Hexagon::S3_2, Hexagon::S5_4, Hexagon::S7_6,
894 Hexagon::S9_8, Hexagon::S11_10, Hexagon::S13_12, Hexagon::S15_14,
895 Hexagon::S17_16, Hexagon::S19_18, Hexagon::S21_20, Hexagon::S23_22,
896 Hexagon::S25_24, Hexagon::S27_26, Hexagon::S29_28, Hexagon::S31_30,
897 Hexagon::S33_32, Hexagon::S35_34, Hexagon::S37_36, Hexagon::S39_38,
898 Hexagon::S41_40, Hexagon::S43_42, Hexagon::S45_44, Hexagon::S47_46,
899 Hexagon::S49_48, Hexagon::S51_50, Hexagon::S53_52, Hexagon::S55_54,
900 Hexagon::S57_56, Hexagon::S59_58, Hexagon::S61_60, Hexagon::S63_62,
901 Hexagon::S65_64, Hexagon::S67_66, Hexagon::S69_68, Hexagon::S71_70,
902 Hexagon::S73_72, Hexagon::S75_74, Hexagon::S77_76, Hexagon::S79_78,
903};
904
905static DecodeStatus
906DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/,
907 const MCDisassembler *Decoder) {
908 RegNo = RegNo >> 1;
909 if (RegNo >= std::size(SysReg64DecoderTable))
910 return MCDisassembler::Fail;
911
912 if (SysReg64DecoderTable[RegNo] == Hexagon::NoRegister)
913 return MCDisassembler::Fail;
914
915 unsigned Register = SysReg64DecoderTable[RegNo];
916 Inst.addOperand(MCOperand::createReg(Register));
917 return MCDisassembler::Success;
918}
919
920static DecodeStatus
921DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/,
922 const MCDisassembler *Decoder) {
923 using namespace Hexagon;
924
925 static const MCPhysReg GuestRegDecoderTable[] = {
926 /* 0 */ GELR, GSR, GOSP, G3,
927 /* 4 */ G4, G5, G6, G7,
928 /* 8 */ G8, G9, G10, G11,
929 /* 12 */ G12, G13, G14, G15,
930 /* 16 */ GPMUCNT4, GPMUCNT5, GPMUCNT6, GPMUCNT7,
931 /* 20 */ G20, G21, G22, G23,
932 /* 24 */ GPCYCLELO, GPCYCLEHI, GPMUCNT0, GPMUCNT1,
933 /* 28 */ GPMUCNT2, GPMUCNT3, G30, G31
934 };
935
936 if (RegNo >= std::size(GuestRegDecoderTable))
937 return MCDisassembler::Fail;
938 if (GuestRegDecoderTable[RegNo] == Hexagon::NoRegister)
939 return MCDisassembler::Fail;
940
941 unsigned Register = GuestRegDecoderTable[RegNo];
942 Inst.addOperand(MCOperand::createReg(Register));
943 return MCDisassembler::Success;
944}
945
946static DecodeStatus
947DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
948 uint64_t /*Address*/,
949 const MCDisassembler *Decoder) {
950 using namespace Hexagon;
951
952 static const MCPhysReg GuestReg64DecoderTable[] = {
953 /* 0 */ G1_0, 0, G3_2, 0,
954 /* 4 */ G5_4, 0, G7_6, 0,
955 /* 8 */ G9_8, 0, G11_10, 0,
956 /* 12 */ G13_12, 0, G15_14, 0,
957 /* 16 */ G17_16, 0, G19_18, 0,
958 /* 20 */ G21_20, 0, G23_22, 0,
959 /* 24 */ G25_24, 0, G27_26, 0,
960 /* 28 */ G29_28, 0, G31_30, 0
961 };
962
963 if (RegNo >= std::size(GuestReg64DecoderTable))
964 return MCDisassembler::Fail;
965 if (GuestReg64DecoderTable[RegNo] == Hexagon::NoRegister)
966 return MCDisassembler::Fail;
967
968 unsigned Register = GuestReg64DecoderTable[RegNo];
969 Inst.addOperand(MCOperand::createReg(Register));
970 return MCDisassembler::Success;
971}
Success
#define Success
Definition: AArch64Disassembler.cpp:42
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
LLVM_ABI
#define LLVM_ABI
Definition: Compiler.h:213
LLVM_ATTRIBUTE_UNUSED
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:298
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:132
Size
uint64_t Size
Definition: ELFObjHandler.cpp:81
DecodeIntRegsLow8RegisterClass
static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:619
DecodeGuestRegsRegisterClass
static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:921
DecodeCtrRegsRegisterClass
static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:738
brtargetDecoder
static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:833
DecodePredRegsRegisterClass
static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:720
LLVMInitializeHexagonDisassembler
LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonDisassembler()
Definition: HexagonDisassembler.cpp:186
s32_0ImmDecoder
static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:822
DecodeHvxVQRRegisterClass
static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:710
unsignedImmDecoder
static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:812
DecodeHvxVRRegisterClass
static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:653
createHexagonDisassembler
static MCDisassembler * createHexagonDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: HexagonDisassembler.cpp:179
DecodeSysRegs64RegisterClass
static DecodeStatus DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:906
DecodeModRegsRegisterClass
static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:794
SysReg64DecoderTable
static const uint16_t SysReg64DecoderTable[]
Definition: HexagonDisassembler.cpp:892
adjustDuplex
static void adjustDuplex(MCInst &MI, MCContext &Context)
Definition: HexagonDisassembler.cpp:352
DecodeRegisterClass
static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo, ArrayRef< MCPhysReg > Table)
Definition: HexagonDisassembler.cpp:608
DecodeSysRegsRegisterClass
static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:878
DecodeDoubleRegsRegisterClass
static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:669
SysRegDecoderTable
static const uint16_t SysRegDecoderTable[]
Definition: HexagonDisassembler.cpp:848
DecodeGeneralSubRegsRegisterClass
static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:640
DecodeHvxWRRegisterClass
static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:692
DecodeIntRegsRegisterClass
static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:624
DecodeHvxQRRegisterClass
static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:729
DecodeCtrRegs64RegisterClass
static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:767
DecodeGeneralDoubleLow8RegsRegisterClass
static DecodeStatus DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:682
DecodeGuestRegs64RegisterClass
static DecodeStatus DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: HexagonDisassembler.cpp:947
HEXAGON_MAX_PACKET_SIZE
#define HEXAGON_MAX_PACKET_SIZE
Definition: HexagonMCTargetDesc.h:36
HEXAGON_INSTR_SIZE
#define HEXAGON_INSTR_SIZE
Definition: HexagonMCTargetDesc.h:32
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:110
I
#define I(x, y, z)
Definition: MD5.cpp:58
OpIndex
unsigned OpIndex
Definition: SPIRVModuleAnalysis.cpp:56
IntRegDecoderTable
static constexpr unsigned IntRegDecoderTable[]
Definition: SparcDisassembler.cpp:65
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:147
llvm::ArrayRef::data
const T * data() const
Definition: ArrayRef.h:144
llvm::ArrayRef::slice
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.
Definition: ArrayRef.h:191
llvm::HexagonMCChecker
Check for a valid bundle.
Definition: HexagonMCChecker.h:33
llvm::MCConstantExpr::create
static LLVM_ABI const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:212
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:83
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:85
llvm::MCDisassembler::getInstructionBundle
virtual DecodeStatus getInstructionBundle(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const
Returns the disassembly of an instruction bundle for VLIW architectures like Hexagon.
Definition: MCDisassembler.h:144
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:109
llvm::MCDisassembler::getInstruction
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:188
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:215
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:27
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:40
llvm::MCOperand::createExpr
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:166
llvm::MCOperand::createReg
static MCOperand createReg(MCRegister Reg)
Definition: MCInst.h:138
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:145
llvm::MCOperand::setReg
void setReg(MCRegister Reg)
Set the register number.
Definition: MCInst.h:79
llvm::MCOperand::isReg
bool isReg() const
Definition: MCInst.h:65
llvm::MCOperand::getReg
MCRegister getReg() const
Returns the register number.
Definition: MCInst.h:73
llvm::MCOperand::createInst
static MCOperand createInst(const MCInst *Val)
Definition: MCInst.h:173
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:77
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:146
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
uint16_t
uint32_t
uint64_t
uint8_t
llvm::HexagonMCInstrInfo::addConstant
void addConstant(MCInst &MI, uint64_t Value, MCContext &Context)
Definition: HexagonMCInstrInfo.cpp:82
llvm::HexagonMCInstrInfo::IsReverseVecRegPair
bool IsReverseVecRegPair(MCRegister VecReg)
Definition: HexagonMCInstrInfo.cpp:699
llvm::HexagonMCInstrInfo::bundleSize
size_t bundleSize(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:116
llvm::HexagonMCInstrInfo::isDuplex
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:624
llvm::HexagonMCInstrInfo::getExtentBits
unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:340
llvm::HexagonMCInstrInfo::isNewValue
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn expects newly produced value.
Definition: HexagonMCInstrInfo.cpp:670
llvm::HexagonMCInstrInfo::getNewValueOp
unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:379
llvm::HexagonMCInstrInfo::getExtendableOp
unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:316
llvm::HexagonMCInstrInfo::IsVecRegPair
bool IsVecRegPair(MCRegister VecReg)
Definition: HexagonMCInstrInfo.cpp:694
llvm::HexagonMCInstrInfo::bundleInstructions
iterator_range< Hexagon::PacketIterator > bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:103
llvm::HexagonMCInstrInfo::isExtendable
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:628
llvm::HexagonMCInstrInfo::extenderForIndex
MCInst const * extenderForIndex(MCInst const &MCB, size_t Index)
Definition: HexagonMCInstrInfo.cpp:222
llvm::HexagonMCInstrInfo::isImmext
bool isImmext(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:650
llvm::HexagonMCInstrInfo::getNewValueOperand
MCOperand const & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:385
llvm::HexagonMCInstrInfo::hasNewValue2
bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a second value.
Definition: HexagonMCInstrInfo.cpp:520
llvm::HexagonMCInstrInfo::getExtentAlignment
unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:334
llvm::HexagonMCInstrInfo::isVector
bool isVector(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:869
llvm::HexagonMCInstrInfo::getNewValueOperand2
MCOperand const & getNewValueOperand2(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:411
llvm::HexagonMCInstrInfo::isExtended
bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:634
llvm::HexagonMCInstrInfo::hasNewValue
bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a value.
Definition: HexagonMCInstrInfo.cpp:513
llvm::Hexagon_MC::getArchSubtarget
MCSubtargetInfo const * getArchSubtarget(MCSubtargetInfo const *STI)
Definition: HexagonMCTargetDesc.cpp:526
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::support::endian::read32le
uint32_t read32le(const void *P)
Definition: Endian.h:429
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::Offset
@ Offset
Definition: DWP.cpp:477
llvm::getTheHexagonTarget
Target & getTheHexagonTarget()
Definition: HexagonTargetInfo.cpp:14
llvm::M1
unsigned M1(unsigned Val)
Definition: VE.h:377
llvm::M0
unsigned M0(unsigned Val)
Definition: VE.h:376
llvm::SignExtend64
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition: MathExtras.h:577
raw_ostream.h
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition: TargetRegistry.h:897
Generated on Sat Aug 30 2025 10:15:30 for LLVM by doxygen 1.9.6