LLVM 22.0.0git
HexagonDisassembler.cpp
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1//===- HexagonDisassembler.cpp - Disassembler for Hexagon ISA -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "MCTargetDesc/HexagonBaseInfo.h"
10#include "MCTargetDesc/HexagonMCChecker.h"
11#include "MCTargetDesc/HexagonMCInstrInfo.h"
12#include "MCTargetDesc/HexagonMCTargetDesc.h"
13#include "TargetInfo/HexagonTargetInfo.h"
14#include "llvm/ADT/ArrayRef.h"
15#include "llvm/MC/MCContext.h"
16#include "llvm/MC/MCDecoder.h"
17#include "llvm/MC/MCDecoderOps.h"
18#include "llvm/MC/MCDisassembler/MCDisassembler.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCInstrInfo.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/MC/TargetRegistry.h"
25#include "llvm/Support/Compiler.h"
26#include "llvm/Support/Endian.h"
27#include "llvm/Support/MathExtras.h"
28#include "llvm/Support/raw_ostream.h"
29#include <cassert>
30#include <cstddef>
31#include <cstdint>
32#include <memory>
33
34#define DEBUG_TYPE "hexagon-disassembler"
35
36using namespace llvm;
37using namespace Hexagon;
38
39using DecodeStatus = MCDisassembler::DecodeStatus;
40
41namespace {
42
43/// Hexagon disassembler for all Hexagon platforms.
44class HexagonDisassembler : public MCDisassembler {
45public:
46 std::unique_ptr<MCInstrInfo const> const MCII;
47 mutable std::unique_ptr<MCInst> CurrentBundle;
48 mutable MCInst const *CurrentExtender;
49
50 HexagonDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
51 MCInstrInfo const *MCII)
52 : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(nullptr),
53 CurrentExtender(nullptr) {}
54
55 DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB,
56 ArrayRef<uint8_t> Bytes, uint64_t Address,
57 raw_ostream &CStream, bool &Complete) const;
58 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
59 ArrayRef<uint8_t> Bytes, uint64_t Address,
60 raw_ostream &CStream) const override;
61
62 DecodeStatus getInstructionBundle(MCInst &Instr, uint64_t &Size,
63 ArrayRef<uint8_t> Bytes, uint64_t Address,
64 raw_ostream &CStream) const override;
65
66 void remapInstruction(MCInst &Instr) const;
67
68private:
69 bool makeBundle(ArrayRef<uint8_t> Bytes, uint64_t Address,
70 uint64_t &BytesToSkip, raw_ostream &CS) const;
71
72 void resetBundle() const {
73 CurrentBundle.reset();
74 CurrentInstruction = nullptr;
75 }
76
77 mutable MCOperand *CurrentInstruction = nullptr;
78};
79
80static uint64_t fullValue(HexagonDisassembler const &Disassembler, MCInst &MI,
81 int64_t Value) {
82 MCInstrInfo MCII = *Disassembler.MCII;
83 if (!Disassembler.CurrentExtender ||
84 MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI))
85 return Value;
86 unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
87 uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f;
88 int64_t Bits;
89 bool Success =
90 Disassembler.CurrentExtender->getOperand(0).getExpr()->evaluateAsAbsolute(
91 Bits);
92 assert(Success);
93 (void)Success;
94 uint64_t Upper26 = static_cast<uint64_t>(Bits);
95 uint64_t Operand = Upper26 | Lower6;
96 return Operand;
97}
98static HexagonDisassembler const &disassembler(const MCDisassembler *Decoder) {
99 return *static_cast<HexagonDisassembler const *>(Decoder);
100}
101template <size_t T>
102static void signedDecoder(MCInst &MI, unsigned tmp,
103 const MCDisassembler *Decoder) {
104 HexagonDisassembler const &Disassembler = disassembler(Decoder);
105 int64_t FullValue = fullValue(Disassembler, MI, SignExtend64<T>(tmp));
106 int64_t Extended = SignExtend64<32>(FullValue);
107 HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());
108}
109}
110
111// Forward declare these because the auto-generated code will reference them.
112// Definitions are further down.
113
114static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
115 uint64_t Address,
116 const MCDisassembler *Decoder);
117static DecodeStatus
118DecodeGeneralSubRegsRegisterClass(MCInst &Inst, unsigned RegNo,
119 uint64_t Address,
120 const MCDisassembler *Decoder);
121static DecodeStatus
122DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
123 const MCDisassembler *Decoder);
124static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
125 uint64_t Address,
126 const MCDisassembler *Decoder);
127static DecodeStatus
128DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
129 const MCDisassembler *Decoder);
130static DecodeStatus
131DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo,
132 uint64_t Address,
133 const MCDisassembler *Decoder);
134static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
135 uint64_t Address,
136 const MCDisassembler *Decoder);
137static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst, unsigned RegNo,
138 uint64_t Address,
139 const MCDisassembler *Decoder);
140static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
141 uint64_t Address,
142 const MCDisassembler *Decoder);
143static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
144 uint64_t Address,
145 const MCDisassembler *Decoder);
146static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
147 uint64_t Address,
148 const MCDisassembler *Decoder);
149static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo,
150 uint64_t Address,
151 const MCDisassembler *Decoder);
152static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo,
153 uint64_t Address,
154 const MCDisassembler *Decoder);
155static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
156 uint64_t Address,
157 const MCDisassembler *Decoder);
158static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
159 uint64_t Address,
160 const MCDisassembler *Decoder);
161static DecodeStatus
162DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
163 const MCDisassembler *Decoder);
164static DecodeStatus DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
165 uint64_t Address,
166 const MCDisassembler *Decoder);
167
168static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
169 uint64_t Address,
170 const MCDisassembler *Decoder);
171static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp,
172 uint64_t /*Address*/,
173 const MCDisassembler *Decoder);
174static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
175 const MCDisassembler *Decoder);
176
177static DecodeStatus n1ConstDecoder(MCInst &MI, const MCDisassembler *Decoder) {
178 MCContext &Ctx = Decoder->getContext();
179 MI.addOperand(MCOperand::createExpr(MCConstantExpr::create(-1, Ctx)));
180 return DecodeStatus::Success;
181}
182
183static DecodeStatus sgp10ConstDecoder(MCInst &MI,
184 const MCDisassembler *Decoder) {
185 MI.addOperand(MCOperand::createReg(Hexagon::SGP1_0));
186 return DecodeStatus::Success;
187}
188
189#include "HexagonDepDecoders.inc"
190#include "HexagonGenDisassemblerTables.inc"
191
192static MCDisassembler *createHexagonDisassembler(const Target &T,
193 const MCSubtargetInfo &STI,
194 MCContext &Ctx) {
195 return new HexagonDisassembler(STI, Ctx, T.createMCInstrInfo());
196}
197
198extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
203
204bool HexagonDisassembler::makeBundle(ArrayRef<uint8_t> Bytes, uint64_t Address,
205 uint64_t &BytesToSkip,
206 raw_ostream &CS) const {
207 bool Complete = false;
208 DecodeStatus Result = DecodeStatus::Success;
209
210 CurrentBundle.reset(new MCInst);
211 CurrentBundle->setOpcode(Hexagon::BUNDLE);
212 CurrentBundle->addOperand(MCOperand::createImm(0));
213 while (Result == Success && !Complete) {
214 if (Bytes.size() < HEXAGON_INSTR_SIZE)
215 return false;
216 MCInst *Inst = getContext().createMCInst();
217 Result = getSingleInstruction(*Inst, *CurrentBundle, Bytes, Address, CS,
218 Complete);
219 CurrentBundle->addOperand(MCOperand::createInst(Inst));
220 BytesToSkip += HEXAGON_INSTR_SIZE;
221 Bytes = Bytes.slice(HEXAGON_INSTR_SIZE);
222 }
223 if (Result == MCDisassembler::Fail)
224 return false;
225 if (BytesToSkip > HEXAGON_MAX_PACKET_SIZE)
226 return false;
227
228 const auto ArchSTI = Hexagon_MC::getArchSubtarget(&STI);
229 const auto STI_ = (ArchSTI != nullptr) ? *ArchSTI : STI;
230 HexagonMCChecker Checker(getContext(), *MCII, STI_, *CurrentBundle,
231 *getContext().getRegisterInfo(), false);
232 if (!Checker.check())
233 return false;
234 remapInstruction(*CurrentBundle);
235 return true;
236}
237
238DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
239 ArrayRef<uint8_t> Bytes,
240 uint64_t Address,
241 raw_ostream &CS) const {
242 CommentStream = &CS;
243
244 Size = 0;
245 uint64_t BytesToSkip = 0;
246
247 if (!CurrentBundle) {
248 if (!makeBundle(Bytes, Address, BytesToSkip, CS)) {
249 Size = BytesToSkip;
250 resetBundle();
251 return MCDisassembler::Fail;
252 }
253 CurrentInstruction = (CurrentBundle->begin() + 1);
254 }
255
256 MI = *(CurrentInstruction->getInst());
257 Size = HEXAGON_INSTR_SIZE;
258 if (++CurrentInstruction == CurrentBundle->end())
259 resetBundle();
260 return MCDisassembler::Success;
261}
262
263DecodeStatus HexagonDisassembler::getInstructionBundle(MCInst &MI,
264 uint64_t &Size,
265 ArrayRef<uint8_t> Bytes,
266 uint64_t Address,
267 raw_ostream &CS) const {
268 CommentStream = &CS;
269 Size = 0;
270 uint64_t BytesToSkip = 0;
271 assert(!CurrentBundle);
272
273 if (!makeBundle(Bytes, Address, BytesToSkip, CS)) {
274 Size = BytesToSkip;
275 resetBundle();
276 return MCDisassembler::Fail;
277 }
278
279 MI = *CurrentBundle;
280 Size = HEXAGON_INSTR_SIZE * HexagonMCInstrInfo::bundleSize(MI);
281 resetBundle();
282
283 return Success;
284}
285
286void HexagonDisassembler::remapInstruction(MCInst &Instr) const {
287 for (auto I: HexagonMCInstrInfo::bundleInstructions(Instr)) {
288 auto &MI = const_cast<MCInst &>(*I.getInst());
289 switch (MI.getOpcode()) {
290 case Hexagon::S2_allocframe:
291 if (MI.getOperand(0).getReg() == Hexagon::R29) {
292 MI.setOpcode(Hexagon::S6_allocframe_to_raw);
293 MI.erase(MI.begin () + 1);
294 MI.erase(MI.begin ());
295 }
296 break;
297 case Hexagon::L2_deallocframe:
298 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
299 MI.getOperand(1).getReg() == Hexagon::R30) {
300 MI.setOpcode(L6_deallocframe_map_to_raw);
301 MI.erase(MI.begin () + 1);
302 MI.erase(MI.begin ());
303 }
304 break;
305 case Hexagon::L4_return:
306 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
307 MI.getOperand(1).getReg() == Hexagon::R30) {
308 MI.setOpcode(L6_return_map_to_raw);
309 MI.erase(MI.begin () + 1);
310 MI.erase(MI.begin ());
311 }
312 break;
313 case Hexagon::L4_return_t:
314 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
315 MI.getOperand(2).getReg() == Hexagon::R30) {
316 MI.setOpcode(L4_return_map_to_raw_t);
317 MI.erase(MI.begin () + 2);
318 MI.erase(MI.begin ());
319 }
320 break;
321 case Hexagon::L4_return_f:
322 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
323 MI.getOperand(2).getReg() == Hexagon::R30) {
324 MI.setOpcode(L4_return_map_to_raw_f);
325 MI.erase(MI.begin () + 2);
326 MI.erase(MI.begin ());
327 }
328 break;
329 case Hexagon::L4_return_tnew_pt:
330 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
331 MI.getOperand(2).getReg() == Hexagon::R30) {
332 MI.setOpcode(L4_return_map_to_raw_tnew_pt);
333 MI.erase(MI.begin () + 2);
334 MI.erase(MI.begin ());
335 }
336 break;
337 case Hexagon::L4_return_fnew_pt:
338 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
339 MI.getOperand(2).getReg() == Hexagon::R30) {
340 MI.setOpcode(L4_return_map_to_raw_fnew_pt);
341 MI.erase(MI.begin () + 2);
342 MI.erase(MI.begin ());
343 }
344 break;
345 case Hexagon::L4_return_tnew_pnt:
346 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
347 MI.getOperand(2).getReg() == Hexagon::R30) {
348 MI.setOpcode(L4_return_map_to_raw_tnew_pnt);
349 MI.erase(MI.begin () + 2);
350 MI.erase(MI.begin ());
351 }
352 break;
353 case Hexagon::L4_return_fnew_pnt:
354 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
355 MI.getOperand(2).getReg() == Hexagon::R30) {
356 MI.setOpcode(L4_return_map_to_raw_fnew_pnt);
357 MI.erase(MI.begin () + 2);
358 MI.erase(MI.begin ());
359 }
360 break;
361 }
362 }
363}
364
365DecodeStatus HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
366 ArrayRef<uint8_t> Bytes,
367 uint64_t Address,
368 raw_ostream &cs,
369 bool &Complete) const {
370 assert(Bytes.size() >= HEXAGON_INSTR_SIZE);
371
372 uint32_t Instruction = support::endian::read32le(Bytes.data());
373
374 auto BundleSize = HexagonMCInstrInfo::bundleSize(MCB);
375 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
376 HexagonII::INST_PARSE_LOOP_END) {
377 if (BundleSize == 0)
378 HexagonMCInstrInfo::setInnerLoop(MCB);
379 else if (BundleSize == 1)
380 HexagonMCInstrInfo::setOuterLoop(MCB);
381 else
382 return DecodeStatus::Fail;
383 }
384
385 CurrentExtender = HexagonMCInstrInfo::extenderForIndex(
386 MCB, HexagonMCInstrInfo::bundleSize(MCB));
387
388 DecodeStatus Result = DecodeStatus::Fail;
389 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
390 HexagonII::INST_PARSE_DUPLEX) {
391 unsigned duplexIClass;
392 uint8_t const *DecodeLow, *DecodeHigh;
393 duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1);
394 switch (duplexIClass) {
395 default:
396 return MCDisassembler::Fail;
397 case 0:
398 DecodeLow = DecoderTableSUBINSN_L132;
399 DecodeHigh = DecoderTableSUBINSN_L132;
400 break;
401 case 1:
402 DecodeLow = DecoderTableSUBINSN_L232;
403 DecodeHigh = DecoderTableSUBINSN_L132;
404 break;
405 case 2:
406 DecodeLow = DecoderTableSUBINSN_L232;
407 DecodeHigh = DecoderTableSUBINSN_L232;
408 break;
409 case 3:
410 DecodeLow = DecoderTableSUBINSN_A32;
411 DecodeHigh = DecoderTableSUBINSN_A32;
412 break;
413 case 4:
414 DecodeLow = DecoderTableSUBINSN_L132;
415 DecodeHigh = DecoderTableSUBINSN_A32;
416 break;
417 case 5:
418 DecodeLow = DecoderTableSUBINSN_L232;
419 DecodeHigh = DecoderTableSUBINSN_A32;
420 break;
421 case 6:
422 DecodeLow = DecoderTableSUBINSN_S132;
423 DecodeHigh = DecoderTableSUBINSN_A32;
424 break;
425 case 7:
426 DecodeLow = DecoderTableSUBINSN_S232;
427 DecodeHigh = DecoderTableSUBINSN_A32;
428 break;
429 case 8:
430 DecodeLow = DecoderTableSUBINSN_S132;
431 DecodeHigh = DecoderTableSUBINSN_L132;
432 break;
433 case 9:
434 DecodeLow = DecoderTableSUBINSN_S132;
435 DecodeHigh = DecoderTableSUBINSN_L232;
436 break;
437 case 10:
438 DecodeLow = DecoderTableSUBINSN_S132;
439 DecodeHigh = DecoderTableSUBINSN_S132;
440 break;
441 case 11:
442 DecodeLow = DecoderTableSUBINSN_S232;
443 DecodeHigh = DecoderTableSUBINSN_S132;
444 break;
445 case 12:
446 DecodeLow = DecoderTableSUBINSN_S232;
447 DecodeHigh = DecoderTableSUBINSN_L132;
448 break;
449 case 13:
450 DecodeLow = DecoderTableSUBINSN_S232;
451 DecodeHigh = DecoderTableSUBINSN_L232;
452 break;
453 case 14:
454 DecodeLow = DecoderTableSUBINSN_S232;
455 DecodeHigh = DecoderTableSUBINSN_S232;
456 break;
457 }
458 MI.setOpcode(Hexagon::DuplexIClass0 + duplexIClass);
459 MCInst *MILow = getContext().createMCInst();
460 MCInst *MIHigh = getContext().createMCInst();
461 auto TmpExtender = CurrentExtender;
462 CurrentExtender =
463 nullptr; // constant extenders in duplex must always be in slot 1
464 Result = decodeInstruction(DecodeLow, *MILow, Instruction & 0x1fff, Address,
465 this, STI);
466 CurrentExtender = TmpExtender;
467 if (Result != DecodeStatus::Success)
468 return DecodeStatus::Fail;
469 Result = decodeInstruction(
470 DecodeHigh, *MIHigh, (Instruction >> 16) & 0x1fff, Address, this, STI);
471 if (Result != DecodeStatus::Success)
472 return DecodeStatus::Fail;
473 MCOperand OPLow = MCOperand::createInst(MILow);
474 MCOperand OPHigh = MCOperand::createInst(MIHigh);
475 MI.addOperand(OPLow);
476 MI.addOperand(OPHigh);
477 Complete = true;
478 } else {
479 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
480 HexagonII::INST_PARSE_PACKET_END)
481 Complete = true;
482
483 if (CurrentExtender != nullptr)
484 Result = decodeInstruction(DecoderTableMustExtend32, MI, Instruction,
485 Address, this, STI);
486
487 if (Result != MCDisassembler::Success)
488 Result = decodeInstruction(DecoderTable32, MI, Instruction, Address, this,
489 STI);
490
491 if (Result != MCDisassembler::Success &&
492 STI.hasFeature(Hexagon::ExtensionHVX))
493 Result = decodeInstruction(DecoderTableEXT_mmvec32, MI, Instruction,
494 Address, this, STI);
495
496 }
497
498 if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) {
499 unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI);
500 MCOperand &MCO = MI.getOperand(OpIndex);
501 assert(MCO.isReg() && "New value consumers must be registers");
502 unsigned Register =
503 getContext().getRegisterInfo()->getEncodingValue(MCO.getReg());
504 if ((Register & 0x6) == 0)
505 // HexagonPRM 10.11 Bit 1-2 == 0 is reserved
506 return MCDisassembler::Fail;
507 unsigned Lookback = (Register & 0x6) >> 1;
508 unsigned Offset = 1;
509 bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI);
510 bool PrevVector = false;
511 auto Instructions = HexagonMCInstrInfo::bundleInstructions(*CurrentBundle);
512 auto i = Instructions.end() - 1;
513 for (auto n = Instructions.begin() - 1;; --i, ++Offset) {
514 if (i == n)
515 // Couldn't find producer
516 return MCDisassembler::Fail;
517 bool CurrentVector = HexagonMCInstrInfo::isVector(*MCII, *i->getInst());
518 if (Vector && !CurrentVector)
519 // Skip scalars when calculating distances for vectors
520 ++Lookback;
521 if (HexagonMCInstrInfo::isImmext(*i->getInst()) && (Vector == PrevVector))
522 ++Lookback;
523 PrevVector = CurrentVector;
524 if (Offset == Lookback)
525 break;
526 }
527 auto const &Inst = *i->getInst();
528 bool SubregBit = (Register & 0x1) != 0;
529 if (HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) {
530 // If subreg bit is set we're selecting the second produced newvalue
531 MCRegister Producer =
532 SubregBit
533 ? HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg()
534 : HexagonMCInstrInfo::getNewValueOperand2(*MCII, Inst).getReg();
535 assert(Producer != Hexagon::NoRegister);
536 MCO.setReg(Producer);
537 } else if (HexagonMCInstrInfo::hasNewValue(*MCII, Inst)) {
538 MCRegister Producer =
539 HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg();
540
541 if (HexagonMCInstrInfo::IsVecRegPair(Producer)) {
542 const bool Rev = HexagonMCInstrInfo::IsReverseVecRegPair(Producer);
543 const unsigned ProdPairIndex =
544 Rev ? Producer - Hexagon::WR0 : Producer - Hexagon::W0;
545 if (Rev)
546 SubregBit = !SubregBit;
547 Producer = (ProdPairIndex << 1) + SubregBit + Hexagon::V0;
548 } else if (SubregBit)
549 // Hexagon PRM 10.11 New-value operands
550 // Nt[0] is reserved and should always be encoded as zero.
551 return MCDisassembler::Fail;
552 assert(Producer != Hexagon::NoRegister);
553 MCO.setReg(Producer);
554 } else
555 return MCDisassembler::Fail;
556 }
557
558 if (CurrentExtender != nullptr) {
559 MCInst const &Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI)
560 ? *MI.getOperand(1).getInst()
561 : MI;
562 if (!HexagonMCInstrInfo::isExtendable(*MCII, Inst) &&
563 !HexagonMCInstrInfo::isExtended(*MCII, Inst))
564 return MCDisassembler::Fail;
565 }
566 return Result;
567}
568
569static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo,
570 ArrayRef<MCPhysReg> Table) {
571 if (RegNo < Table.size()) {
572 Inst.addOperand(MCOperand::createReg(Table[RegNo]));
573 return MCDisassembler::Success;
574 }
575
576 return MCDisassembler::Fail;
577}
578
579static DecodeStatus
580DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
581 const MCDisassembler *Decoder) {
582 return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder);
583}
584
585static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
586 uint64_t Address,
587 const MCDisassembler *Decoder) {
588 static const MCPhysReg IntRegDecoderTable[] = {
589 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
590 Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
591 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
592 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
593 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,
594 Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,
595 Hexagon::R30, Hexagon::R31};
596
597 return DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable);
598}
599
600static DecodeStatus
601DecodeGeneralSubRegsRegisterClass(MCInst &Inst, unsigned RegNo,
602 uint64_t Address,
603 const MCDisassembler *Decoder) {
604 static const MCPhysReg GeneralSubRegDecoderTable[] = {
605 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3,
606 Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7,
607 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
608 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
609 };
610
611 return DecodeRegisterClass(Inst, RegNo, GeneralSubRegDecoderTable);
612}
613
614static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
615 uint64_t /*Address*/,
616 const MCDisassembler *Decoder) {
617 static const MCPhysReg HvxVRDecoderTable[] = {
618 Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4,
619 Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9,
620 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14,
621 Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19,
622 Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24,
623 Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29,
624 Hexagon::V30, Hexagon::V31};
625
626 return DecodeRegisterClass(Inst, RegNo, HvxVRDecoderTable);
627}
628
629static DecodeStatus
630DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
631 uint64_t /*Address*/,
632 const MCDisassembler *Decoder) {
633 static const MCPhysReg DoubleRegDecoderTable[] = {
634 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
635 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7,
636 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11,
637 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15};
638
639 return DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable);
640}
641
642static DecodeStatus
643DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo,
644 uint64_t /*Address*/,
645 const MCDisassembler *Decoder) {
646 static const MCPhysReg GeneralDoubleLow8RegDecoderTable[] = {
647 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
648 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11};
649
650 return DecodeRegisterClass(Inst, RegNo, GeneralDoubleLow8RegDecoderTable);
651}
652
653static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
654 uint64_t /*Address*/,
655 const MCDisassembler *Decoder) {
656 static const MCPhysReg HvxWRDecoderTable[] = {
657 Hexagon::W0, Hexagon::WR0, Hexagon::W1, Hexagon::WR1, Hexagon::W2,
658 Hexagon::WR2, Hexagon::W3, Hexagon::WR3, Hexagon::W4, Hexagon::WR4,
659 Hexagon::W5, Hexagon::WR5, Hexagon::W6, Hexagon::WR6, Hexagon::W7,
660 Hexagon::WR7, Hexagon::W8, Hexagon::WR8, Hexagon::W9, Hexagon::WR9,
661 Hexagon::W10, Hexagon::WR10, Hexagon::W11, Hexagon::WR11, Hexagon::W12,
662 Hexagon::WR12, Hexagon::W13, Hexagon::WR13, Hexagon::W14, Hexagon::WR14,
663 Hexagon::W15, Hexagon::WR15,
664 };
665
666 return DecodeRegisterClass(Inst, RegNo, HvxWRDecoderTable);
667}
668
669LLVM_ATTRIBUTE_UNUSED // Suppress warning temporarily.
670 static DecodeStatus
671 DecodeHvxVQRRegisterClass(MCInst &Inst, unsigned RegNo,
672 uint64_t /*Address*/,
673 const MCDisassembler *Decoder) {
674 static const MCPhysReg HvxVQRDecoderTable[] = {
675 Hexagon::VQ0, Hexagon::VQ1, Hexagon::VQ2, Hexagon::VQ3,
676 Hexagon::VQ4, Hexagon::VQ5, Hexagon::VQ6, Hexagon::VQ7};
677
678 return DecodeRegisterClass(Inst, RegNo >> 2, HvxVQRDecoderTable);
679}
680
681static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
682 uint64_t /*Address*/,
683 const MCDisassembler *Decoder) {
684 static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,
685 Hexagon::P2, Hexagon::P3};
686
687 return DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable);
688}
689
690static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
691 uint64_t /*Address*/,
692 const MCDisassembler *Decoder) {
693 static const MCPhysReg HvxQRDecoderTable[] = {Hexagon::Q0, Hexagon::Q1,
694 Hexagon::Q2, Hexagon::Q3};
695
696 return DecodeRegisterClass(Inst, RegNo, HvxQRDecoderTable);
697}
698
699static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
700 uint64_t /*Address*/,
701 const MCDisassembler *Decoder) {
702 using namespace Hexagon;
703
704 static const MCPhysReg CtrlRegDecoderTable[] = {
705 /* 0 */ SA0, LC0, SA1, LC1,
706 /* 4 */ P3_0, C5, M0, M1,
707 /* 8 */ USR, PC, UGP, GP,
708 /* 12 */ CS0, CS1, UPCYCLELO, UPCYCLEHI,
709 /* 16 */ FRAMELIMIT, FRAMEKEY, PKTCOUNTLO, PKTCOUNTHI,
710 /* 20 */ 0, 0, 0, 0,
711 /* 24 */ 0, 0, 0, 0,
712 /* 28 */ 0, 0, UTIMERLO, UTIMERHI
713 };
714
715 if (RegNo >= std::size(CtrlRegDecoderTable))
716 return MCDisassembler::Fail;
717
718 static_assert(NoRegister == 0, "Expecting NoRegister to be 0");
719 if (CtrlRegDecoderTable[RegNo] == NoRegister)
720 return MCDisassembler::Fail;
721
722 unsigned Register = CtrlRegDecoderTable[RegNo];
723 Inst.addOperand(MCOperand::createReg(Register));
724 return MCDisassembler::Success;
725}
726
727static DecodeStatus
728DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/,
729 const MCDisassembler *Decoder) {
730 using namespace Hexagon;
731
732 static const MCPhysReg CtrlReg64DecoderTable[] = {
733 /* 0 */ C1_0, 0, C3_2, 0,
734 /* 4 */ C5_4, 0, C7_6, 0,
735 /* 8 */ C9_8, 0, C11_10, 0,
736 /* 12 */ CS, 0, UPCYCLE, 0,
737 /* 16 */ C17_16, 0, PKTCOUNT, 0,
738 /* 20 */ 0, 0, 0, 0,
739 /* 24 */ 0, 0, 0, 0,
740 /* 28 */ 0, 0, UTIMER, 0
741 };
742
743 if (RegNo >= std::size(CtrlReg64DecoderTable))
744 return MCDisassembler::Fail;
745
746 static_assert(NoRegister == 0, "Expecting NoRegister to be 0");
747 if (CtrlReg64DecoderTable[RegNo] == NoRegister)
748 return MCDisassembler::Fail;
749
750 unsigned Register = CtrlReg64DecoderTable[RegNo];
751 Inst.addOperand(MCOperand::createReg(Register));
752 return MCDisassembler::Success;
753}
754
755static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
756 uint64_t /*Address*/,
757 const MCDisassembler *Decoder) {
758 unsigned Register = 0;
759 switch (RegNo) {
760 case 0:
761 Register = Hexagon::M0;
762 break;
763 case 1:
764 Register = Hexagon::M1;
765 break;
766 default:
767 return MCDisassembler::Fail;
768 }
769 Inst.addOperand(MCOperand::createReg(Register));
770 return MCDisassembler::Success;
771}
772
773static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
774 uint64_t /*Address*/,
775 const MCDisassembler *Decoder) {
776 HexagonDisassembler const &Disassembler = disassembler(Decoder);
777 int64_t FullValue = fullValue(Disassembler, MI, tmp);
778 assert(FullValue >= 0 && "Negative in unsigned decoder");
779 HexagonMCInstrInfo::addConstant(MI, FullValue, Disassembler.getContext());
780 return MCDisassembler::Success;
781}
782
783static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp,
784 uint64_t /*Address*/,
785 const MCDisassembler *Decoder) {
786 HexagonDisassembler const &Disassembler = disassembler(Decoder);
787 unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI);
788 tmp = SignExtend64(tmp, Bits);
789 signedDecoder<32>(MI, tmp, Decoder);
790 return MCDisassembler::Success;
791}
792
793// custom decoder for various jump/call immediates
794static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
795 const MCDisassembler *Decoder) {
796 HexagonDisassembler const &Disassembler = disassembler(Decoder);
797 unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI);
798 // r13_2 is not extendable, so if there are no extent bits, it's r13_2
799 if (Bits == 0)
800 Bits = 15;
801 uint64_t FullValue = fullValue(Disassembler, MI, SignExtend64(tmp, Bits));
802 uint32_t Extended = FullValue + Address;
803 if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, 0, 0,
804 4))
805 HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());
806 return MCDisassembler::Success;
807}
808
809static const uint16_t SysRegDecoderTable[] = {
810 Hexagon::SGP0, Hexagon::SGP1, Hexagon::STID,
811 Hexagon::ELR, Hexagon::BADVA0, Hexagon::BADVA1,
812 Hexagon::SSR, Hexagon::CCR, Hexagon::HTID,
813 Hexagon::BADVA, Hexagon::IMASK, Hexagon::S11,
814 Hexagon::S12, Hexagon::S13, Hexagon::S14,
815 Hexagon::S15, Hexagon::EVB, Hexagon::MODECTL,
816 Hexagon::SYSCFG, Hexagon::S19, Hexagon::S20,
817 Hexagon::VID, Hexagon::S22, Hexagon::S23,
818 Hexagon::S24, Hexagon::S25, Hexagon::S26,
819 Hexagon::CFGBASE, Hexagon::DIAG, Hexagon::REV,
820 Hexagon::PCYCLELO, Hexagon::PCYCLEHI, Hexagon::ISDBST,
821 Hexagon::ISDBCFG0, Hexagon::ISDBCFG1, Hexagon::S35,
822 Hexagon::BRKPTPC0, Hexagon::BRKPTCFG0, Hexagon::BRKPTPC1,
823 Hexagon::BRKPTCFG1, Hexagon::ISDBMBXIN, Hexagon::ISDBMBXOUT,
824 Hexagon::ISDBEN, Hexagon::ISDBGPR, Hexagon::S44,
825 Hexagon::S45, Hexagon::S46, Hexagon::S47,
826 Hexagon::PMUCNT0, Hexagon::PMUCNT1, Hexagon::PMUCNT2,
827 Hexagon::PMUCNT3, Hexagon::PMUEVTCFG, Hexagon::PMUCFG,
828 Hexagon::S54, Hexagon::S55, Hexagon::S56,
829 Hexagon::S57, Hexagon::S58, Hexagon::S59,
830 Hexagon::S60, Hexagon::S61, Hexagon::S62,
831 Hexagon::S63, Hexagon::S64, Hexagon::S65,
832 Hexagon::S66, Hexagon::S67, Hexagon::S68,
833 Hexagon::S69, Hexagon::S70, Hexagon::S71,
834 Hexagon::S72, Hexagon::S73, Hexagon::S74,
835 Hexagon::S75, Hexagon::S76, Hexagon::S77,
836 Hexagon::S78, Hexagon::S79, Hexagon::S80,
837};
838
839static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo,
840 uint64_t /*Address*/,
841 const MCDisassembler *Decoder) {
842 if (RegNo >= std::size(SysRegDecoderTable))
843 return MCDisassembler::Fail;
844
845 if (SysRegDecoderTable[RegNo] == Hexagon::NoRegister)
846 return MCDisassembler::Fail;
847
848 unsigned Register = SysRegDecoderTable[RegNo];
849 Inst.addOperand(MCOperand::createReg(Register));
850 return MCDisassembler::Success;
851}
852
853static const uint16_t SysReg64DecoderTable[] = {
854 Hexagon::SGP1_0, Hexagon::S3_2, Hexagon::S5_4, Hexagon::S7_6,
855 Hexagon::S9_8, Hexagon::S11_10, Hexagon::S13_12, Hexagon::S15_14,
856 Hexagon::S17_16, Hexagon::S19_18, Hexagon::S21_20, Hexagon::S23_22,
857 Hexagon::S25_24, Hexagon::S27_26, Hexagon::S29_28, Hexagon::S31_30,
858 Hexagon::S33_32, Hexagon::S35_34, Hexagon::S37_36, Hexagon::S39_38,
859 Hexagon::S41_40, Hexagon::S43_42, Hexagon::S45_44, Hexagon::S47_46,
860 Hexagon::S49_48, Hexagon::S51_50, Hexagon::S53_52, Hexagon::S55_54,
861 Hexagon::S57_56, Hexagon::S59_58, Hexagon::S61_60, Hexagon::S63_62,
862 Hexagon::S65_64, Hexagon::S67_66, Hexagon::S69_68, Hexagon::S71_70,
863 Hexagon::S73_72, Hexagon::S75_74, Hexagon::S77_76, Hexagon::S79_78,
864};
865
866static DecodeStatus
867DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/,
868 const MCDisassembler *Decoder) {
869 RegNo = RegNo >> 1;
870 if (RegNo >= std::size(SysReg64DecoderTable))
871 return MCDisassembler::Fail;
872
873 if (SysReg64DecoderTable[RegNo] == Hexagon::NoRegister)
874 return MCDisassembler::Fail;
875
876 unsigned Register = SysReg64DecoderTable[RegNo];
877 Inst.addOperand(MCOperand::createReg(Register));
878 return MCDisassembler::Success;
879}
880
881static DecodeStatus
882DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/,
883 const MCDisassembler *Decoder) {
884 using namespace Hexagon;
885
886 static const MCPhysReg GuestRegDecoderTable[] = {
887 /* 0 */ GELR, GSR, GOSP, G3,
888 /* 4 */ G4, G5, G6, G7,
889 /* 8 */ G8, G9, G10, G11,
890 /* 12 */ G12, G13, G14, G15,
891 /* 16 */ GPMUCNT4, GPMUCNT5, GPMUCNT6, GPMUCNT7,
892 /* 20 */ G20, G21, G22, G23,
893 /* 24 */ GPCYCLELO, GPCYCLEHI, GPMUCNT0, GPMUCNT1,
894 /* 28 */ GPMUCNT2, GPMUCNT3, G30, G31
895 };
896
897 if (RegNo >= std::size(GuestRegDecoderTable))
898 return MCDisassembler::Fail;
899 if (GuestRegDecoderTable[RegNo] == Hexagon::NoRegister)
900 return MCDisassembler::Fail;
901
902 unsigned Register = GuestRegDecoderTable[RegNo];
903 Inst.addOperand(MCOperand::createReg(Register));
904 return MCDisassembler::Success;
905}
906
907static DecodeStatus
908DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
909 uint64_t /*Address*/,
910 const MCDisassembler *Decoder) {
911 using namespace Hexagon;
912
913 static const MCPhysReg GuestReg64DecoderTable[] = {
914 /* 0 */ G1_0, 0, G3_2, 0,
915 /* 4 */ G5_4, 0, G7_6, 0,
916 /* 8 */ G9_8, 0, G11_10, 0,
917 /* 12 */ G13_12, 0, G15_14, 0,
918 /* 16 */ G17_16, 0, G19_18, 0,
919 /* 20 */ G21_20, 0, G23_22, 0,
920 /* 24 */ G25_24, 0, G27_26, 0,
921 /* 28 */ G29_28, 0, G31_30, 0
922 };
923
924 if (RegNo >= std::size(GuestReg64DecoderTable))
925 return MCDisassembler::Fail;
926 if (GuestReg64DecoderTable[RegNo] == Hexagon::NoRegister)
927 return MCDisassembler::Fail;
928
929 unsigned Register = GuestReg64DecoderTable[RegNo];
930 Inst.addOperand(MCOperand::createReg(Register));
931 return MCDisassembler::Success;
932}
DecodeStatus
MCDisassembler::DecodeStatus DecodeStatus
Definition AArch64Disassembler.cpp:36
Success
#define Success
Definition AArch64Disassembler.cpp:42
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
LLVM_ABI
#define LLVM_ABI
Definition Compiler.h:213
LLVM_ATTRIBUTE_UNUSED
#define LLVM_ATTRIBUTE_UNUSED
Definition Compiler.h:298
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition Compiler.h:132
sgp10ConstDecoder
static DecodeStatus sgp10ConstDecoder(MCInst &MI, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:183
DecodeIntRegsLow8RegisterClass
static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:580
DecodeGuestRegsRegisterClass
static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:882
DecodeCtrRegsRegisterClass
static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:699
brtargetDecoder
static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:794
DecodePredRegsRegisterClass
static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:681
LLVMInitializeHexagonDisassembler
LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonDisassembler()
Definition HexagonDisassembler.cpp:199
s32_0ImmDecoder
static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:783
DecodeHvxVQRRegisterClass
static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:671
unsignedImmDecoder
static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:773
DecodeHvxVRRegisterClass
static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:614
createHexagonDisassembler
static MCDisassembler * createHexagonDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition HexagonDisassembler.cpp:192
DecodeSysRegs64RegisterClass
static DecodeStatus DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:867
DecodeModRegsRegisterClass
static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:755
SysReg64DecoderTable
static const uint16_t SysReg64DecoderTable[]
Definition HexagonDisassembler.cpp:853
DecodeRegisterClass
static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo, ArrayRef< MCPhysReg > Table)
Definition HexagonDisassembler.cpp:569
DecodeSysRegsRegisterClass
static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:839
DecodeDoubleRegsRegisterClass
static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:630
n1ConstDecoder
static DecodeStatus n1ConstDecoder(MCInst &MI, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:177
SysRegDecoderTable
static const uint16_t SysRegDecoderTable[]
Definition HexagonDisassembler.cpp:809
DecodeGeneralSubRegsRegisterClass
static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:601
DecodeHvxWRRegisterClass
static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:653
DecodeIntRegsRegisterClass
static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:585
DecodeHvxQRRegisterClass
static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:690
DecodeCtrRegs64RegisterClass
static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:728
DecodeGeneralDoubleLow8RegsRegisterClass
static DecodeStatus DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:643
DecodeGuestRegs64RegisterClass
static DecodeStatus DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:908
HEXAGON_MAX_PACKET_SIZE
#define HEXAGON_MAX_PACKET_SIZE
Definition HexagonMCTargetDesc.h:36
HEXAGON_INSTR_SIZE
#define HEXAGON_INSTR_SIZE
Definition HexagonMCTargetDesc.h:32
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:110
I
#define I(x, y, z)
Definition MD5.cpp:58
Register
Promote Memory to Register
Definition Mem2Reg.cpp:110
T
#define T
Definition Mips16ISelLowering.cpp:353
OpIndex
unsigned OpIndex
Definition SPIRVModuleAnalysis.cpp:56
IntRegDecoderTable
static constexpr unsigned IntRegDecoderTable[]
Definition SparcDisassembler.cpp:65
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:41
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition ArrayRef.h:147
llvm::ArrayRef::data
const T * data() const
Definition ArrayRef.h:144
llvm::ArrayRef::slice
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.
Definition ArrayRef.h:191
llvm::MCConstantExpr::create
static LLVM_ABI const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition MCExpr.cpp:212
llvm::MCContext
Context object for machine code objects.
Definition MCContext.h:83
llvm::MCDisassembler
Superclass for all disassemblers.
Definition MCDisassembler.h:85
llvm::MCDisassembler::getContext
MCContext & getContext() const
Definition MCDisassembler.h:228
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition MCDisassembler.h:109
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition MCInst.h:188
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition MCInst.h:215
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition MCInst.h:210
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition MCInstrInfo.h:27
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition MCInst.h:40
llvm::MCOperand::createExpr
static MCOperand createExpr(const MCExpr *Val)
Definition MCInst.h:166
llvm::MCOperand::createReg
static MCOperand createReg(MCRegister Reg)
Definition MCInst.h:138
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition MCInst.h:145
llvm::MCOperand::setReg
void setReg(MCRegister Reg)
Set the register number.
Definition MCInst.h:79
llvm::MCOperand::isReg
bool isReg() const
Definition MCInst.h:65
llvm::MCOperand::getReg
MCRegister getReg() const
Returns the register number.
Definition MCInst.h:73
llvm::MCOperand::getInst
const MCInst * getInst() const
Definition MCInst.h:128
llvm::MCOperand::getExpr
const MCExpr * getExpr() const
Definition MCInst.h:118
llvm::MCOperand::createInst
static MCOperand createInst(const MCInst *Val)
Definition MCInst.h:173
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition MCSubtargetInfo.h:77
llvm::Register
Wrapper class representing virtual and physical registers.
Definition Register.h:19
llvm::Target
Target - Wrapper for Target specific information.
Definition TargetRegistry.h:146
llvm::Value
LLVM Value Representation.
Definition Value.h:75
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition raw_ostream.h:53
uint16_t
uint32_t
uint64_t
llvm::HexagonMCInstrInfo::addConstant
void addConstant(MCInst &MI, uint64_t Value, MCContext &Context)
Definition HexagonMCInstrInfo.cpp:82
llvm::HexagonMCInstrInfo::IsReverseVecRegPair
bool IsReverseVecRegPair(MCRegister VecReg)
Definition HexagonMCInstrInfo.cpp:699
llvm::HexagonMCInstrInfo::bundleSize
size_t bundleSize(MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:116
llvm::HexagonMCInstrInfo::isDuplex
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:624
llvm::HexagonMCInstrInfo::getExtentBits
unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:340
llvm::HexagonMCInstrInfo::isNewValue
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn expects newly produced value.
Definition HexagonMCInstrInfo.cpp:670
llvm::HexagonMCInstrInfo::getNewValueOp
unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:379
llvm::HexagonMCInstrInfo::getExtendableOp
unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:316
llvm::HexagonMCInstrInfo::IsVecRegPair
bool IsVecRegPair(MCRegister VecReg)
Definition HexagonMCInstrInfo.cpp:694
llvm::HexagonMCInstrInfo::bundleInstructions
iterator_range< Hexagon::PacketIterator > bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:103
llvm::HexagonMCInstrInfo::isExtendable
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:628
llvm::HexagonMCInstrInfo::extenderForIndex
MCInst const * extenderForIndex(MCInst const &MCB, size_t Index)
Definition HexagonMCInstrInfo.cpp:222
llvm::HexagonMCInstrInfo::isImmext
bool isImmext(MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:650
llvm::HexagonMCInstrInfo::getNewValueOperand
MCOperand const & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:385
llvm::HexagonMCInstrInfo::hasNewValue2
bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a second value.
Definition HexagonMCInstrInfo.cpp:520
llvm::HexagonMCInstrInfo::getExtentAlignment
unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:334
llvm::HexagonMCInstrInfo::isVector
bool isVector(MCInstrInfo const &MCII, MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:869
llvm::HexagonMCInstrInfo::getNewValueOperand2
MCOperand const & getNewValueOperand2(MCInstrInfo const &MCII, MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:411
llvm::HexagonMCInstrInfo::isExtended
bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:634
llvm::HexagonMCInstrInfo::hasNewValue
bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a value.
Definition HexagonMCInstrInfo.cpp:513
llvm::Hexagon_MC::getArchSubtarget
MCSubtargetInfo const * getArchSubtarget(MCSubtargetInfo const *STI)
Definition HexagonMCTargetDesc.cpp:526
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
Definition MicrosoftDemangle.h:132
llvm::sandboxir::getContext
Context & getContext() const
Definition BasicBlock.h:99
llvm::sandboxir::Instruction
friend class Instruction
Iterator for Instructions in a `BasicBlock.
Definition BasicBlock.h:73
llvm::support::endian::read32le
uint32_t read32le(const void *P)
Definition Endian.h:429
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition AddressRanges.h:18
llvm::Offset
@ Offset
Definition DWP.cpp:477
llvm::getTheHexagonTarget
Target & getTheHexagonTarget()
Definition HexagonTargetInfo.cpp:14
llvm::M1
unsigned M1(unsigned Val)
Definition VE.h:377
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition MCRegister.h:21
llvm::M0
unsigned M0(unsigned Val)
Definition VE.h:376
llvm::SignExtend64
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition MathExtras.h:577
raw_ostream.h
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition TargetRegistry.h:934
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