84 if (&Subtarget == &NewSubtarget)
87 Names2InstrOpCodes.
clear();
89 Names2RegMasks.
clear();
90 Names2SubRegIndices.
clear();
91 Names2TargetIndices.
clear();
92 Names2DirectTargetFlags.
clear();
93 Names2BitmaskTargetFlags.
clear();
94 Names2MMOTargetFlags.
clear();
96 initNames2RegClasses();
100void PerTargetMIParsingState::initNames2Regs() {
101 if (!Names2Regs.empty())
105 Names2Regs.insert(std::make_pair(
"noreg", 0));
107 assert(
TRI &&
"Expected target register info");
109 for (
unsigned I = 0, E =
TRI->getNumRegs();
I < E; ++
I) {
114 assert(WasInserted &&
"Expected registers to be unique case-insensitively");
121 auto RegInfo = Names2Regs.find(
RegName);
122 if (RegInfo == Names2Regs.end())
124 Reg = RegInfo->getValue();
131 std::optional<uint8_t> FV =
TRI->getVRegFlagValue(FlagName);
138void PerTargetMIParsingState::initNames2InstrOpCodes() {
139 if (!Names2InstrOpCodes.
empty())
142 assert(
TII &&
"Expected target instruction info");
143 for (
unsigned I = 0, E =
TII->getNumOpcodes();
I < E; ++
I)
149 initNames2InstrOpCodes();
150 auto InstrInfo = Names2InstrOpCodes.
find(InstrName);
151 if (InstrInfo == Names2InstrOpCodes.
end())
153 OpCode = InstrInfo->getValue();
157void PerTargetMIParsingState::initNames2RegMasks() {
158 if (!Names2RegMasks.
empty())
161 assert(
TRI &&
"Expected target register info");
165 for (
size_t I = 0, E = RegMasks.
size();
I < E; ++
I)
167 std::make_pair(
StringRef(RegMaskNames[
I]).lower(), RegMasks[
I]));
171 initNames2RegMasks();
172 auto RegMaskInfo = Names2RegMasks.
find(Identifier);
173 if (RegMaskInfo == Names2RegMasks.
end())
175 return RegMaskInfo->getValue();
178void PerTargetMIParsingState::initNames2SubRegIndices() {
179 if (!Names2SubRegIndices.
empty())
182 for (
unsigned I = 1, E =
TRI->getNumSubRegIndices();
I < E; ++
I)
183 Names2SubRegIndices.
insert(
184 std::make_pair(
TRI->getSubRegIndexName(
I),
I));
188 initNames2SubRegIndices();
189 auto SubRegInfo = Names2SubRegIndices.
find(
Name);
190 if (SubRegInfo == Names2SubRegIndices.
end())
192 return SubRegInfo->getValue();
195void PerTargetMIParsingState::initNames2TargetIndices() {
196 if (!Names2TargetIndices.
empty())
199 assert(
TII &&
"Expected target instruction info");
200 auto Indices =
TII->getSerializableTargetIndices();
201 for (
const auto &
I : Indices)
206 initNames2TargetIndices();
207 auto IndexInfo = Names2TargetIndices.
find(
Name);
208 if (IndexInfo == Names2TargetIndices.
end())
210 Index = IndexInfo->second;
214void PerTargetMIParsingState::initNames2DirectTargetFlags() {
215 if (!Names2DirectTargetFlags.
empty())
219 assert(
TII &&
"Expected target instruction info");
221 for (
const auto &
I : Flags)
222 Names2DirectTargetFlags.
insert(
228 initNames2DirectTargetFlags();
229 auto FlagInfo = Names2DirectTargetFlags.
find(
Name);
230 if (FlagInfo == Names2DirectTargetFlags.
end())
232 Flag = FlagInfo->second;
236void PerTargetMIParsingState::initNames2BitmaskTargetFlags() {
237 if (!Names2BitmaskTargetFlags.
empty())
241 assert(
TII &&
"Expected target instruction info");
243 for (
const auto &
I : Flags)
244 Names2BitmaskTargetFlags.
insert(
250 initNames2BitmaskTargetFlags();
251 auto FlagInfo = Names2BitmaskTargetFlags.
find(
Name);
252 if (FlagInfo == Names2BitmaskTargetFlags.
end())
254 Flag = FlagInfo->second;
258void PerTargetMIParsingState::initNames2MMOTargetFlags() {
259 if (!Names2MMOTargetFlags.
empty())
263 assert(
TII &&
"Expected target instruction info");
264 auto Flags =
TII->getSerializableMachineMemOperandTargetFlags();
265 for (
const auto &
I : Flags)
271 initNames2MMOTargetFlags();
272 auto FlagInfo = Names2MMOTargetFlags.
find(
Name);
273 if (FlagInfo == Names2MMOTargetFlags.
end())
275 Flag = FlagInfo->second;
279void PerTargetMIParsingState::initNames2RegClasses() {
280 if (!Names2RegClasses.
empty())
284 for (
unsigned I = 0, E =
TRI->getNumRegClasses();
I < E; ++
I) {
285 const auto *RC =
TRI->getRegClass(
I);
291void PerTargetMIParsingState::initNames2RegBanks() {
292 if (!Names2RegBanks.
empty())
310 auto RegClassInfo = Names2RegClasses.
find(
Name);
311 if (RegClassInfo == Names2RegClasses.
end())
313 return RegClassInfo->getValue();
317 auto RegBankInfo = Names2RegBanks.
find(
Name);
318 if (RegBankInfo == Names2RegBanks.
end())
320 return RegBankInfo->getValue();
325 : MF(MF), SM(&SM), IRSlots(IRSlots),
Target(
T) {
329 auto I =
VRegInfos.insert(std::make_pair(Num,
nullptr));
333 Info->VReg =
MRI.createIncompleteVirtualRegister();
334 I.first->second =
Info;
336 return *
I.first->second;
346 I.first->second =
Info;
348 return *
I.first->second;
356 Slots2Values.
insert(std::make_pair(
unsigned(Slot), V));
364 for (
const auto &Arg :
F.args())
366 for (
const auto &BB :
F) {
368 for (
const auto &
I : BB)
383struct ParsedMachineOperand {
387 std::optional<unsigned> TiedDefIdx;
391 std::optional<unsigned> &TiedDefIdx)
392 : Operand(Operand), Begin(Begin),
End(
End), TiedDefIdx(TiedDefIdx) {
395 "Only used register operands can be tied");
417 void lex(
unsigned SkipChar = 0);
431 bool parseBasicBlocks();
437 bool parseStandaloneStackObject(
int &FI);
440 bool parseMDTuple(
MDNode *&MD,
bool IsDistinct);
455 bool parseRegisterFlag(
unsigned &Flags);
457 bool parseSubRegisterIndex(
unsigned &
SubReg);
458 bool parseRegisterTiedDefIndex(
unsigned &TiedDefIdx);
460 std::optional<unsigned> &TiedDefIdx,
471 bool parseStackFrameIndex(
int &FI);
473 bool parseFixedStackFrameIndex(
int &FI);
483 bool parseDIExpression(
MDNode *&Expr);
484 bool parseDILocation(
MDNode *&Expr);
486 bool parseCFIOffset(
int &
Offset);
487 bool parseCFIRegister(
unsigned &
Reg);
489 bool parseCFIEscapeValues(std::string& Values);
500 bool parseMachineOperand(
const unsigned OpCode,
const unsigned OpIdx,
502 std::optional<unsigned> &TiedDefIdx);
503 bool parseMachineOperandAndTargetFlags(
const unsigned OpCode,
504 const unsigned OpIdx,
506 std::optional<unsigned> &TiedDefIdx);
507 bool parseOffset(int64_t &
Offset);
508 bool parseIRBlockAddressTaken(
BasicBlock *&BB);
510 bool parseAddrspace(
unsigned &Addrspace);
511 bool parseSectionID(std::optional<MBBSectionID> &SID);
512 bool parseBBID(std::optional<UniqueBBID> &BBID);
513 bool parseCallFrameSize(
unsigned &CallFrameSize);
522 bool parsePreOrPostInstrSymbol(
MCSymbol *&Symbol);
526 bool parseTargetImmMnemonic(
const unsigned OpCode,
const unsigned OpIdx,
554 bool parseInstruction(
unsigned &OpCode,
unsigned &Flags);
570 bool parseStringConstant(std::string &Result);
587 SourceRange(SourceRange), PFS(PFS) {}
589void MIParser::lex(
unsigned SkipChar) {
591 CurrentSource.substr(SkipChar), Token,
595bool MIParser::error(
const Twine &Msg) {
return error(Token.location(), Msg); }
615 assert(SourceRange.isValid() &&
"Invalid source range");
637 return "<unknown token>";
642 if (Token.isNot(TokenKind))
649 if (Token.isNot(TokenKind))
656bool MIParser::parseSectionID(std::optional<MBBSectionID> &SID) {
662 return error(
"Unknown Section ID");
665 const StringRef &S = Token.stringValue();
666 if (S ==
"Exception")
668 else if (S ==
"Cold")
671 return error(
"Unknown Section ID");
678bool MIParser::parseBBID(std::optional<UniqueBBID> &BBID) {
682 unsigned CloneID = 0;
684 return error(
"Unknown BB ID");
688 return error(
"Unknown Clone ID");
691 BBID = {BaseID, CloneID};
696bool MIParser::parseCallFrameSize(
unsigned &CallFrameSize) {
701 return error(
"Unknown call frame size");
702 CallFrameSize =
Value;
707bool MIParser::parseBasicBlockDefinition(
713 auto Loc = Token.location();
714 auto Name = Token.stringValue();
716 bool MachineBlockAddressTaken =
false;
718 bool IsLandingPad =
false;
719 bool IsInlineAsmBrIndirectTarget =
false;
720 bool IsEHFuncletEntry =
false;
721 std::optional<MBBSectionID> SectionID;
723 std::optional<UniqueBBID> BBID;
724 unsigned CallFrameSize = 0;
729 switch (Token.kind()) {
731 MachineBlockAddressTaken =
true;
735 if (parseIRBlockAddressTaken(AddressTakenIRBlock))
743 IsInlineAsmBrIndirectTarget =
true;
747 IsEHFuncletEntry =
true;
757 if (parseIRBlock(BB, MF.getFunction()))
762 if (parseSectionID(SectionID))
770 if (parseCallFrameSize(CallFrameSize))
784 BB = dyn_cast_or_null<BasicBlock>(
785 MF.getFunction().getValueSymbolTable()->lookup(
Name));
788 "' is not defined in the function '" +
791 auto *
MBB = MF.CreateMachineBasicBlock(BB, BBID);
793 bool WasInserted = MBBSlots.
insert(std::make_pair(
ID,
MBB)).second;
795 return error(Loc,
Twine(
"redefinition of machine basic block with id #") +
799 if (MachineBlockAddressTaken)
801 if (AddressTakenIRBlock)
814bool MIParser::parseBasicBlockDefinitions(
820 if (Token.isErrorOrEOF())
821 return Token.isError();
823 return error(
"expected a basic block definition before instructions");
824 unsigned BraceDepth = 0;
826 if (parseBasicBlockDefinition(MBBSlots))
828 bool IsAfterNewline =
false;
832 Token.isErrorOrEOF())
835 return error(
"basic block definition should be located at the start of "
838 IsAfterNewline =
true;
841 IsAfterNewline =
false;
846 return error(
"extraneous closing brace ('}')");
852 if (!Token.isError() && BraceDepth)
853 return error(
"expected '}'");
854 }
while (!Token.isErrorOrEOF());
855 return Token.isError();
863 if (Token.isNewlineOrEOF())
867 return error(
"expected a named register");
869 if (parseNamedRegister(Reg))
877 return error(
"expected a lane mask");
879 "Use correct get-function for lane mask");
882 return error(
"invalid lane mask value");
896 if (Token.isNewlineOrEOF())
900 return error(
"expected a machine basic block reference");
909 return error(
"expected an integer literal after '('");
943 bool ExplicitSuccessors =
false;
946 if (parseBasicBlockSuccessors(
MBB))
948 ExplicitSuccessors =
true;
950 if (parseBasicBlockLiveins(
MBB))
956 if (!Token.isNewlineOrEOF())
957 return error(
"expected line break at the end of a list");
962 bool IsInBundle =
false;
986 return error(
"nested instruction bundles are not allowed");
995 assert(Token.isNewlineOrEOF() &&
"MI is not fully parsed");
1000 if (!ExplicitSuccessors) {
1007 if (IsFallthrough) {
1008 AddFalthroughFrom = &
MBB;
1017bool MIParser::parseBasicBlocks() {
1022 if (Token.isErrorOrEOF())
1023 return Token.isError();
1032 if (AddFalthroughFrom) {
1036 AddFalthroughFrom =
nullptr;
1038 if (parseBasicBlock(*
MBB, AddFalthroughFrom))
1051 while (Token.isRegister() || Token.isRegisterFlag()) {
1052 auto Loc = Token.location();
1053 std::optional<unsigned> TiedDefIdx;
1054 if (parseRegisterOperand(MO, TiedDefIdx,
true))
1057 ParsedMachineOperand(MO, Loc, Token.location(), TiedDefIdx));
1066 if (Token.isError() || parseInstruction(OpCode, Flags))
1078 auto Loc = Token.location();
1079 std::optional<unsigned> TiedDefIdx;
1080 if (parseMachineOperandAndTargetFlags(OpCode,
Operands.size(), MO, TiedDefIdx))
1083 ParsedMachineOperand(MO, Loc, Token.location(), TiedDefIdx));
1088 return error(
"expected ',' before the next machine operand");
1092 MCSymbol *PreInstrSymbol =
nullptr;
1094 if (parsePreOrPostInstrSymbol(PreInstrSymbol))
1096 MCSymbol *PostInstrSymbol =
nullptr;
1098 if (parsePreOrPostInstrSymbol(PostInstrSymbol))
1100 MDNode *HeapAllocMarker =
nullptr;
1102 if (parseHeapAllocMarker(HeapAllocMarker))
1104 MDNode *PCSections =
nullptr;
1106 if (parsePCSections(PCSections))
1109 unsigned CFIType = 0;
1113 return error(
"expected an integer literal after 'cfi-type'");
1123 unsigned InstrNum = 0;
1127 return error(
"expected an integer literal after 'debug-instr-number'");
1144 if (parseDILocation(
Node))
1147 return error(
"expected a metadata node after 'debug-location'");
1148 if (!isa<DILocation>(
Node))
1149 return error(
"referenced metadata is not a DILocation");
1157 while (!Token.isNewlineOrEOF()) {
1159 if (parseMachineMemoryOperand(
MemOp))
1162 if (Token.isNewlineOrEOF())
1165 return error(
"expected ',' before the next machine memory operand");
1170 const auto &MCID = MF.getSubtarget().getInstrInfo()->get(OpCode);
1171 if (!MCID.isVariadic()) {
1173 if (verifyImplicitOperands(
Operands, MCID))
1177 MI = MF.CreateMachineInstr(MCID, DebugLocation,
true);
1178 MI->setFlags(Flags);
1182 for (
const auto &Operand :
Operands)
1183 MI->addOperand(MF, Operand.Operand);
1188 MI->setPreInstrSymbol(MF, PreInstrSymbol);
1189 if (PostInstrSymbol)
1190 MI->setPostInstrSymbol(MF, PostInstrSymbol);
1191 if (HeapAllocMarker)
1192 MI->setHeapAllocMarker(MF, HeapAllocMarker);
1194 MI->setPCSections(MF, PCSections);
1196 MI->setCFIType(MF, CFIType);
1197 if (!MemOperands.
empty())
1198 MI->setMemRefs(MF, MemOperands);
1200 MI->setDebugInstrNum(InstrNum);
1207 return error(
"expected a machine basic block reference");
1213 "expected end of string after the machine basic block reference");
1217bool MIParser::parseStandaloneNamedRegister(
Register &Reg) {
1220 return error(
"expected a named register");
1221 if (parseNamedRegister(Reg))
1225 return error(
"expected end of string after the register reference");
1229bool MIParser::parseStandaloneVirtualRegister(
VRegInfo *&Info) {
1232 return error(
"expected a virtual register");
1233 if (parseVirtualRegister(Info))
1237 return error(
"expected end of string after the register reference");
1241bool MIParser::parseStandaloneRegister(
Register &Reg) {
1245 return error(
"expected either a named or virtual register");
1248 if (parseRegister(Reg, Info))
1253 return error(
"expected end of string after the register reference");
1257bool MIParser::parseStandaloneStackObject(
int &FI) {
1260 return error(
"expected a stack object");
1261 if (parseStackFrameIndex(FI))
1264 return error(
"expected end of string after the stack object reference");
1268bool MIParser::parseStandaloneMDNode(
MDNode *&
Node) {
1274 if (parseDIExpression(
Node))
1277 if (parseDILocation(
Node))
1280 return error(
"expected a metadata node");
1282 return error(
"expected end of string after the metadata node");
1286bool MIParser::parseMachineMetadata() {
1289 return error(
"expected a metadata node");
1293 return error(
"expected metadata id after '!'");
1304 return error(
"expected a metadata node");
1308 if (parseMDTuple(MD, IsDistinct))
1311 auto FI = PFS.MachineForwardRefMDNodes.find(
ID);
1312 if (FI != PFS.MachineForwardRefMDNodes.end()) {
1314 PFS.MachineForwardRefMDNodes.erase(FI);
1316 assert(PFS.MachineMetadataNodes[
ID] == MD &&
"Tracking VH didn't work");
1318 auto [It,
Inserted] = PFS.MachineMetadataNodes.try_emplace(
ID);
1320 return error(
"Metadata id is already used");
1321 It->second.reset(MD);
1327bool MIParser::parseMDTuple(
MDNode *&MD,
bool IsDistinct) {
1329 if (parseMDNodeVector(Elts))
1338 return error(
"expected '{' here");
1359 return error(
"expected end of metadata node");
1367bool MIParser::parseMetadata(
Metadata *&MD) {
1369 return error(
"expected '!' here");
1374 if (parseStringConstant(Str))
1381 return error(
"expected metadata id after '!'");
1383 SMLoc Loc = mapSMLoc(Token.location());
1390 auto NodeInfo = PFS.IRSlots.MetadataNodes.find(
ID);
1391 if (NodeInfo != PFS.IRSlots.MetadataNodes.end()) {
1392 MD = NodeInfo->second.get();
1396 NodeInfo = PFS.MachineMetadataNodes.find(
ID);
1397 if (NodeInfo != PFS.MachineMetadataNodes.end()) {
1398 MD = NodeInfo->second.get();
1402 auto &FwdRef = PFS.MachineForwardRefMDNodes[
ID];
1403 FwdRef = std::make_pair(
1405 PFS.MachineMetadataNodes[
ID].reset(FwdRef.first.get());
1406 MD = FwdRef.first.get();
1413 return MO.
isDef() ?
"implicit-def" :
"implicit";
1418 assert(Reg.isPhysical() &&
"expected phys reg");
1446 const auto *
TRI = MF.getSubtarget().getRegisterInfo();
1447 assert(
TRI &&
"Expected target register info");
1448 for (
const auto &
I : ImplicitOperands) {
1452 Twine(
"missing implicit register operand '") +
1459bool MIParser::parseInstruction(
unsigned &OpCode,
unsigned &Flags) {
1522 return error(
"expected a machine instruction");
1523 StringRef InstrName = Token.stringValue();
1524 if (PFS.Target.parseInstrName(InstrName, OpCode))
1525 return error(
Twine(
"unknown machine instruction name '") + InstrName +
"'");
1530bool MIParser::parseNamedRegister(
Register &Reg) {
1533 if (PFS.Target.getRegisterByName(
Name, Reg))
1538bool MIParser::parseNamedVirtualRegister(
VRegInfo *&Info) {
1543 Info = &PFS.getVRegInfoNamed(
Name);
1547bool MIParser::parseVirtualRegister(
VRegInfo *&Info) {
1549 return parseNamedVirtualRegister(Info);
1554 Info = &PFS.getVRegInfo(
ID);
1559 switch (Token.kind()) {
1564 return parseNamedRegister(Reg);
1567 if (parseVirtualRegister(Info))
1579 return error(
"expected '_', register class, or register bank name");
1594 return error(Loc,
Twine(
"conflicting register classes, previously: ") +
1603 return error(Loc,
"register class specification on generic register");
1611 RegBank = PFS.Target.getRegBank(
Name);
1613 return error(Loc,
"expected '_', register class, or register bank name");
1624 return error(Loc,
"conflicting generic register banks");
1630 return error(Loc,
"register bank specification on normal register");
1635bool MIParser::parseRegisterFlag(
unsigned &Flags) {
1636 const unsigned OldFlags =
Flags;
1637 switch (Token.kind()) {
1671 if (OldFlags == Flags)
1674 return error(
"duplicate '" + Token.stringValue() +
"' register flag");
1679bool MIParser::parseSubRegisterIndex(
unsigned &
SubReg) {
1683 return error(
"expected a subregister index after '.'");
1684 auto Name = Token.stringValue();
1687 return error(
Twine(
"use of unknown subregister index '") +
Name +
"'");
1692bool MIParser::parseRegisterTiedDefIndex(
unsigned &TiedDefIdx) {
1696 return error(
"expected an integer literal after 'tied-def'");
1708 for (
unsigned I = 0, E =
Operands.size();
I != E; ++
I) {
1713 unsigned DefIdx = *
Operands[
I].TiedDefIdx;
1716 Twine(
"use of invalid tied-def operand index '" +
1717 Twine(DefIdx) +
"'; instruction has only ") +
1718 Twine(E) +
" operands");
1719 const auto &DefOperand =
Operands[DefIdx].Operand;
1720 if (!DefOperand.isReg() || !DefOperand.isDef())
1723 Twine(
"use of invalid tied-def operand index '") +
1724 Twine(DefIdx) +
"'; the operand #" +
Twine(DefIdx) +
1725 " isn't a defined register");
1727 for (
const auto &TiedPair : TiedRegisterPairs) {
1728 if (TiedPair.first == DefIdx)
1730 Twine(
"the tied-def operand #") +
Twine(DefIdx) +
1731 " is already tied with another register operand");
1733 TiedRegisterPairs.push_back(std::make_pair(DefIdx,
I));
1737 for (
const auto &TiedPair : TiedRegisterPairs)
1738 MI.tieOperands(TiedPair.first, TiedPair.second);
1743 std::optional<unsigned> &TiedDefIdx,
1746 while (Token.isRegisterFlag()) {
1747 if (parseRegisterFlag(Flags))
1750 if (!Token.isRegister())
1751 return error(
"expected a register after register flags");
1754 if (parseRegister(Reg,
RegInfo))
1759 if (parseSubRegisterIndex(
SubReg))
1761 if (!
Reg.isVirtual())
1762 return error(
"subregister index expects a virtual register");
1765 if (!
Reg.isVirtual())
1766 return error(
"register class specification expects a virtual register");
1768 if (parseRegisterClassOrBank(*
RegInfo))
1775 if (!parseRegisterTiedDefIndex(
Idx))
1780 if (parseLowLevelType(Token.location(), Ty))
1781 return error(
"expected tied-def or low-level type after '('");
1786 if (
MRI.getType(Reg).isValid() &&
MRI.getType(Reg) != Ty)
1787 return error(
"inconsistent type for generic virtual register");
1790 MRI.setType(Reg, Ty);
1791 MRI.noteNewVirtualRegister(Reg);
1796 if (!
Reg.isVirtual())
1797 return error(
"unexpected type on physical register");
1800 if (parseLowLevelType(Token.location(), Ty))
1806 if (
MRI.getType(Reg).isValid() &&
MRI.getType(Reg) != Ty)
1807 return error(
"inconsistent type for generic virtual register");
1810 MRI.setType(Reg, Ty);
1811 }
else if (
Reg.isVirtual()) {
1817 return error(
"generic virtual registers must have a type");
1822 return error(
"cannot have a killed def operand");
1825 return error(
"cannot have a dead use operand");
1839 const APSInt &
Int = Token.integerValue();
1840 if (
auto SImm =
Int.trySExtValue();
Int.isSigned() && SImm.has_value())
1842 else if (
auto UImm =
Int.tryZExtValue(); !
Int.isSigned() && UImm.has_value())
1845 return error(
"integer literal is too large to be an immediate operand");
1850bool MIParser::parseTargetImmMnemonic(
const unsigned OpCode,
1851 const unsigned OpIdx,
1855 auto Loc = Token.location();
1861 Len += Token.range().size();
1870 Src =
StringRef(Loc, Len + Token.stringValue().size());
1875 ->
bool { return error(Loc, Msg); }))
1887 auto Source = StringValue.
str();
1892 return ErrCB(Loc + Err.getColumnNo(), Err.getMessage());
1898 return ::parseIRConstant(
1899 Loc, StringValue, PFS,
C,
1901 return error(Loc, Msg);
1914 return Size != 0 && isUInt<16>(
Size);
1918 return NumElts != 0 && isUInt<16>(NumElts);
1922 return isUInt<24>(AddrSpace);
1926 if (Token.range().front() ==
's' || Token.range().front() ==
'p') {
1929 return error(
"expected integers after 's'/'p' type character");
1932 if (Token.range().front() ==
's') {
1936 return error(
"invalid size for scalar type");
1943 }
else if (Token.range().front() ==
'p') {
1947 return error(
"invalid address space number");
1956 return error(Loc,
"expected sN, pA, <M x sN>, <M x pA>, <vscale x M x sN>, "
1957 "or <vscale x M x pA> for GlobalISel type");
1965 return error(
"expected <vscale x M x sN> or <vscale x M x pA>");
1969 auto GetError = [
this, &HasVScale, Loc]() {
1972 Loc,
"expected <vscale x M x sN> or <vscale M x pA> for vector type");
1973 return error(Loc,
"expected <M x sN> or <M x pA> for vector type");
1978 uint64_t NumElements = Token.integerValue().getZExtValue();
1980 return error(
"invalid number of vector elements");
1988 if (Token.range().front() !=
's' && Token.range().front() !=
'p')
1993 return error(
"expected integers after 's'/'p' type character");
1995 if (Token.range().front() ==
's') {
1998 return error(
"invalid size for scalar element in vector");
2000 }
else if (Token.range().front() ==
'p') {
2004 return error(
"invalid address space number");
2023 if (TypeStr.
front() !=
'i' && TypeStr.
front() !=
's' &&
2024 TypeStr.
front() !=
'p')
2026 "a typed immediate operand should start with one of 'i', 's', or 'p'");
2029 return error(
"expected integers after 'i'/'s'/'p' type character");
2031 auto Loc = Token.location();
2035 !(Token.range() ==
"true" || Token.range() ==
"false"))
2036 return error(
"expected an integer literal");
2046 auto Loc = Token.location();
2050 return error(
"expected a floating point literal");
2061 assert(S[0] ==
'0' && tolower(S[1]) ==
'x');
2063 if (!isxdigit(S[2]))
2066 APInt A(V.size()*4, V, 16);
2070 unsigned NumBits = (
A == 0) ? 32 :
A.getActiveBits();
2081 return ErrCB(Token.
location(),
"expected 32-bit integer (too large)");
2089 if (
A.getBitWidth() > 32)
2090 return ErrCB(Token.
location(),
"expected 32-bit integer (too large)");
2091 Result =
A.getZExtValue();
2097bool MIParser::getUnsigned(
unsigned &Result) {
2098 return ::getUnsigned(
2100 return error(Loc, Msg);
2110 auto MBBInfo = PFS.MBBSlots.find(
Number);
2111 if (MBBInfo == PFS.MBBSlots.end())
2112 return error(
Twine(
"use of undefined machine basic block #") +
2114 MBB = MBBInfo->second;
2117 if (!Token.stringValue().empty() && Token.stringValue() !=
MBB->
getName())
2119 " isn't '" + Token.stringValue() +
"'");
2132bool MIParser::parseStackFrameIndex(
int &FI) {
2137 auto ObjectInfo = PFS.StackObjectSlots.find(
ID);
2138 if (ObjectInfo == PFS.StackObjectSlots.end())
2142 if (
const auto *Alloca =
2143 MF.getFrameInfo().getObjectAllocation(ObjectInfo->second))
2144 Name = Alloca->getName();
2145 if (!Token.stringValue().empty() && Token.stringValue() !=
Name)
2147 "' isn't '" + Token.stringValue() +
"'");
2149 FI = ObjectInfo->second;
2155 if (parseStackFrameIndex(FI))
2161bool MIParser::parseFixedStackFrameIndex(
int &FI) {
2166 auto ObjectInfo = PFS.FixedStackObjectSlots.find(
ID);
2167 if (ObjectInfo == PFS.FixedStackObjectSlots.end())
2168 return error(
Twine(
"use of undefined fixed stack object '%fixed-stack.") +
2171 FI = ObjectInfo->second;
2175bool MIParser::parseFixedStackObjectOperand(
MachineOperand &Dest) {
2177 if (parseFixedStackFrameIndex(FI))
2186 switch (Token.
kind()) {
2191 return ErrCB(Token.
location(),
Twine(
"use of undefined global value '") +
2192 Token.
range() +
"'");
2201 return ErrCB(Token.
location(),
Twine(
"use of undefined global value '@") +
2202 Twine(GVIdx) +
"'");
2211bool MIParser::parseGlobalValue(
GlobalValue *&GV) {
2212 return ::parseGlobalValue(
2215 return error(Loc, Msg);
2225 if (parseOperandsOffset(Dest))
2230bool MIParser::parseConstantPoolIndexOperand(
MachineOperand &Dest) {
2237 return error(
"use of undefined constant '%const." +
Twine(
ID) +
"'");
2240 if (parseOperandsOffset(Dest))
2250 auto JumpTableEntryInfo = PFS.JumpTableSlots.find(
ID);
2251 if (JumpTableEntryInfo == PFS.JumpTableSlots.end())
2252 return error(
"use of undefined jump table '%jump-table." +
Twine(
ID) +
"'");
2260 const char *
Symbol = MF.createExternalSymbolName(Token.stringValue());
2263 if (parseOperandsOffset(Dest))
2273 if (parseOperandsOffset(Dest))
2278bool MIParser::parseSubRegisterIndexOperand(
MachineOperand &Dest) {
2281 unsigned SubRegIndex = PFS.Target.getSubRegIndex(Token.stringValue());
2282 if (SubRegIndex == 0)
2292 auto Loc = Token.location();
2295 return error(
"expected metadata id after '!'");
2299 auto NodeInfo = PFS.IRSlots.MetadataNodes.find(
ID);
2300 if (NodeInfo == PFS.IRSlots.MetadataNodes.end()) {
2301 NodeInfo = PFS.MachineMetadataNodes.find(
ID);
2302 if (NodeInfo == PFS.MachineMetadataNodes.end())
2303 return error(Loc,
"use of undefined metadata '!" +
Twine(
ID) +
"'");
2306 Node = NodeInfo->second.get();
2310bool MIParser::parseDIExpression(
MDNode *&Expr) {
2313 CurrentSource,
Read,
Error, *PFS.MF.getFunction().getParent(),
2315 CurrentSource = CurrentSource.substr(
Read);
2322bool MIParser::parseDILocation(
MDNode *&Loc) {
2326 bool HaveLine =
false;
2328 unsigned Column = 0;
2330 MDNode *InlinedAt =
nullptr;
2331 bool ImplicitCode =
false;
2339 if (Token.stringValue() ==
"line") {
2344 Token.integerValue().isSigned())
2345 return error(
"expected unsigned integer");
2346 Line = Token.integerValue().getZExtValue();
2351 if (Token.stringValue() ==
"column") {
2356 Token.integerValue().isSigned())
2357 return error(
"expected unsigned integer");
2358 Column = Token.integerValue().getZExtValue();
2362 if (Token.stringValue() ==
"scope") {
2367 return error(
"expected metadata node");
2368 if (!isa<DIScope>(Scope))
2369 return error(
"expected DIScope node");
2372 if (Token.stringValue() ==
"inlinedAt") {
2380 if (parseDILocation(InlinedAt))
2383 return error(
"expected metadata node");
2384 if (!isa<DILocation>(InlinedAt))
2385 return error(
"expected DILocation node");
2388 if (Token.stringValue() ==
"isImplicitCode") {
2393 return error(
"expected true/false");
2397 if (Token.stringValue() ==
"true")
2398 ImplicitCode =
true;
2399 else if (Token.stringValue() ==
"false")
2400 ImplicitCode =
false;
2402 return error(
"expected true/false");
2407 return error(
Twine(
"invalid DILocation argument '") +
2408 Token.stringValue() +
"'");
2416 return error(
"DILocation requires line number");
2418 return error(
"DILocation requires a scope");
2420 Loc =
DILocation::get(MF.getFunction().getContext(), Line, Column, Scope,
2421 InlinedAt, ImplicitCode);
2431 if (parseDIExpression(
Node))
2438bool MIParser::parseCFIOffset(
int &
Offset) {
2440 return error(
"expected a cfi offset");
2441 if (Token.integerValue().getSignificantBits() > 32)
2442 return error(
"expected a 32 bit integer (the cfi offset is too large)");
2443 Offset = (int)Token.integerValue().getExtValue();
2448bool MIParser::parseCFIRegister(
unsigned &Reg) {
2450 return error(
"expected a cfi register");
2452 if (parseNamedRegister(LLVMReg))
2454 const auto *
TRI = MF.getSubtarget().getRegisterInfo();
2455 assert(
TRI &&
"Expected target register info");
2456 int DwarfReg =
TRI->getDwarfRegNum(LLVMReg,
true);
2458 return error(
"invalid DWARF register");
2464bool MIParser::parseCFIAddressSpace(
unsigned &
AddressSpace) {
2466 return error(
"expected a cfi address space literal");
2467 if (Token.integerValue().isSigned())
2468 return error(
"expected an unsigned integer (cfi address space)");
2474bool MIParser::parseCFIEscapeValues(std::string &Values) {
2477 return error(
"expected a hexadecimal literal");
2481 if (
Value > UINT8_MAX)
2482 return error(
"expected a 8-bit integer (too large)");
2490 auto Kind = Token.kind();
2498 if (parseCFIRegister(Reg))
2513 CFIIndex = MF.addFrameInst(
2517 if (parseCFIRegister(Reg))
2523 if (parseCFIOffset(
Offset))
2529 if (parseCFIOffset(
Offset))
2531 CFIIndex = MF.addFrameInst(
2553 if (parseCFIRegister(Reg))
2561 if (parseCFIRegister(Reg))
2568 parseCFIRegister(Reg2))
2587 if (parseCFIEscapeValues(Values))
2601 switch (Token.kind()) {
2603 BB = dyn_cast_or_null<BasicBlock>(
2604 F.getValueSymbolTable()->lookup(Token.stringValue()));
2606 return error(
Twine(
"use of undefined IR block '") + Token.range() +
"'");
2610 unsigned SlotNumber = 0;
2613 BB =
const_cast<BasicBlock *
>(getIRBlock(SlotNumber,
F));
2615 return error(
Twine(
"use of undefined IR block '%ir-block.") +
2616 Twine(SlotNumber) +
"'");
2632 return error(
"expected a global value");
2636 auto *
F = dyn_cast<Function>(GV);
2638 return error(
"expected an IR function reference");
2644 return error(
"expected an IR block reference");
2645 if (parseIRBlock(BB, *
F))
2651 if (parseOperandsOffset(Dest))
2660 return error(
"expected syntax intrinsic(@llvm.whatever)");
2663 return error(
"expected syntax intrinsic(@llvm.whatever)");
2665 std::string
Name = std::string(Token.stringValue());
2669 return error(
"expected ')' to terminate intrinsic name");
2674 return error(
"unknown intrinsic name");
2686 return error(
"expected syntax intpred(whatever) or floatpred(whatever");
2689 return error(
"whatever");
2712 return error(
"invalid floating-point predicate");
2727 return error(
"invalid integer predicate");
2733 return error(
"predicate should be terminated by ')'.");
2743 return error(
"expected syntax shufflemask(<integer or undef>, ...)");
2750 const APSInt &
Int = Token.integerValue();
2753 return error(
"expected integer constant");
2759 return error(
"shufflemask should be terminated by ')'.");
2771 return error(
"expected syntax dbg-instr-ref(<unsigned>, <unsigned>)");
2774 return error(
"expected unsigned integer for instruction index");
2775 uint64_t InstrIdx = Token.integerValue().getZExtValue();
2776 assert(InstrIdx <= std::numeric_limits<unsigned>::max() &&
2777 "Instruction reference's instruction index is too large");
2781 return error(
"expected syntax dbg-instr-ref(<unsigned>, <unsigned>)");
2784 return error(
"expected unsigned integer for operand index");
2785 uint64_t OpIdx = Token.integerValue().getZExtValue();
2786 assert(OpIdx <= std::numeric_limits<unsigned>::max() &&
2787 "Instruction reference's operand index is too large");
2791 return error(
"expected syntax dbg-instr-ref(<unsigned>, <unsigned>)");
2803 return error(
"expected the name of the target index");
2805 if (PFS.Target.getTargetIndex(Token.stringValue(), Index))
2806 return error(
"use of undefined target index '" + Token.stringValue() +
"'");
2811 if (parseOperandsOffset(Dest))
2816bool MIParser::parseCustomRegisterMaskOperand(
MachineOperand &Dest) {
2817 assert(Token.stringValue() ==
"CustomRegMask" &&
"Expected a custom RegMask");
2826 return error(
"expected a named register");
2828 if (parseNamedRegister(Reg))
2843bool MIParser::parseLiveoutRegisterMaskOperand(
MachineOperand &Dest) {
2851 return error(
"expected a named register");
2853 if (parseNamedRegister(Reg))
2868bool MIParser::parseMachineOperand(
const unsigned OpCode,
const unsigned OpIdx,
2870 std::optional<unsigned> &TiedDefIdx) {
2871 switch (Token.kind()) {
2886 return parseRegisterOperand(Dest, TiedDefIdx);
2888 return parseImmediateOperand(Dest);
2896 return parseFPImmediateOperand(Dest);
2898 return parseMBBOperand(Dest);
2900 return parseStackObjectOperand(Dest);
2902 return parseFixedStackObjectOperand(Dest);
2905 return parseGlobalAddressOperand(Dest);
2907 return parseConstantPoolIndexOperand(Dest);
2909 return parseJumpTableIndexOperand(Dest);
2911 return parseExternalSymbolOperand(Dest);
2913 return parseMCSymbolOperand(Dest);
2915 return parseSubRegisterIndexOperand(Dest);
2918 return parseMetadataOperand(Dest);
2936 return parseCFIOperand(Dest);
2938 return parseBlockAddressOperand(Dest);
2940 return parseIntrinsicOperand(Dest);
2942 return parseTargetIndexOperand(Dest);
2944 return parseLiveoutRegisterMaskOperand(Dest);
2947 return parsePredicateOperand(Dest);
2949 return parseShuffleMaskOperand(Dest);
2951 return parseDbgInstrRefOperand(Dest);
2955 if (
const auto *RegMask = PFS.Target.getRegMask(Token.stringValue())) {
2959 }
else if (Token.stringValue() ==
"CustomRegMask") {
2960 return parseCustomRegisterMaskOperand(Dest);
2962 return parseTypedImmediateOperand(Dest);
2964 const auto *
TII = MF.getSubtarget().getInstrInfo();
2965 if (
const auto *Formatter =
TII->getMIRFormatter()) {
2966 return parseTargetImmMnemonic(OpCode, OpIdx, Dest, *Formatter);
2972 return error(
"expected a machine operand");
2977bool MIParser::parseMachineOperandAndTargetFlags(
2978 const unsigned OpCode,
const unsigned OpIdx,
MachineOperand &Dest,
2979 std::optional<unsigned> &TiedDefIdx) {
2981 bool HasTargetFlags =
false;
2983 HasTargetFlags =
true;
2988 return error(
"expected the name of the target flag");
2989 if (PFS.Target.getDirectTargetFlag(Token.stringValue(), TF)) {
2990 if (PFS.Target.getBitmaskTargetFlag(Token.stringValue(), TF))
2991 return error(
"use of undefined target flag '" + Token.stringValue() +
2998 return error(
"expected the name of the target flag");
2999 unsigned BitFlag = 0;
3000 if (PFS.Target.getBitmaskTargetFlag(Token.stringValue(), BitFlag))
3001 return error(
"use of undefined target flag '" + Token.stringValue() +
3010 auto Loc = Token.location();
3011 if (parseMachineOperand(OpCode, OpIdx, Dest, TiedDefIdx))
3013 if (!HasTargetFlags)
3016 return error(Loc,
"register operands can't have target flags");
3021bool MIParser::parseOffset(int64_t &
Offset) {
3028 return error(
"expected an integer literal after '" + Sign +
"'");
3029 if (Token.integerValue().getSignificantBits() > 64)
3030 return error(
"expected 64-bit integer (too large)");
3031 Offset = Token.integerValue().getExtValue();
3038bool MIParser::parseIRBlockAddressTaken(
BasicBlock *&BB) {
3042 return error(
"expected basic block after 'ir_block_address_taken'");
3044 if (parseIRBlock(BB, MF.getFunction()))
3051bool MIParser::parseAlignment(
uint64_t &Alignment) {
3055 return error(
"expected an integer literal after 'align'");
3056 if (getUint64(Alignment))
3061 return error(
"expected a power-of-2 literal after 'align'");
3066bool MIParser::parseAddrspace(
unsigned &Addrspace) {
3070 return error(
"expected an integer literal after 'addrspace'");
3087 switch (Token.
kind()) {
3093 unsigned SlotNumber = 0;
3121 return ErrCB(Token.
location(),
Twine(
"use of undefined IR value '") + Token.
range() +
"'");
3125bool MIParser::parseIRValue(
const Value *&V) {
3126 return ::parseIRValue(
3128 return error(Loc, Msg);
3132bool MIParser::getUint64(
uint64_t &Result) {
3133 if (Token.hasIntegerValue()) {
3134 if (Token.integerValue().getActiveBits() > 64)
3135 return error(
"expected 64-bit integer (too large)");
3136 Result = Token.integerValue().getZExtValue();
3143 if (
A.getBitWidth() > 64)
3144 return error(
"expected 64-bit integer (too large)");
3151bool MIParser::getHexUint(
APInt &Result) {
3152 return ::getHexUint(Token, Result);
3156 const auto OldFlags =
Flags;
3157 switch (Token.kind()) {
3172 if (PFS.Target.getMMOTargetFlag(Token.stringValue(), TF))
3173 return error(
"use of undefined target MMO flag '" + Token.stringValue() +
3181 if (OldFlags == Flags)
3184 return error(
"duplicate '" + Token.stringValue() +
"' memory operand flag");
3190 switch (Token.kind()) {
3192 PSV = MF.getPSVManager().getStack();
3195 PSV = MF.getPSVManager().getGOT();
3198 PSV = MF.getPSVManager().getJumpTable();
3201 PSV = MF.getPSVManager().getConstantPool();
3205 if (parseFixedStackFrameIndex(FI))
3207 PSV = MF.getPSVManager().getFixedStack(FI);
3213 if (parseStackFrameIndex(FI))
3215 PSV = MF.getPSVManager().getFixedStack(FI);
3221 switch (Token.kind()) {
3227 PSV = MF.getPSVManager().getGlobalValueCallEntry(GV);
3231 PSV = MF.getPSVManager().getExternalSymbolCallEntry(
3232 MF.createExternalSymbolName(Token.stringValue()));
3236 "expected a global value or an external symbol after 'call-entry'");
3241 const auto *
TII = MF.getSubtarget().getInstrInfo();
3242 if (
const auto *Formatter =
TII->getMIRFormatter()) {
3243 if (Formatter->parseCustomPseudoSourceValue(
3244 Token.stringValue(), MF, PFS, PSV,
3246 return error(Loc, Msg);
3250 return error(
"unable to parse target custom pseudo source value");
3266 if (parseMemoryPseudoSourceValue(PSV))
3279 return error(
"expected an IR value reference");
3280 const Value *
V =
nullptr;
3283 if (V && !
V->getType()->isPointerTy())
3284 return error(
"expected a pointer IR value");
3293bool MIParser::parseOptionalScope(
LLVMContext &Context,
3299 return error(
"expected '(' in syncscope");
3302 if (parseStringConstant(SSN))
3307 return error(
"expected ')' in syncscope");
3313bool MIParser::parseOptionalAtomicOrdering(
AtomicOrdering &Order) {
3332 return error(
"expected an atomic scope, ordering or a size specification");
3339 while (Token.isMemoryOperandFlag()) {
3340 if (parseMemoryOperandFlag(Flags))
3344 (Token.stringValue() !=
"load" && Token.stringValue() !=
"store"))
3345 return error(
"expected 'load' or 'store' memory operation");
3346 if (Token.stringValue() ==
"load")
3360 if (parseOptionalScope(MF.getFunction().getContext(), SSID))
3365 if (parseOptionalAtomicOrdering(Order))
3368 if (parseOptionalAtomicOrdering(FailureOrder))
3374 return error(
"expected memory LLT, the size integer literal or 'unknown-size' after "
3375 "memory operation");
3380 if (getUint64(
Size))
3391 if (parseLowLevelType(Token.location(), MemoryType))
3404 if (Token.stringValue() !=
Word)
3408 if (parseMachinePointerInfo(
Ptr))
3418 switch (Token.kind()) {
3424 if (
Ptr.Offset & (Alignment - 1)) {
3429 return error(
"specified alignment is more aligned than offset");
3431 BaseAlignment = Alignment;
3440 if (parseAddrspace(
Ptr.AddrSpace))
3465 return error(
"expected 'align' or '!tbaa' or '!alias.scope' or "
3466 "'!noalias' or '!range'");
3471 Dest = MF.getMachineMemOperand(
Ptr, Flags, MemoryType,
Align(BaseAlignment),
3472 AAInfo,
Range, SSID, Order, FailureOrder);
3476bool MIParser::parsePreOrPostInstrSymbol(
MCSymbol *&Symbol) {
3479 "Invalid token for a pre- post-instruction symbol!");
3482 return error(
"expected a symbol after 'pre-instr-symbol'");
3483 Symbol = getOrCreateMCSymbol(Token.stringValue());
3489 return error(
"expected ',' before the next machine operand");
3494bool MIParser::parseHeapAllocMarker(
MDNode *&
Node) {
3496 "Invalid token for a heap alloc marker!");
3501 return error(
"expected a MDNode after 'heap-alloc-marker'");
3506 return error(
"expected ',' before the next machine operand");
3511bool MIParser::parsePCSections(
MDNode *&
Node) {
3513 "Invalid token for a PC sections!");
3518 return error(
"expected a MDNode after 'pcsections'");
3523 return error(
"expected ',' before the next machine operand");
3533 for (
const auto &BB :
F) {
3539 Slots2BasicBlocks.
insert(std::make_pair(
unsigned(Slot), &BB));
3546 return Slots2BasicBlocks.
lookup(Slot);
3549const BasicBlock *MIParser::getIRBlock(
unsigned Slot) {
3550 if (Slots2BasicBlocks.empty())
3556 if (&
F == &MF.getFunction())
3557 return getIRBlock(Slot);
3569 return MF.getContext().getOrCreateSymbol(
Name);
3572bool MIParser::parseStringConstant(std::string &Result) {
3574 return error(
"expected string constant");
3575 Result = std::string(Token.stringValue());
3583 return MIParser(PFS,
Error, Src).parseBasicBlockDefinitions(PFS.
MBBSlots);
3588 return MIParser(PFS,
Error, Src).parseBasicBlocks();
3594 return MIParser(PFS,
Error, Src).parseStandaloneMBB(
MBB);
3600 return MIParser(PFS,
Error, Src).parseStandaloneRegister(Reg);
3606 return MIParser(PFS,
Error, Src).parseStandaloneNamedRegister(Reg);
3612 return MIParser(PFS,
Error, Src).parseStandaloneVirtualRegister(
Info);
3618 return MIParser(PFS,
Error, Src).parseStandaloneStackObject(FI);
3623 return MIParser(PFS,
Error, Src).parseStandaloneMDNode(Node);
3628 return MIParser(PFS,
Error, Src, SrcRange).parseMachineMetadata();
3636 ErrorCallback(Loc, Msg);
3640 return ::parseIRValue(Token, PFS, V, ErrorCallback);
unsigned const MachineRegisterInfo * MRI
This file defines the StringMap class.
This file implements a class to represent arbitrary precision integral constant values and operations...
This file implements the APSInt class, which is a simple class that represents an arbitrary sized int...
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Atomic ordering constants.
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Analysis containing CSE Info
This file contains the declarations for the subclasses of Constant, which represent the different fla...
static Error parseAlignment(StringRef Str, Align &Alignment, StringRef Name, bool AllowZero=false)
Attempts to parse an alignment component of a specification.
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines the DenseMap class.
const HexagonInstrInfo * TII
Module.h This file contains the declarations for the Module class.
A common definition of LaneBitmask for use in TableGen and CodeGen.
Implement a low-level type suitable for MachineInstr level instruction selection.
static const char * printImplicitRegisterFlag(const MachineOperand &MO)
static const BasicBlock * getIRBlockFromSlot(unsigned Slot, const DenseMap< unsigned, const BasicBlock * > &Slots2BasicBlocks)
static std::string getRegisterName(const TargetRegisterInfo *TRI, Register Reg)
static bool parseIRConstant(StringRef::iterator Loc, StringRef StringValue, PerFunctionMIParsingState &PFS, const Constant *&C, ErrorCallbackType ErrCB)
static void initSlots2Values(const Function &F, DenseMap< unsigned, const Value * > &Slots2Values)
Creates the mapping from slot numbers to function's unnamed IR values.
static bool parseIRValue(const MIToken &Token, PerFunctionMIParsingState &PFS, const Value *&V, ErrorCallbackType ErrCB)
static bool verifyScalarSize(uint64_t Size)
static bool getUnsigned(const MIToken &Token, unsigned &Result, ErrorCallbackType ErrCB)
static bool getHexUint(const MIToken &Token, APInt &Result)
static bool verifyVectorElementCount(uint64_t NumElts)
static void mapValueToSlot(const Value *V, ModuleSlotTracker &MST, DenseMap< unsigned, const Value * > &Slots2Values)
static void initSlots2BasicBlocks(const Function &F, DenseMap< unsigned, const BasicBlock * > &Slots2BasicBlocks)
function_ref< bool(StringRef::iterator Loc, const Twine &)> ErrorCallbackType
static bool isImplicitOperandIn(const MachineOperand &ImplicitOperand, ArrayRef< ParsedMachineOperand > Operands)
Return true if the parsed machine operands contain a given machine operand.
static bool parseGlobalValue(const MIToken &Token, PerFunctionMIParsingState &PFS, GlobalValue *&GV, ErrorCallbackType ErrCB)
static bool verifyAddrSpace(uint64_t AddrSpace)
mir Rename Register Operands
unsigned const TargetRegisterInfo * TRI
ConstantRange Range(APInt(BitWidth, Low), APInt(BitWidth, High))
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool parseMetadata(const StringRef &Input, uint64_t &FunctionHash, uint32_t &Attributes)
Parse Input that contains metadata.
This file defines the SmallVector class.
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
Class for arbitrary precision integers.
uint64_t getZExtValue() const
Get zero extended value.
uint64_t getLimitedValue(uint64_t Limit=UINT64_MAX) const
If this value is smaller than the specified limit, return it, otherwise return the limit value.
An arbitrary precision integer that knows its signedness.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
LLVM Basic Block Representation.
static BlockAddress * get(Function *F, BasicBlock *BB)
Return a BlockAddress for the specified function and basic block.
static BranchProbability getRaw(uint32_t N)
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
@ FCMP_OEQ
0 0 0 1 True if ordered and equal
@ FCMP_TRUE
1 1 1 1 Always true (always folded)
@ ICMP_SLT
signed less than
@ ICMP_SLE
signed less or equal
@ FCMP_OLT
0 1 0 0 True if ordered and less than
@ FCMP_ULE
1 1 0 1 True if unordered, less than, or equal
@ FCMP_OGT
0 0 1 0 True if ordered and greater than
@ FCMP_OGE
0 0 1 1 True if ordered and greater than or equal
@ ICMP_UGE
unsigned greater or equal
@ ICMP_UGT
unsigned greater than
@ ICMP_SGT
signed greater than
@ FCMP_ULT
1 1 0 0 True if unordered or less than
@ FCMP_ONE
0 1 1 0 True if ordered and operands are unequal
@ FCMP_UEQ
1 0 0 1 True if unordered or equal
@ ICMP_ULT
unsigned less than
@ FCMP_UGT
1 0 1 0 True if unordered or greater than
@ FCMP_OLE
0 1 0 1 True if ordered and less than or equal
@ FCMP_ORD
0 1 1 1 True if ordered (no nans)
@ ICMP_SGE
signed greater or equal
@ FCMP_UNE
1 1 1 0 True if unordered or not equal
@ ICMP_ULE
unsigned less or equal
@ FCMP_UGE
1 0 1 1 True if unordered, greater than, or equal
@ FCMP_FALSE
0 0 0 0 Always false (always folded)
@ FCMP_UNO
1 0 0 0 True if unordered: isnan(X) | isnan(Y)
bool isFPPredicate() const
bool isIntPredicate() const
This is an important base class in LLVM.
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
ValueT lookup(const_arg_type_t< KeyT > Val) const
lookup - Return the entry for the specified key, or a default constructed value if no such entry exis...
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
static constexpr ElementCount get(ScalarTy MinVal, bool Scalable)
Lightweight error class with error context and mandatory checking.
ValueSymbolTable * getValueSymbolTable()
getSymbolTable() - Return the symbol table if any, otherwise nullptr.
Module * getParent()
Get the module that this global value is contained inside of...
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Return an array that contains the direct target flag values and their names.
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Return an array that contains the bitmask target flag values and their names.
static constexpr LLT vector(ElementCount EC, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
static constexpr LLT token()
Get a low-level token; just a scalar with zero bits (or no size).
This is an important class for using LLVM in a threaded context.
SyncScope::ID getOrInsertSyncScopeID(StringRef SSN)
getOrInsertSyncScopeID - Maps synchronization scope name to synchronization scope ID.
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_def_cfa_register modifies a rule for computing CFA.
static MCCFIInstruction createUndefined(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_undefined From now on the previous value of Register can't be restored anymore.
static MCCFIInstruction createRestore(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_restore says that the rule for Register is now the same as it was at the beginning of the functi...
static MCCFIInstruction createLLVMDefAspaceCfa(MCSymbol *L, unsigned Register, int64_t Offset, unsigned AddressSpace, SMLoc Loc)
.cfi_llvm_def_aspace_cfa defines the rule for computing the CFA to be the result of evaluating the DW...
static MCCFIInstruction createRegister(MCSymbol *L, unsigned Register1, unsigned Register2, SMLoc Loc={})
.cfi_register Previous value of Register1 is saved in register Register2.
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
static MCCFIInstruction createNegateRAStateWithPC(MCSymbol *L, SMLoc Loc={})
.cfi_negate_ra_state_with_pc AArch64 negate RA state with PC.
static MCCFIInstruction createNegateRAState(MCSymbol *L, SMLoc Loc={})
.cfi_negate_ra_state AArch64 negate RA state.
static MCCFIInstruction createRememberState(MCSymbol *L, SMLoc Loc={})
.cfi_remember_state Save all current rules for all registers.
static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int64_t Offset, SMLoc Loc={})
.cfi_def_cfa_offset modifies a rule for computing CFA.
static MCCFIInstruction createEscape(MCSymbol *L, StringRef Vals, SMLoc Loc={}, StringRef Comment="")
.cfi_escape Allows the user to add arbitrary bytes to the unwind info.
static MCCFIInstruction createWindowSave(MCSymbol *L, SMLoc Loc={})
.cfi_window_save SPARC register window is saved.
static MCCFIInstruction createAdjustCfaOffset(MCSymbol *L, int64_t Adjustment, SMLoc Loc={})
.cfi_adjust_cfa_offset Same as .cfi_def_cfa_offset, but Offset is a relative value that is added/subt...
static MCCFIInstruction createRestoreState(MCSymbol *L, SMLoc Loc={})
.cfi_restore_state Restore the previously saved state.
static MCCFIInstruction createSameValue(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_same_value Current value of Register is the same as in the previous frame.
static MCCFIInstruction createRelOffset(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})
.cfi_rel_offset Previous value of Register is saved at offset Offset from the current CFA register.
Describe properties that are true of each instruction in the target description file.
ArrayRef< MCPhysReg > implicit_defs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
bool isCall() const
Return true if the instruction is a call.
ArrayRef< MCPhysReg > implicit_uses() const
Return a list of registers that are potentially read by any instance of this machine instruction.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
void replaceAllUsesWith(Metadata *MD)
RAUW a temporary.
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
static MDString * get(LLVMContext &Context, StringRef Str)
static MDTuple * getDistinct(LLVMContext &Context, ArrayRef< Metadata * > MDs)
Return a distinct node.
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
static TempMDTuple getTemporary(LLVMContext &Context, ArrayRef< Metadata * > MDs)
Return a temporary node.
void normalizeSuccProbs()
Normalize probabilities of all successors so that the sum of them becomes one.
void setAddressTakenIRBlock(BasicBlock *BB)
Set this block to reflect that it corresponds to an IR-level basic block with a BlockAddress.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
void setCallFrameSize(unsigned N)
Set the call frame size on entry to this basic block.
void setAlignment(Align A)
Set alignment of the basic block.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
void setSectionID(MBBSectionID V)
Sets the section ID for this basic block.
void setIsInlineAsmBrIndirectTarget(bool V=true)
Indicates if this is the indirect dest of an INLINEASM_BR.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
void setIsEHFuncletEntry(bool V=true)
Indicates if this is the entry block of an EH funclet.
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
void setMachineBlockAddressTaken()
Set this block to indicate that its address is used as something other than the target of a terminato...
void setIsEHPad(bool V=true)
Indicates the block is a landing pad.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
void setFlag(MIFlag Flag)
Set a MI flag.
A description of a memory reference used in the backend.
Flags
Flags values. These may be or'd together.
@ MOVolatile
The memory access is volatile.
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
@ MOLoad
The memory access reads data.
@ MONonTemporal
The memory access is non-temporal.
@ MOInvariant
The memory access always returns the same value (or traps).
@ MOStore
The memory access writes data.
MachineOperand class - Representation of each machine instruction operand.
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
static MachineOperand CreateES(const char *SymName, unsigned TargetFlags=0)
static MachineOperand CreateFPImm(const ConstantFP *CFP)
static MachineOperand CreateCFIIndex(unsigned CFIIndex)
static MachineOperand CreateRegMask(const uint32_t *Mask)
CreateRegMask - Creates a register mask operand referencing Mask.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
static MachineOperand CreateCImm(const ConstantInt *CI)
static MachineOperand CreateMetadata(const MDNode *Meta)
static MachineOperand CreatePredicate(unsigned Pred)
static MachineOperand CreateImm(int64_t Val)
static MachineOperand CreateShuffleMask(ArrayRef< int > Mask)
static MachineOperand CreateJTI(unsigned Idx, unsigned TargetFlags=0)
static MachineOperand CreateDbgInstrRef(unsigned InstrIdx, unsigned OpIdx)
static MachineOperand CreateRegLiveOut(const uint32_t *Mask)
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset, unsigned TargetFlags=0)
void setTargetFlags(unsigned F)
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
static MachineOperand CreateCPI(unsigned Idx, int Offset, unsigned TargetFlags=0)
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
static MachineOperand CreateMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0)
static MachineOperand CreateIntrinsicID(Intrinsic::ID ID)
static MachineOperand CreateFI(int Idx)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register createIncompleteVirtualRegister(StringRef Name="")
Creates a new virtual register that has no register class, register bank or size assigned yet.
This interface provides simple read-only access to a block of memory, and provides simple methods for...
virtual StringRef getBufferIdentifier() const
Return an identifier for this buffer, typically the filename it was read from.
const char * getBufferEnd() const
const char * getBufferStart() const
Manage lifetime of a slot tracker for printing IR.
int getLocalSlot(const Value *V)
Return the slot number of the specified local value.
void incorporateFunction(const Function &F)
Incorporate the given function.
A Module instance is used to store all the information related to an LLVM module.
Special value supplied for machine level alias analysis.
Holds all the information related to register banks.
const RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
unsigned getNumRegBanks() const
Get the total number of register banks.
This class implements the register bank concept.
Wrapper class representing virtual and physical registers.
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Represents a location in source code.
static SMLoc getFromPointer(const char *Ptr)
Represents a range in source code.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
This owns the files read by a parser, handles include stacks, and handles diagnostic wrangling.
unsigned getMainFileID() const
const MemoryBuffer * getMemoryBuffer(unsigned i) const
SMDiagnostic GetMessage(SMLoc Loc, DiagKind Kind, const Twine &Msg, ArrayRef< SMRange > Ranges={}, ArrayRef< SMFixIt > FixIts={}) const
Return an SMDiagnostic at the specified location with the specified string.
iterator find(StringRef Key)
bool insert(MapEntryTy *KeyValue)
insert - Insert the specified key/value pair into the map.
StringRef - Represent a constant reference to a string, i.e.
std::string str() const
str - Get the contents as an std::string.
constexpr StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
StringRef drop_front(size_t N=1) const
Return a StringRef equal to 'this' but with the first N elements dropped.
constexpr size_t size() const
size - Get the string size.
char front() const
front - Get the first character in the string.
std::string lower() const
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
Target - Wrapper for Target specific information.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
std::string str() const
Return the twine contents as a std::string.
Value * lookup(StringRef Name) const
This method finds the value with the given Name in the the symbol table.
LLVM Value Representation.
An efficient, type-erasing, non-owning reference to a callable.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ C
The default llvm calling convention, compatible with C.
ID lookupIntrinsicID(StringRef Name)
This does the actual lookup of an intrinsic ID which matches the given function name.
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Debug
Register 'use' is for debugging purpose.
@ Renamable
Register that may be renamed.
@ Define
Register definition.
@ InternalRead
Register reads a value that is defined inside the same instruction or bundle.
@ Kill
The last use of a register.
@ Undef
Value of the register doesn't matter.
@ EarlyClobber
Register definition happens before uses.
@ System
Synchronized with respect to all concurrently executing threads.
Reg
All possible values of the reg field in the ModR/M byte.
support::ulittle32_t Word
Scope
Defines the scope in which this symbol should be visible: Default – Visible in the public interface o...
This is an optimization pass for GlobalISel generic memory operations.
bool parseStackObjectReference(PerFunctionMIParsingState &PFS, int &FI, StringRef Src, SMDiagnostic &Error)
bool parseMDNode(PerFunctionMIParsingState &PFS, MDNode *&Node, StringRef Src, SMDiagnostic &Error)
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
StringRef lexMIToken(StringRef Source, MIToken &Token, function_ref< void(StringRef::iterator, const Twine &)> ErrorCallback)
Consume a single machine instruction token in the given source and return the remaining source string...
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
bool parseMachineBasicBlockDefinitions(PerFunctionMIParsingState &PFS, StringRef Src, SMDiagnostic &Error)
Parse the machine basic block definitions, and skip the machine instructions.
void guessSuccessors(const MachineBasicBlock &MBB, SmallVectorImpl< MachineBasicBlock * > &Result, bool &IsFallthrough)
Determine a possible list of successors of a basic block based on the basic block machine operand bei...
bool parseMBBReference(PerFunctionMIParsingState &PFS, MachineBasicBlock *&MBB, StringRef Src, SMDiagnostic &Error)
uint64_t PowerOf2Ceil(uint64_t A)
Returns the power of two which is greater than or equal to the given value.
DIExpression * parseDIExpressionBodyAtBeginning(StringRef Asm, unsigned &Read, SMDiagnostic &Err, const Module &M, const SlotMapping *Slots)
AtomicOrdering
Atomic ordering for LLVM's memory model.
bool parseMachineInstructions(PerFunctionMIParsingState &PFS, StringRef Src, SMDiagnostic &Error)
Parse the machine instructions.
bool parseRegisterReference(PerFunctionMIParsingState &PFS, Register &Reg, StringRef Src, SMDiagnostic &Error)
Constant * parseConstantValue(StringRef Asm, SMDiagnostic &Err, const Module &M, const SlotMapping *Slots=nullptr)
Parse a type and a constant value in the given string.
const char * toString(DWARFSectionKind Kind)
bool parseMachineMetadata(PerFunctionMIParsingState &PFS, StringRef Src, SMRange SourceRange, SMDiagnostic &Error)
bool parseVirtualRegisterReference(PerFunctionMIParsingState &PFS, VRegInfo *&Info, StringRef Src, SMDiagnostic &Error)
bool parseNamedRegisterReference(PerFunctionMIParsingState &PFS, Register &Reg, StringRef Src, SMDiagnostic &Error)
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
MDNode * Scope
The tag for alias scope specification (used with noalias).
MDNode * TBAA
The tag for type-based alias analysis.
MDNode * NoAlias
The tag specifying the noalias scope.
This struct is a compact representation of a valid (non-zero power of two) alignment.
static constexpr LaneBitmask getAll()
static const MBBSectionID ExceptionSectionID
static const MBBSectionID ColdSectionID
A token produced by the machine instruction lexer.
bool hasIntegerValue() const
bool is(TokenKind K) const
StringRef stringValue() const
Return the token's string value.
@ kw_cfi_aarch64_negate_ra_sign_state
@ kw_cfi_llvm_def_aspace_cfa
@ kw_inlineasm_br_indirect_target
@ kw_cfi_aarch64_negate_ra_sign_state_with_pc
@ kw_cfi_def_cfa_register
@ kw_cfi_adjust_cfa_offset
@ kw_machine_block_address_taken
@ kw_ir_block_address_taken
StringRef::iterator location() const
const APSInt & integerValue() const
This class contains a discriminated union of information about pointers in memory operands,...
VRegInfo & getVRegInfo(Register Num)
const SlotMapping & IRSlots
const Value * getIRValue(unsigned Slot)
DenseMap< unsigned, MachineBasicBlock * > MBBSlots
StringMap< VRegInfo * > VRegInfosNamed
DenseMap< unsigned, const Value * > Slots2Values
Maps from slot numbers to function's unnamed values.
PerFunctionMIParsingState(MachineFunction &MF, SourceMgr &SM, const SlotMapping &IRSlots, PerTargetMIParsingState &Target)
DenseMap< Register, VRegInfo * > VRegInfos
VRegInfo & getVRegInfoNamed(StringRef RegName)
BumpPtrAllocator Allocator
bool getVRegFlagValue(StringRef FlagName, uint8_t &FlagValue) const
bool getDirectTargetFlag(StringRef Name, unsigned &Flag)
Try to convert a name of a direct target flag to the corresponding target flag.
const RegisterBank * getRegBank(StringRef Name)
Check if the given identifier is a name of a register bank.
bool parseInstrName(StringRef InstrName, unsigned &OpCode)
Try to convert an instruction name to an opcode.
unsigned getSubRegIndex(StringRef Name)
Check if the given identifier is a name of a subregister index.
bool getTargetIndex(StringRef Name, int &Index)
Try to convert a name of target index to the corresponding target index.
void setTarget(const TargetSubtargetInfo &NewSubtarget)
bool getRegisterByName(StringRef RegName, Register &Reg)
Try to convert a register name to a register number.
bool getMMOTargetFlag(StringRef Name, MachineMemOperand::Flags &Flag)
Try to convert a name of a MachineMemOperand target flag to the corresponding target flag.
bool getBitmaskTargetFlag(StringRef Name, unsigned &Flag)
Try to convert a name of a bitmask target flag to the corresponding target flag.
const TargetRegisterClass * getRegClass(StringRef Name)
Check if the given identifier is a name of a register class.
const uint32_t * getRegMask(StringRef Identifier)
Check if the given identifier is a name of a register mask.
This struct contains the mappings from the slot numbers to unnamed metadata nodes,...
NumberedValues< GlobalValue * > GlobalValues