80#define DEBUG_TYPE "mips-lower"
86 cl::desc(
"MIPS: Don't trap on integer division by zero."),
92 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
93 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
124 unsigned &NumIntermediates,
MVT &RegisterVT)
const {
129 return NumIntermediates;
145 unsigned Flag)
const {
151 unsigned Flag)
const {
157 unsigned Flag)
const {
163 unsigned Flag)
const {
169 unsigned Flag)
const {
171 N->getOffset(), Flag);
564 if (!TM.isPositionIndependent() || !TM.getABI().IsO32() ||
584 EVT Ty =
N->getValueType(0);
585 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64;
586 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64;
592 N->getOperand(0),
N->getOperand(1));
597 if (
N->hasAnyUseOfValue(0)) {
606 if (
N->hasAnyUseOfValue(1)) {
648 "Illegal Condition Code");
662 if (!
LHS.getValueType().isFloatingPoint())
774 SDValue ValueIfTrue =
N->getOperand(0), ValueIfFalse =
N->getOperand(2);
790 SDValue FCC =
N->getOperand(1), Glue =
N->getOperand(3);
791 return DAG.
getNode(Opc,
SDLoc(
N), ValueIfFalse.getValueType(),
792 ValueIfFalse, FCC, ValueIfTrue, Glue);
801 SDValue FirstOperand =
N->getOperand(0);
802 unsigned FirstOperandOpc = FirstOperand.
getOpcode();
804 EVT ValTy =
N->getValueType(0);
808 unsigned SMPos, SMSize;
814 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
824 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.
getOperand(1))))
844 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.
getOperand(1))))
849 if (SMPos != Pos || Pos >= ValTy.
getSizeInBits() || SMSize >= 32 ||
871 NewOperand = FirstOperand;
873 return DAG.
getNode(Opc,
DL, ValTy, NewOperand,
884 SDValue FirstOperand =
N->getOperand(0), SecondOperand =
N->getOperand(1);
885 unsigned SMPos0, SMSize0, SMPos1, SMSize1;
889 SecondOperand.getOpcode() ==
ISD::SHL) ||
891 SecondOperand.getOpcode() ==
ISD::AND)) {
902 ? SecondOperand.getOperand(0)
907 if (!(CN = dyn_cast<ConstantSDNode>(AndMask)) ||
912 ? SecondOperand.getOperand(1)
914 if (!(CN = dyn_cast<ConstantSDNode>(ShlShift)))
918 if (SMPos0 != 0 || SMSize0 != ShlShiftValue)
922 EVT ValTy =
N->getValueType(0);
923 SMPos1 = ShlShiftValue;
925 SMSize1 = (ValTy == MVT::i64 ? 64 : 32) - SMPos1;
939 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.
getOperand(1))) ||
944 if (SecondOperand.getOpcode() ==
ISD::AND &&
945 SecondOperand.getOperand(0).getOpcode() ==
ISD::SHL) {
947 if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand.getOperand(1))) ||
952 if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
957 if (!(CN = dyn_cast<ConstantSDNode>(Shl.
getOperand(1))))
964 EVT ValTy =
N->getValueType(0);
965 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.
getSizeInBits()))
978 if (~CN->
getSExtValue() == ((((int64_t)1 << SMSize0) - 1) << SMPos0) &&
979 ((SMSize0 + SMPos0 <= 64 && Subtarget.
hasMips64r2()) ||
980 (SMSize0 + SMPos0 <= 32))) {
983 if (SecondOperand.getOpcode() ==
ISD::AND) {
984 if (!(CN1 = dyn_cast<ConstantSDNode>(SecondOperand->getOperand(1))))
987 if (!(CN1 = dyn_cast<ConstantSDNode>(
N->getOperand(1))))
996 EVT ValTy =
N->getOperand(0)->getValueType(0);
1002 SecondOperand, Const1);
1071 if (!Mult.hasOneUse())
1079 SDValue MultLHS = Mult->getOperand(0);
1080 SDValue MultRHS = Mult->getOperand(1);
1087 if (!IsSigned && !IsUnsigned)
1093 std::tie(BottomHalf, TopHalf) =
1120 !Subtarget.
inMips16Mode() &&
N->getValueType(0) == MVT::i64)
1135 !Subtarget.
inMips16Mode() &&
N->getValueType(0) == MVT::i64)
1145 SDValue InnerAdd =
N->getOperand(1);
1161 EVT ValTy =
N->getValueType(0);
1178 SDValue FirstOperand =
N->getOperand(0);
1179 unsigned FirstOperandOpc = FirstOperand.
getOpcode();
1180 SDValue SecondOperand =
N->getOperand(1);
1181 EVT ValTy =
N->getValueType(0);
1185 unsigned SMPos, SMSize;
1190 if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand)))
1202 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.
getOperand(1))) ||
1208 if (SMPos != 0 || SMSize > 32 || Pos + SMSize > ValTy.
getSizeInBits())
1223 unsigned Opc =
N->getOpcode();
1262 if (
auto *
C = dyn_cast<ConstantSDNode>(
Y))
1263 return C->getAPIntValue().ule(15);
1271 N->getOperand(0).getOpcode() ==
ISD::SRL) ||
1273 N->getOperand(0).getOpcode() ==
ISD::SHL)) &&
1274 "Expected shift-shift mask");
1276 if (
N->getOperand(0).getValueType().isVector())
1291 switch (
Op.getOpcode())
1306 return lowerFCANONICALIZE(
Op, DAG);
1340 bool Is64Bit,
bool IsMicroMips) {
1349 TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ))
1370 switch (
MI.getOpcode()) {
1373 case Mips::ATOMIC_LOAD_ADD_I8:
1374 return emitAtomicBinaryPartword(
MI, BB, 1);
1375 case Mips::ATOMIC_LOAD_ADD_I16:
1376 return emitAtomicBinaryPartword(
MI, BB, 2);
1377 case Mips::ATOMIC_LOAD_ADD_I32:
1378 return emitAtomicBinary(
MI, BB);
1379 case Mips::ATOMIC_LOAD_ADD_I64:
1380 return emitAtomicBinary(
MI, BB);
1382 case Mips::ATOMIC_LOAD_AND_I8:
1383 return emitAtomicBinaryPartword(
MI, BB, 1);
1384 case Mips::ATOMIC_LOAD_AND_I16:
1385 return emitAtomicBinaryPartword(
MI, BB, 2);
1386 case Mips::ATOMIC_LOAD_AND_I32:
1387 return emitAtomicBinary(
MI, BB);
1388 case Mips::ATOMIC_LOAD_AND_I64:
1389 return emitAtomicBinary(
MI, BB);
1391 case Mips::ATOMIC_LOAD_OR_I8:
1392 return emitAtomicBinaryPartword(
MI, BB, 1);
1393 case Mips::ATOMIC_LOAD_OR_I16:
1394 return emitAtomicBinaryPartword(
MI, BB, 2);
1395 case Mips::ATOMIC_LOAD_OR_I32:
1396 return emitAtomicBinary(
MI, BB);
1397 case Mips::ATOMIC_LOAD_OR_I64:
1398 return emitAtomicBinary(
MI, BB);
1400 case Mips::ATOMIC_LOAD_XOR_I8:
1401 return emitAtomicBinaryPartword(
MI, BB, 1);
1402 case Mips::ATOMIC_LOAD_XOR_I16:
1403 return emitAtomicBinaryPartword(
MI, BB, 2);
1404 case Mips::ATOMIC_LOAD_XOR_I32:
1405 return emitAtomicBinary(
MI, BB);
1406 case Mips::ATOMIC_LOAD_XOR_I64:
1407 return emitAtomicBinary(
MI, BB);
1409 case Mips::ATOMIC_LOAD_NAND_I8:
1410 return emitAtomicBinaryPartword(
MI, BB, 1);
1411 case Mips::ATOMIC_LOAD_NAND_I16:
1412 return emitAtomicBinaryPartword(
MI, BB, 2);
1413 case Mips::ATOMIC_LOAD_NAND_I32:
1414 return emitAtomicBinary(
MI, BB);
1415 case Mips::ATOMIC_LOAD_NAND_I64:
1416 return emitAtomicBinary(
MI, BB);
1418 case Mips::ATOMIC_LOAD_SUB_I8:
1419 return emitAtomicBinaryPartword(
MI, BB, 1);
1420 case Mips::ATOMIC_LOAD_SUB_I16:
1421 return emitAtomicBinaryPartword(
MI, BB, 2);
1422 case Mips::ATOMIC_LOAD_SUB_I32:
1423 return emitAtomicBinary(
MI, BB);
1424 case Mips::ATOMIC_LOAD_SUB_I64:
1425 return emitAtomicBinary(
MI, BB);
1427 case Mips::ATOMIC_SWAP_I8:
1428 return emitAtomicBinaryPartword(
MI, BB, 1);
1429 case Mips::ATOMIC_SWAP_I16:
1430 return emitAtomicBinaryPartword(
MI, BB, 2);
1431 case Mips::ATOMIC_SWAP_I32:
1432 return emitAtomicBinary(
MI, BB);
1433 case Mips::ATOMIC_SWAP_I64:
1434 return emitAtomicBinary(
MI, BB);
1436 case Mips::ATOMIC_CMP_SWAP_I8:
1437 return emitAtomicCmpSwapPartword(
MI, BB, 1);
1438 case Mips::ATOMIC_CMP_SWAP_I16:
1439 return emitAtomicCmpSwapPartword(
MI, BB, 2);
1440 case Mips::ATOMIC_CMP_SWAP_I32:
1441 return emitAtomicCmpSwap(
MI, BB);
1442 case Mips::ATOMIC_CMP_SWAP_I64:
1443 return emitAtomicCmpSwap(
MI, BB);
1445 case Mips::ATOMIC_LOAD_MIN_I8:
1446 return emitAtomicBinaryPartword(
MI, BB, 1);
1447 case Mips::ATOMIC_LOAD_MIN_I16:
1448 return emitAtomicBinaryPartword(
MI, BB, 2);
1449 case Mips::ATOMIC_LOAD_MIN_I32:
1450 return emitAtomicBinary(
MI, BB);
1451 case Mips::ATOMIC_LOAD_MIN_I64:
1452 return emitAtomicBinary(
MI, BB);
1454 case Mips::ATOMIC_LOAD_MAX_I8:
1455 return emitAtomicBinaryPartword(
MI, BB, 1);
1456 case Mips::ATOMIC_LOAD_MAX_I16:
1457 return emitAtomicBinaryPartword(
MI, BB, 2);
1458 case Mips::ATOMIC_LOAD_MAX_I32:
1459 return emitAtomicBinary(
MI, BB);
1460 case Mips::ATOMIC_LOAD_MAX_I64:
1461 return emitAtomicBinary(
MI, BB);
1463 case Mips::ATOMIC_LOAD_UMIN_I8:
1464 return emitAtomicBinaryPartword(
MI, BB, 1);
1465 case Mips::ATOMIC_LOAD_UMIN_I16:
1466 return emitAtomicBinaryPartword(
MI, BB, 2);
1467 case Mips::ATOMIC_LOAD_UMIN_I32:
1468 return emitAtomicBinary(
MI, BB);
1469 case Mips::ATOMIC_LOAD_UMIN_I64:
1470 return emitAtomicBinary(
MI, BB);
1472 case Mips::ATOMIC_LOAD_UMAX_I8:
1473 return emitAtomicBinaryPartword(
MI, BB, 1);
1474 case Mips::ATOMIC_LOAD_UMAX_I16:
1475 return emitAtomicBinaryPartword(
MI, BB, 2);
1476 case Mips::ATOMIC_LOAD_UMAX_I32:
1477 return emitAtomicBinary(
MI, BB);
1478 case Mips::ATOMIC_LOAD_UMAX_I64:
1479 return emitAtomicBinary(
MI, BB);
1481 case Mips::PseudoSDIV:
1482 case Mips::PseudoUDIV:
1489 case Mips::SDIV_MM_Pseudo:
1490 case Mips::UDIV_MM_Pseudo:
1493 case Mips::DIV_MMR6:
1494 case Mips::DIVU_MMR6:
1495 case Mips::MOD_MMR6:
1496 case Mips::MODU_MMR6:
1498 case Mips::PseudoDSDIV:
1499 case Mips::PseudoDUDIV:
1506 case Mips::PseudoSELECT_I:
1507 case Mips::PseudoSELECT_I64:
1508 case Mips::PseudoSELECT_S:
1509 case Mips::PseudoSELECT_D32:
1510 case Mips::PseudoSELECT_D64:
1511 return emitPseudoSELECT(
MI, BB,
false, Mips::BNE);
1512 case Mips::PseudoSELECTFP_F_I:
1513 case Mips::PseudoSELECTFP_F_I64:
1514 case Mips::PseudoSELECTFP_F_S:
1515 case Mips::PseudoSELECTFP_F_D32:
1516 case Mips::PseudoSELECTFP_F_D64:
1517 return emitPseudoSELECT(
MI, BB,
true, Mips::BC1F);
1518 case Mips::PseudoSELECTFP_T_I:
1519 case Mips::PseudoSELECTFP_T_I64:
1520 case Mips::PseudoSELECTFP_T_S:
1521 case Mips::PseudoSELECTFP_T_D32:
1522 case Mips::PseudoSELECTFP_T_D64:
1523 return emitPseudoSELECT(
MI, BB,
true, Mips::BC1T);
1524 case Mips::PseudoD_SELECT_I:
1525 case Mips::PseudoD_SELECT_I64:
1526 return emitPseudoD_SELECT(
MI, BB);
1528 return emitLDR_W(
MI, BB);
1530 return emitLDR_D(
MI, BB);
1532 return emitSTR_W(
MI, BB);
1534 return emitSTR_D(
MI, BB);
1550 bool NeedsAdditionalReg =
false;
1551 switch (
MI.getOpcode()) {
1552 case Mips::ATOMIC_LOAD_ADD_I32:
1553 AtomicOp = Mips::ATOMIC_LOAD_ADD_I32_POSTRA;
1555 case Mips::ATOMIC_LOAD_SUB_I32:
1556 AtomicOp = Mips::ATOMIC_LOAD_SUB_I32_POSTRA;
1558 case Mips::ATOMIC_LOAD_AND_I32:
1559 AtomicOp = Mips::ATOMIC_LOAD_AND_I32_POSTRA;
1561 case Mips::ATOMIC_LOAD_OR_I32:
1562 AtomicOp = Mips::ATOMIC_LOAD_OR_I32_POSTRA;
1564 case Mips::ATOMIC_LOAD_XOR_I32:
1565 AtomicOp = Mips::ATOMIC_LOAD_XOR_I32_POSTRA;
1567 case Mips::ATOMIC_LOAD_NAND_I32:
1568 AtomicOp = Mips::ATOMIC_LOAD_NAND_I32_POSTRA;
1570 case Mips::ATOMIC_SWAP_I32:
1571 AtomicOp = Mips::ATOMIC_SWAP_I32_POSTRA;
1573 case Mips::ATOMIC_LOAD_ADD_I64:
1574 AtomicOp = Mips::ATOMIC_LOAD_ADD_I64_POSTRA;
1576 case Mips::ATOMIC_LOAD_SUB_I64:
1577 AtomicOp = Mips::ATOMIC_LOAD_SUB_I64_POSTRA;
1579 case Mips::ATOMIC_LOAD_AND_I64:
1580 AtomicOp = Mips::ATOMIC_LOAD_AND_I64_POSTRA;
1582 case Mips::ATOMIC_LOAD_OR_I64:
1583 AtomicOp = Mips::ATOMIC_LOAD_OR_I64_POSTRA;
1585 case Mips::ATOMIC_LOAD_XOR_I64:
1586 AtomicOp = Mips::ATOMIC_LOAD_XOR_I64_POSTRA;
1588 case Mips::ATOMIC_LOAD_NAND_I64:
1589 AtomicOp = Mips::ATOMIC_LOAD_NAND_I64_POSTRA;
1591 case Mips::ATOMIC_SWAP_I64:
1592 AtomicOp = Mips::ATOMIC_SWAP_I64_POSTRA;
1594 case Mips::ATOMIC_LOAD_MIN_I32:
1595 AtomicOp = Mips::ATOMIC_LOAD_MIN_I32_POSTRA;
1596 NeedsAdditionalReg =
true;
1598 case Mips::ATOMIC_LOAD_MAX_I32:
1599 AtomicOp = Mips::ATOMIC_LOAD_MAX_I32_POSTRA;
1600 NeedsAdditionalReg =
true;
1602 case Mips::ATOMIC_LOAD_UMIN_I32:
1603 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I32_POSTRA;
1604 NeedsAdditionalReg =
true;
1606 case Mips::ATOMIC_LOAD_UMAX_I32:
1607 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I32_POSTRA;
1608 NeedsAdditionalReg =
true;
1610 case Mips::ATOMIC_LOAD_MIN_I64:
1611 AtomicOp = Mips::ATOMIC_LOAD_MIN_I64_POSTRA;
1612 NeedsAdditionalReg =
true;
1614 case Mips::ATOMIC_LOAD_MAX_I64:
1615 AtomicOp = Mips::ATOMIC_LOAD_MAX_I64_POSTRA;
1616 NeedsAdditionalReg =
true;
1618 case Mips::ATOMIC_LOAD_UMIN_I64:
1619 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I64_POSTRA;
1620 NeedsAdditionalReg =
true;
1622 case Mips::ATOMIC_LOAD_UMAX_I64:
1623 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I64_POSTRA;
1624 NeedsAdditionalReg =
true;
1685 if (NeedsAdditionalReg) {
1692 MI.eraseFromParent();
1699 unsigned SrcReg)
const {
1719 int64_t ShiftImm = 32 - (
Size * 8);
1730 "Unsupported size for EmitAtomicBinaryPartial.");
1757 unsigned AtomicOp = 0;
1758 bool NeedsAdditionalReg =
false;
1759 switch (
MI.getOpcode()) {
1760 case Mips::ATOMIC_LOAD_NAND_I8:
1761 AtomicOp = Mips::ATOMIC_LOAD_NAND_I8_POSTRA;
1763 case Mips::ATOMIC_LOAD_NAND_I16:
1764 AtomicOp = Mips::ATOMIC_LOAD_NAND_I16_POSTRA;
1766 case Mips::ATOMIC_SWAP_I8:
1767 AtomicOp = Mips::ATOMIC_SWAP_I8_POSTRA;
1769 case Mips::ATOMIC_SWAP_I16:
1770 AtomicOp = Mips::ATOMIC_SWAP_I16_POSTRA;
1772 case Mips::ATOMIC_LOAD_ADD_I8:
1773 AtomicOp = Mips::ATOMIC_LOAD_ADD_I8_POSTRA;
1775 case Mips::ATOMIC_LOAD_ADD_I16:
1776 AtomicOp = Mips::ATOMIC_LOAD_ADD_I16_POSTRA;
1778 case Mips::ATOMIC_LOAD_SUB_I8:
1779 AtomicOp = Mips::ATOMIC_LOAD_SUB_I8_POSTRA;
1781 case Mips::ATOMIC_LOAD_SUB_I16:
1782 AtomicOp = Mips::ATOMIC_LOAD_SUB_I16_POSTRA;
1784 case Mips::ATOMIC_LOAD_AND_I8:
1785 AtomicOp = Mips::ATOMIC_LOAD_AND_I8_POSTRA;
1787 case Mips::ATOMIC_LOAD_AND_I16:
1788 AtomicOp = Mips::ATOMIC_LOAD_AND_I16_POSTRA;
1790 case Mips::ATOMIC_LOAD_OR_I8:
1791 AtomicOp = Mips::ATOMIC_LOAD_OR_I8_POSTRA;
1793 case Mips::ATOMIC_LOAD_OR_I16:
1794 AtomicOp = Mips::ATOMIC_LOAD_OR_I16_POSTRA;
1796 case Mips::ATOMIC_LOAD_XOR_I8:
1797 AtomicOp = Mips::ATOMIC_LOAD_XOR_I8_POSTRA;
1799 case Mips::ATOMIC_LOAD_XOR_I16:
1800 AtomicOp = Mips::ATOMIC_LOAD_XOR_I16_POSTRA;
1802 case Mips::ATOMIC_LOAD_MIN_I8:
1803 AtomicOp = Mips::ATOMIC_LOAD_MIN_I8_POSTRA;
1804 NeedsAdditionalReg =
true;
1806 case Mips::ATOMIC_LOAD_MIN_I16:
1807 AtomicOp = Mips::ATOMIC_LOAD_MIN_I16_POSTRA;
1808 NeedsAdditionalReg =
true;
1810 case Mips::ATOMIC_LOAD_MAX_I8:
1811 AtomicOp = Mips::ATOMIC_LOAD_MAX_I8_POSTRA;
1812 NeedsAdditionalReg =
true;
1814 case Mips::ATOMIC_LOAD_MAX_I16:
1815 AtomicOp = Mips::ATOMIC_LOAD_MAX_I16_POSTRA;
1816 NeedsAdditionalReg =
true;
1818 case Mips::ATOMIC_LOAD_UMIN_I8:
1819 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I8_POSTRA;
1820 NeedsAdditionalReg =
true;
1822 case Mips::ATOMIC_LOAD_UMIN_I16:
1823 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I16_POSTRA;
1824 NeedsAdditionalReg =
true;
1826 case Mips::ATOMIC_LOAD_UMAX_I8:
1827 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I8_POSTRA;
1828 NeedsAdditionalReg =
true;
1830 case Mips::ATOMIC_LOAD_UMAX_I16:
1831 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I16_POSTRA;
1832 NeedsAdditionalReg =
true;
1861 int64_t MaskImm = (
Size == 1) ? 255 : 65535;
1902 if (NeedsAdditionalReg) {
1908 MI.eraseFromParent();
1922 assert((
MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ||
1923 MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I64) &&
1924 "Unsupported atomic pseudo for EmitAtomicCmpSwap.");
1926 const unsigned Size =
MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ? 4 : 8;
1934 unsigned AtomicOp =
MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32
1935 ? Mips::ATOMIC_CMP_SWAP_I32_POSTRA
1936 : Mips::ATOMIC_CMP_SWAP_I64_POSTRA;
1951 Register OldValCopy =
MRI.createVirtualRegister(
MRI.getRegClass(OldVal));
1952 Register NewValCopy =
MRI.createVirtualRegister(
MRI.getRegClass(NewVal));
1970 MI.eraseFromParent();
1978 "Unsupported size for EmitAtomicCmpSwapPartial.");
2005 unsigned AtomicOp =
MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I8
2006 ? Mips::ATOMIC_CMP_SWAP_I8_POSTRA
2007 : Mips::ATOMIC_CMP_SWAP_I16_POSTRA;
2048 int64_t MaskImm = (
Size == 1) ? 255 : 65535;
2049 BuildMI(BB,
DL,
TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2)
2051 BuildMI(BB,
DL,
TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr)
2094 MI.eraseFromParent();
2119 FCC0, Dest, CondRes);
2141 "Floating point operand expected.");
2152 EVT Ty =
Op.getValueType();
2158 "Windows is the only supported COFF target");
2208 EVT Ty =
Op.getValueType();
2251 Args.push_back(Entry);
2256 .setLibCallee(
CallingConv::C, PtrTy, TlsGetAddr, std::move(Args));
2257 std::pair<SDValue, SDValue> CallResult =
LowerCallTo(CLI);
2303 EVT Ty =
Op.getValueType();
2316 EVT Ty =
Op.getValueType();
2345 const Value *SV = cast<SrcValueSDNode>(
Op.getOperand(2))->getValue();
2352 EVT VT =
Node->getValueType(0);
2357 const Value *SV = cast<SrcValueSDNode>(
Node->getOperand(2))->getValue();
2384 unsigned ArgSizeInBytes =
2400 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes;
2409 bool HasExtractInsert) {
2410 EVT TyX =
Op.getOperand(0).getValueType();
2411 EVT TyY =
Op.getOperand(1).getValueType();
2428 if (HasExtractInsert) {
2446 if (TyX == MVT::f32)
2456 bool HasExtractInsert) {
2457 unsigned WidthX =
Op.getOperand(0).getValueSizeInBits();
2458 unsigned WidthY =
Op.getOperand(1).getValueSizeInBits();
2467 if (HasExtractInsert) {
2473 if (WidthX > WidthY)
2475 else if (WidthY > WidthX)
2494 if (WidthX > WidthY)
2496 else if (WidthY > WidthX)
2514 bool HasExtractInsert)
const {
2526 Op.getOperand(0), Const1);
2529 if (HasExtractInsert)
2540 if (
Op.getValueType() == MVT::f32)
2554 bool HasExtractInsert)
const {
2565 if (HasExtractInsert)
2587 EVT VT =
Op.getValueType();
2601 if (
Op.getConstantOperandVal(0) != 0) {
2603 "return address can be determined only for current frame");
2609 EVT VT =
Op.getValueType();
2622 if (
Op.getConstantOperandVal(0) != 0) {
2624 "return address can be determined only for current frame");
2630 MVT VT =
Op.getSimpleValueType();
2631 unsigned RA =
ABI.
IsN64() ? Mips::RA_64 : Mips::RA;
2657 unsigned OffsetReg =
ABI.
IsN64() ? Mips::V1_64 : Mips::V1;
2658 unsigned AddrReg =
ABI.
IsN64() ? Mips::V0_64 : Mips::V0;
2748 DL, VTList,
Cond, ShiftRightHi,
2764 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
2765 EVT BasePtrVT =
Ptr.getValueType();
2775 LD->getMemOperand());
2781 EVT MemVT = LD->getMemoryVT();
2787 if ((LD->getAlign().value() >= (MemVT.
getSizeInBits() / 8)) ||
2788 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2792 EVT VT =
Op.getValueType();
2796 assert((VT == MVT::i32) || (VT == MVT::i64));
2839 SDValue Ops[] = { SRL, LWR.getValue(1) };
2912 ((MemVT == MVT::i32) || (MemVT == MVT::i64)))
2924 EVT ValTy =
Op->getValueType(0);
2970 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
2976 static const MCPhysReg FloatVectorIntRegs[] = { Mips::A0, Mips::A2 };
2984 if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) {
2988 else if (ArgFlags.
isZExt())
2996 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
3000 else if (ArgFlags.
isZExt())
3011 bool AllocateFloatsInIntReg = State.
isVarArg() || ValNo > 1 ||
3014 bool isI64 = (ValVT == MVT::i32 && OrigAlign ==
Align(8));
3018 if (ValVT == MVT::i32 && isVectorFloat) {
3025 if (Reg == Mips::A2)
3034 }
else if (ValVT == MVT::i32 ||
3035 (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
3039 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
3042 }
else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
3046 if (Reg == Mips::A1 || Reg == Mips::A3)
3062 if (ValVT == MVT::f32) {
3070 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
3089 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
3091 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
3097 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 };
3099 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
3106#include "MipsGenCallingConv.inc"
3109 return CC_Mips_FixedArg;
3121 const SDLoc &
DL,
bool IsTailCall,
3139 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
3140 bool IsPICCall,
bool GlobalOrExternal,
bool InternalLinkage,
3153 if (IsPICCall && !InternalLinkage && IsCallReloc) {
3154 unsigned GPReg =
ABI.
IsN64() ? Mips::GP_64 : Mips::GP;
3156 RegsToPass.push_back(std::make_pair(GPReg,
getGlobalReg(CLI.
DAG, Ty)));
3165 for (
auto &R : RegsToPass) {
3172 for (
auto &R : RegsToPass)
3179 assert(Mask &&
"Missing call preserved mask for calling convention");
3183 Function *
F =
G->getGlobal()->getParent()->getFunction(
Sym);
3184 if (
F &&
F->hasFnAttribute(
"__Mips16RetHelper")) {
3197 switch (
MI.getOpcode()) {
3201 case Mips::JALRPseudo:
3203 case Mips::JALR64Pseudo:
3204 case Mips::JALR16_MM:
3205 case Mips::JALRC16_MMR6:
3206 case Mips::TAILCALLREG:
3207 case Mips::TAILCALLREG64:
3208 case Mips::TAILCALLR6REG:
3209 case Mips::TAILCALL64R6REG:
3210 case Mips::TAILCALLREG_MM:
3211 case Mips::TAILCALLREG_MMR6: {
3215 Node->getNumOperands() < 1 ||
3216 Node->getOperand(0).getNumOperands() < 2) {
3222 const SDValue TargetAddr = Node->getOperand(0).getOperand(1);
3225 dyn_cast_or_null<const GlobalAddressSDNode>(TargetAddr)) {
3229 if (!isa<Function>(
G->getGlobal())) {
3230 LLVM_DEBUG(
dbgs() <<
"Not adding R_MIPS_JALR against data symbol "
3231 <<
G->getGlobal()->getName() <<
"\n");
3234 Sym =
G->getGlobal()->getName();
3237 dyn_cast_or_null<const ExternalSymbolSDNode>(TargetAddr)) {
3238 Sym = ES->getSymbol();
3281 dyn_cast_or_null<const ExternalSymbolSDNode>(Callee.getNode());
3313 unsigned ReservedArgArea =
3315 CCInfo.AllocateStack(ReservedArgArea,
Align(1));
3321 unsigned StackSize = CCInfo.getStackSize();
3328 bool InternalLinkage =
false;
3330 IsTailCall = isEligibleForTailCallOptimization(
3333 InternalLinkage =
G->getGlobal()->hasInternalLinkage();
3334 IsTailCall &= (InternalLinkage ||
G->getGlobal()->hasLocalLinkage() ||
3335 G->getGlobal()->hasPrivateLinkage() ||
3336 G->getGlobal()->hasHiddenVisibility() ||
3337 G->getGlobal()->hasProtectedVisibility());
3342 "site marked musttail");
3351 StackSize =
alignTo(StackSize, StackAlignment);
3353 if (!(IsTailCall || MemcpyInByVal))
3360 std::deque<std::pair<unsigned, SDValue>> RegsToPass;
3363 CCInfo.rewindByValRegsInfo();
3366 for (
unsigned i = 0, e = ArgLocs.
size(), OutIdx = 0; i != e; ++i, ++OutIdx) {
3367 SDValue Arg = OutVals[OutIdx];
3371 bool UseUpperBits =
false;
3374 if (
Flags.isByVal()) {
3375 unsigned FirstByValReg, LastByValReg;
3376 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3377 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3380 "ByVal args of size 0 should have been ignored by front-end.");
3381 assert(ByValIdx < CCInfo.getInRegsParamsCount());
3383 "Do not tail-call optimize if there is a byval argument.");
3384 passByValArg(Chain,
DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
3387 CCInfo.nextInRegsParam();
3397 if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
3398 (ValVT == MVT::f64 && LocVT == MVT::i64) ||
3399 (ValVT == MVT::i64 && LocVT == MVT::f64))
3401 else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
3412 Register LocRegHigh = ArgLocs[++i].getLocReg();
3413 RegsToPass.
push_back(std::make_pair(LocRegLo,
Lo));
3414 RegsToPass.push_back(std::make_pair(LocRegHigh,
Hi));
3423 UseUpperBits =
true;
3429 UseUpperBits =
true;
3435 UseUpperBits =
true;
3443 unsigned ValSizeInBits = Outs[OutIdx].ArgVT.getSizeInBits();
3453 RegsToPass.push_back(std::make_pair(VA.
getLocReg(), Arg));
3474 Chain, Arg,
DL, IsTailCall, DAG));
3479 if (!MemOpChains.
empty())
3487 bool GlobalOrExternal =
false, IsCallReloc =
false;
3496 if (
auto *
N = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3501 }
else if (
auto *
N = dyn_cast<GlobalAddressSDNode>(Callee)) {
3505 if (
auto *
F = dyn_cast<Function>(
N->getGlobal())) {
3506 if (
F->hasFnAttribute(
"long-call"))
3507 UseLongCalls =
true;
3508 else if (
F->hasFnAttribute(
"short-call"))
3509 UseLongCalls =
false;
3520 G->getGlobal()->hasDLLImportStorageClass()) {
3522 "Windows is the only supported COFF target");
3530 if (InternalLinkage)
3546 GlobalOrExternal =
true;
3549 const char *
Sym = S->getSymbol();
3565 GlobalOrExternal =
true;
3571 getOpndList(Ops, RegsToPass, IsPIC, GlobalOrExternal, InternalLinkage,
3572 IsCallReloc, CLI, Callee, Chain);
3588 if (!(MemcpyInByVal)) {
3595 return LowerCallResult(Chain, InGlue, CallConv, IsVarArg, Ins,
DL, DAG,
3601SDValue MipsTargetLowering::LowerCallResult(
3612 dyn_cast_or_null<const ExternalSymbolSDNode>(CLI.
Callee.
getNode());
3613 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI.
RetTy,
3617 for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
3622 RVLocs[i].getLocVT(), InGlue);
3627 unsigned ValSizeInBits =
Ins[i].ArgVT.getSizeInBits();
3728SDValue MipsTargetLowering::LowerFormalArguments(
3739 std::vector<SDValue> OutChains;
3749 if (
Func.hasFnAttribute(
"interrupt") && !
Func.arg_empty())
3751 "Functions with the interrupt attribute cannot have arguments!");
3753 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg);
3755 CCInfo.getInRegsParamsCount() > 0);
3757 unsigned CurArgIdx = 0;
3758 CCInfo.rewindByValRegsInfo();
3760 for (
unsigned i = 0, e = ArgLocs.
size(), InsIdx = 0; i != e; ++i, ++InsIdx) {
3762 if (Ins[InsIdx].isOrigArg()) {
3763 std::advance(FuncArg, Ins[InsIdx].getOrigArgIndex() - CurArgIdx);
3764 CurArgIdx =
Ins[InsIdx].getOrigArgIndex();
3770 if (
Flags.isByVal()) {
3771 assert(Ins[InsIdx].isOrigArg() &&
"Byval arguments cannot be implicit");
3772 unsigned FirstByValReg, LastByValReg;
3773 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3774 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3777 "ByVal args of size 0 should have been ignored by front-end.");
3778 assert(ByValIdx < CCInfo.getInRegsParamsCount());
3779 copyByValRegs(Chain,
DL, OutChains, DAG, Flags, InVals, &*FuncArg,
3780 FirstByValReg, LastByValReg, VA, CCInfo);
3781 CCInfo.nextInRegsParam();
3801 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
3802 (RegVT == MVT::i64 && ValVT == MVT::f64) ||
3803 (RegVT == MVT::f64 && ValVT == MVT::i64))
3805 else if (
ABI.
IsO32() && RegVT == MVT::i32 &&
3806 ValVT == MVT::f64) {
3815 ArgValue, ArgValue2);
3834 LocVT,
DL, Chain, FIN,
3836 OutChains.push_back(ArgValue.
getValue(1));
3845 for (
unsigned i = 0, e = ArgLocs.
size(), InsIdx = 0; i != e; ++i, ++InsIdx) {
3847 if (ArgLocs[i].needsCustom()) {
3855 if (Ins[InsIdx].
Flags.isSRet()) {
3869 writeVarArgRegs(OutChains, Chain,
DL, DAG, CCInfo);
3873 if (!OutChains.empty()) {
3874 OutChains.push_back(Chain);
3891 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
3892 return CCInfo.CheckCallReturn(Outs, RetCC_Mips,
RetTy);
3895bool MipsTargetLowering::shouldSignExtendTypeInLibCall(
Type *Ty,
3896 bool IsSigned)
const {
3930 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
3936 for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
3940 bool UseUpperBits =
false;
3951 UseUpperBits =
true;
3957 UseUpperBits =
true;
3963 UseUpperBits =
true;
3971 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
3997 unsigned V0 =
ABI.
IsN64() ? Mips::V0_64 : Mips::V0;
4012 return LowerInterruptReturn(RetOps,
DL, DAG);
4025MipsTargetLowering::getConstraintType(
StringRef Constraint)
const {
4037 if (Constraint.
size() == 1) {
4038 switch (Constraint[0]) {
4052 if (Constraint ==
"ZC")
4062MipsTargetLowering::getSingleConstraintMatchWeight(
4063 AsmOperandInfo &
info,
const char *constraint)
const {
4065 Value *CallOperandVal =
info.CallOperandVal;
4068 if (!CallOperandVal)
4072 switch (*constraint) {
4101 if (isa<ConstantInt>(CallOperandVal))
4116 unsigned long long &Reg) {
4117 if (
C.front() !=
'{' ||
C.back() !=
'}')
4118 return std::make_pair(
false,
false);
4122 I = std::find_if(
B, E, isdigit);
4128 return std::make_pair(
true,
false);
4139 return VT.
bitsLT(MinVT) ? MinVT : VT;
4142std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
4148 unsigned long long Reg;
4153 return std::make_pair(0U,
nullptr);
4155 if ((Prefix ==
"hi" || Prefix ==
"lo")) {
4158 return std::make_pair(0U,
nullptr);
4160 RC =
TRI->getRegClass(Prefix ==
"hi" ?
4161 Mips::HI32RegClassID : Mips::LO32RegClassID);
4162 return std::make_pair(*(RC->
begin()), RC);
4163 }
else if (Prefix.starts_with(
"$msa")) {
4168 return std::make_pair(0U,
nullptr);
4171 .
Case(
"$msair", Mips::MSAIR)
4172 .
Case(
"$msacsr", Mips::MSACSR)
4173 .
Case(
"$msaaccess", Mips::MSAAccess)
4174 .
Case(
"$msasave", Mips::MSASave)
4175 .
Case(
"$msamodify", Mips::MSAModify)
4176 .
Case(
"$msarequest", Mips::MSARequest)
4177 .
Case(
"$msamap", Mips::MSAMap)
4178 .
Case(
"$msaunmap", Mips::MSAUnmap)
4182 return std::make_pair(0U,
nullptr);
4184 RC =
TRI->getRegClass(Mips::MSACtrlRegClassID);
4185 return std::make_pair(Reg, RC);
4189 return std::make_pair(0U,
nullptr);
4191 if (Prefix ==
"$f") {
4194 if (VT == MVT::Other)
4199 if (RC == &Mips::AFGR64RegClass) {
4203 }
else if (Prefix ==
"$fcc")
4204 RC =
TRI->getRegClass(Mips::FCCRegClassID);
4205 else if (Prefix ==
"$w") {
4212 assert(Reg < RC->getNumRegs());
4213 return std::make_pair(*(RC->
begin() + Reg), RC);
4219std::pair<unsigned, const TargetRegisterClass *>
4223 if (Constraint.
size() == 1) {
4224 switch (Constraint[0]) {
4228 if ((VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8 ||
4232 return std::make_pair(0U, &Mips::CPU16RegsRegClass);
4233 return std::make_pair(0U, &Mips::GPR32RegClass);
4237 return std::make_pair(0U, &Mips::GPR32RegClass);
4240 return std::make_pair(0U, &Mips::GPR64RegClass);
4242 return std::make_pair(0U,
nullptr);
4244 if (VT == MVT::v16i8)
4245 return std::make_pair(0U, &Mips::MSA128BRegClass);
4246 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
4247 return std::make_pair(0U, &Mips::MSA128HRegClass);
4248 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
4249 return std::make_pair(0U, &Mips::MSA128WRegClass);
4250 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
4251 return std::make_pair(0U, &Mips::MSA128DRegClass);
4252 else if (VT == MVT::f32)
4253 return std::make_pair(0U, &Mips::FGR32RegClass);
4256 return std::make_pair(0U, &Mips::FGR64RegClass);
4257 return std::make_pair(0U, &Mips::AFGR64RegClass);
4262 return std::make_pair((
unsigned)Mips::T9, &Mips::GPR32RegClass);
4264 return std::make_pair((
unsigned)Mips::T9_64, &Mips::GPR64RegClass);
4266 return std::make_pair(0U,
nullptr);
4269 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
4270 return std::make_pair((
unsigned)Mips::LO0, &Mips::LO32RegClass);
4271 return std::make_pair((
unsigned)Mips::LO0_64, &Mips::LO64RegClass);
4276 return std::make_pair(0U,
nullptr);
4280 if (!Constraint.
empty()) {
4281 std::pair<unsigned, const TargetRegisterClass *>
R;
4282 R = parseRegForInlineAsmConstraint(Constraint, VT);
4293void MipsTargetLowering::LowerAsmOperandForConstraint(
SDValue Op,
4295 std::vector<SDValue> &Ops,
4301 if (Constraint.
size() > 1)
4304 char ConstraintLetter = Constraint[0];
4305 switch (ConstraintLetter) {
4311 int64_t Val =
C->getSExtValue();
4312 if (isInt<16>(Val)) {
4321 int64_t Val =
C->getZExtValue();
4332 if (isUInt<16>(Val)) {
4341 int64_t Val =
C->getSExtValue();
4342 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
4351 int64_t Val =
C->getSExtValue();
4352 if ((Val >= -65535) && (Val <= -1)) {
4361 int64_t Val =
C->getSExtValue();
4362 if ((isInt<15>(Val))) {
4371 int64_t Val =
C->getSExtValue();
4372 if ((Val <= 65535) && (Val >= 1)) {
4381 Ops.push_back(Result);
4388bool MipsTargetLowering::isLegalAddressingMode(
const DataLayout &
DL,
4416EVT MipsTargetLowering::getOptimalMemOpType(
4424bool MipsTargetLowering::isFPImmLegal(
const APFloat &Imm,
EVT VT,
4425 bool ForCodeSize)
const {
4426 if (VT != MVT::f32 && VT != MVT::f64)
4428 if (
Imm.isNegZero())
4430 return Imm.isZero();
4433unsigned MipsTargetLowering::getJumpTableEncoding()
const {
4442bool MipsTargetLowering::useSoftFloat()
const {
4446void MipsTargetLowering::copyByValRegs(
4450 unsigned FirstReg,
unsigned LastReg,
const CCValAssign &VA,
4455 unsigned NumRegs = LastReg - FirstReg;
4456 unsigned RegAreaSize = NumRegs * GPRSizeInBytes;
4457 unsigned FrameObjSize = std::max(
Flags.getByValSize(), RegAreaSize);
4464 (
int)((ByValArgRegs.
size() - FirstReg) * GPRSizeInBytes);
4486 for (
unsigned I = 0;
I < NumRegs; ++
I) {
4487 unsigned ArgReg = ByValArgRegs[FirstReg +
I];
4488 unsigned VReg =
addLiveIn(MF, ArgReg, RC);
4489 unsigned Offset =
I * GPRSizeInBytes;
4494 OutChains.push_back(Store);
4499void MipsTargetLowering::passByValArg(
4501 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
4506 unsigned ByValSizeInBytes =
Flags.getByValSize();
4507 unsigned OffsetInBytes = 0;
4510 std::min(
Flags.getNonZeroByValAlign(),
Align(RegSizeInBytes));
4513 unsigned NumRegs = LastReg - FirstReg;
4517 bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes);
4521 for (;
I < NumRegs - LeftoverBytes; ++
I, OffsetInBytes += RegSizeInBytes) {
4527 unsigned ArgReg = ArgRegs[FirstReg +
I];
4528 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
4532 if (ByValSizeInBytes == OffsetInBytes)
4536 if (LeftoverBytes) {
4539 for (
unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0;
4540 OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) {
4541 unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes;
4543 if (RemainingSizeInBytes < LoadSizeInBytes)
4559 Shamt = TotalBytesLoaded * 8;
4561 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8;
4571 OffsetInBytes += LoadSizeInBytes;
4572 TotalBytesLoaded += LoadSizeInBytes;
4573 Alignment = std::min(Alignment,
Align(LoadSizeInBytes));
4576 unsigned ArgReg = ArgRegs[FirstReg +
I];
4577 RegsToPass.push_back(std::make_pair(ArgReg, Val));
4583 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes;
4590 Align(Alignment),
false,
false,
4595void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
4616 (
int)(RegSizeInBytes * (ArgRegs.
size() -
Idx));
4628 for (
unsigned I =
Idx;
I < ArgRegs.
size();
4629 ++
I, VaArgOffset += RegSizeInBytes) {
4636 cast<StoreSDNode>(
Store.getNode())->getMemOperand()->setValue(
4638 OutChains.push_back(Store);
4643 Align Alignment)
const {
4646 assert(
Size &&
"Byval argument's size shouldn't be 0.");
4650 unsigned FirstReg = 0;
4651 unsigned NumRegs = 0;
4663 Alignment >=
Align(RegSizeInBytes) &&
4664 "Byval argument's alignment should be a multiple of RegSizeInBytes.");
4672 if ((Alignment > RegSizeInBytes) && (FirstReg % 2)) {
4673 State->
AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]);
4679 for (
unsigned I = FirstReg;
Size > 0 && (
I < IntArgRegs.
size());
4680 Size -= RegSizeInBytes, ++
I, ++NumRegs)
4690 unsigned Opc)
const {
4692 "Subtarget already supports SELECT nodes with the use of"
4693 "conditional-move instructions.");
4716 F->insert(It, copy0MBB);
4717 F->insert(It, sinkMBB);
4760 MI.eraseFromParent();
4769 "Subtarget already supports SELECT nodes with the use of"
4770 "conditional-move instructions.");
4793 F->insert(It, copy0MBB);
4794 F->insert(It, sinkMBB);
4836 MI.eraseFromParent();
4849 .
Case(
"$28", Mips::GP_64)
4850 .
Case(
"sp", Mips::SP_64)
4856 .
Case(
"$28", Mips::GP)
4857 .
Case(
"sp", Mips::SP)
4875 unsigned Imm =
MI.getOperand(2).getImm();
4881 Register Temp =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4890 Register LoadHalf =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4891 Register LoadFull =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4892 Register Undef =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4897 .
addImm(Imm + (IsLittle ? 0 : 3))
4902 .
addImm(Imm + (IsLittle ? 3 : 0))
4907 MI.eraseFromParent();
4921 unsigned Imm =
MI.getOperand(2).getImm();
4928 Register Temp =
MRI.createVirtualRegister(&Mips::GPR64RegClass);
4935 Register Wtemp =
MRI.createVirtualRegister(&Mips::MSA128WRegClass);
4936 Register Lo =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4937 Register Hi =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4941 .
addImm(Imm + (IsLittle ? 0 : 4));
4945 .
addImm(Imm + (IsLittle ? 4 : 0));
4955 Register LoHalf =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4956 Register LoFull =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4957 Register LoUndef =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4958 Register HiHalf =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4959 Register HiFull =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4960 Register HiUndef =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4961 Register Wtemp =
MRI.createVirtualRegister(&Mips::MSA128WRegClass);
4966 .
addImm(Imm + (IsLittle ? 0 : 7))
4971 .
addImm(Imm + (IsLittle ? 3 : 4))
4977 .
addImm(Imm + (IsLittle ? 4 : 3))
4982 .
addImm(Imm + (IsLittle ? 7 : 0))
4991 MI.eraseFromParent();
5003 Register StoreVal =
MI.getOperand(0).getReg();
5005 unsigned Imm =
MI.getOperand(2).getImm();
5011 Register BitcastW =
MRI.createVirtualRegister(&Mips::MSA128WRegClass);
5012 Register Tmp =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
5025 Register Tmp =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
5033 .
addImm(Imm + (IsLittle ? 0 : 3));
5037 .
addImm(Imm + (IsLittle ? 3 : 0));
5040 MI.eraseFromParent();
5053 Register StoreVal =
MI.getOperand(0).getReg();
5055 unsigned Imm =
MI.getOperand(2).getImm();
5062 Register BitcastD =
MRI.createVirtualRegister(&Mips::MSA128DRegClass);
5063 Register Lo =
MRI.createVirtualRegister(&Mips::GPR64RegClass);
5076 Register BitcastW =
MRI.createVirtualRegister(&Mips::MSA128WRegClass);
5077 Register Lo =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
5078 Register Hi =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
5093 .
addImm(Imm + (IsLittle ? 0 : 4));
5097 .
addImm(Imm + (IsLittle ? 4 : 0));
5103 Register Lo =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
5104 Register Hi =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
5117 .
addImm(Imm + (IsLittle ? 0 : 3));
5121 .
addImm(Imm + (IsLittle ? 3 : 0));
5125 .
addImm(Imm + (IsLittle ? 4 : 7));
5129 .
addImm(Imm + (IsLittle ? 7 : 4));
5132 MI.eraseFromParent();
unsigned const MachineRegisterInfo * MRI
static SDValue performSHLCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
If the operand is a bitwise AND with a constant RHS, and the shift has a constant RHS and is the only...
static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget, const AArch64TargetLowering &TLI)
static SDValue performANDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
This file declares a class to represent arbitrary precision floating point values and provide a varie...
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Function Alias Analysis Results
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
#define LLVM_ATTRIBUTE_UNUSED
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
const HexagonInstrInfo * TII
Module.h This file contains the declarations for the Module class.
static MachineBasicBlock * insertDivByZeroTrap(MachineInstr &MI, MachineBasicBlock *MBB)
unsigned const TargetRegisterInfo * TRI
cl::opt< bool > EmitJalrReloc
static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State) LLVM_ATTRIBUTE_UNUSED
static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, ArrayRef< MCPhysReg > F64Regs)
static SDValue performMADD_MSUBCombine(SDNode *ROOTNode, SelectionDAG &CurDAG, const MipsSubtarget &Subtarget)
static bool invertFPCondCodeUser(Mips::CondCode CC)
This function returns true if the floating point conditional branches and conditional moves which use...
static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG, bool SingleFloat)
static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static const MCPhysReg Mips64DPRegs[8]
static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, bool IsLittle)
static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, SDValue Chain, unsigned Offset)
static unsigned addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
static std::pair< bool, bool > parsePhysicalReg(StringRef C, StringRef &Prefix, unsigned long long &Reg)
This is a helper function to parse a physical register string and split it into non-numeric and numer...
static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, SDValue Chain, SDValue Src, unsigned Offset)
static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasExtractInsert)
static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
cl::opt< bool > EmitJalrReloc
static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op)
static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasExtractInsert)
static cl::opt< bool > NoZeroDivCheck("mno-check-zero-division", cl::Hidden, cl::desc("MIPS: Don't trap on integer division by zero."), cl::init(false))
static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA, EVT ArgVT, const SDLoc &DL, SelectionDAG &DAG)
static Mips::CondCode condCodeToFCC(ISD::CondCode CC)
static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, SDValue False, const SDLoc &DL)
uint64_t IntrinsicInst * II
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SI optimize exec mask operations pre RA
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
This file defines the SmallVector class.
static const MCPhysReg IntRegs[32]
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
static const MCPhysReg F32Regs[64]
This class represents an incoming formal argument to a Function.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
LLVM Basic Block Representation.
static BranchProbability getOne()
CCState - This class holds information needed while lowering arguments and return values.
MachineFunction & getMachineFunction() const
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set,...
CallingConv::ID getCallingConv() const
MCRegister AllocateReg(MCPhysReg Reg)
AllocateReg - Attempt to allocate one register.
int64_t AllocateStack(unsigned Size, Align Alignment)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
uint64_t getStackSize() const
Returns the size of the currently allocated portion of the stack.
void addInRegsParamInfo(unsigned RegBegin, unsigned RegEnd)
void addLoc(const CCValAssign &V)
CCValAssign - Represent assignment of one arg/retval to a location.
Register getLocReg() const
LocInfo getLocInfo() const
static CCValAssign getReg(unsigned ValNo, MVT ValVT, MCRegister Reg, MVT LocVT, LocInfo HTP, bool IsCustom=false)
static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT, MCRegister Reg, MVT LocVT, LocInfo HTP)
bool isUpperBitsInLoc() const
static CCValAssign getMem(unsigned ValNo, MVT ValVT, int64_t Offset, MVT LocVT, LocInfo HTP, bool IsCustom=false)
int64_t getLocMemOffset() const
bool isMustTailCall() const
Tests if this call site must be tail call optimized.
uint64_t getZExtValue() const
int64_t getSExtValue() const
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
TypeSize getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
const char * getSymbol() const
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
const GlobalValue * getGlobal() const
bool hasLocalLinkage() const
bool hasDLLImportStorageClass() const
const GlobalObject * getAliaseeObject() const
bool hasInternalLinkage() const
Class to represent integer types.
This is an important class for using LLVM in a threaded context.
void emitError(const Instruction *I, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
This class is used to represent ISD::LOAD nodes.
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Wrapper class representing physical registers. Should be passed by value.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
static auto integer_valuetypes()
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
static MVT getVectorVT(MVT VT, unsigned NumElements)
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
bool isValid() const
Return true if this is a valid simple valuetype.
static MVT getIntegerVT(unsigned BitWidth)
static auto fp_valuetypes()
static auto fp_fixedlen_vector_valuetypes()
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
void setFrameAddressIsTaken(bool T)
void setHasTailCall(bool V=true)
void setReturnAddressIsTaken(bool s)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MCContext & getContext() const
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
void insert(iterator MBBI, MachineBasicBlock *MBB)
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
const MachineOperand & getOperand(unsigned i) const
@ EK_GPRel64BlockAddress
EK_GPRel64BlockAddress - Each entry is an address of block, encoded with a relocation as gp-relative,...
@ MOVolatile
The memory access is volatile.
Flags getFlags() const
Return the raw flags of the source value,.
MachineOperand class - Representation of each machine instruction operand.
void setSubReg(unsigned subReg)
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
void setIsKill(bool Val=true)
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
const MachinePointerInfo & getPointerInfo() const
const SDValue & getChain() const
EVT getMemoryVT() const
Return the type of the in-memory value.
ArrayRef< MCPhysReg > GetVarArgRegs() const
The registers to use for the variable argument list.
bool ArePtrs64bit() const
unsigned GetCalleeAllocdArgSizeInBytes(CallingConv::ID CC) const
Obtain the size of the area allocated by the callee for arguments.
unsigned GetPtrAddiuOp() const
unsigned GetPtrAndOp() const
ArrayRef< MCPhysReg > GetByValArgRegs() const
The registers to use for byval arguments.
unsigned GetNullPtr() const
bool WasOriginalArgVectorFloat(unsigned ValNo) const
static SpecialCallingConvType getSpecialCallingConvForCallee(const SDNode *Callee, const MipsSubtarget &Subtarget)
Determine the SpecialCallingConvType for the given callee.
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
void setVarArgsFrameIndex(int Index)
unsigned getSRetReturnReg() const
int getVarArgsFrameIndex() const
MachinePointerInfo callPtrInfo(MachineFunction &MF, const char *ES)
Create a MachinePointerInfo that has an ExternalSymbolPseudoSourceValue object representing a GOT ent...
Register getGlobalBaseReg(MachineFunction &MF)
void setSRetReturnReg(unsigned Reg)
void setFormalArgInfo(unsigned Size, bool HasByval)
static const uint32_t * getMips16RetHelperMask()
bool inMicroMipsMode() const
bool useSoftFloat() const
const MipsInstrInfo * getInstrInfo() const override
bool inMips16Mode() const
bool inAbs2008Mode() const
const MipsRegisterInfo * getRegisterInfo() const override
bool systemSupportsUnalignedAccess() const
Does the system support unaligned memory access.
bool hasExtractInsert() const
Features related to the presence of specific instructions.
bool isTargetCOFF() const
bool isTargetWindows() const
bool isSingleFloat() const
bool useLongCalls() const
unsigned getGPRSizeInBytes() const
bool inMips16HardFloat() const
const TargetFrameLowering * getFrameLowering() const override
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the register type for a given MVT, ensuring vectors are treated as a series of gpr sized integ...
bool hasBitTest(SDValue X, SDValue Y) const override
Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be us...
static const MipsTargetLowering * create(const MipsTargetMachine &TM, const MipsSubtarget &STI)
SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN64) const
unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override
Break down vectors to the correct number of gpr sized integers.
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName - This method returns the name of a target specific
SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - get the ISD::SETCC result ValueType
SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned Flag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
createFastISel - This method returns a target specific FastISel object, or null if the target does no...
MipsTargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned HiFlag, unsigned LoFlag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
SDValue getDllimportVariable(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, SDValue Chain, const MachinePointerInfo &PtrInfo) const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
CCAssignFn * CCAssignFnForReturn() const
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
SDValue getDllimportSymbol(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
CCAssignFn * CCAssignFnForCall() const
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the number of registers for a given MVT, ensuring vectors are treated as a series of gpr sized...
SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
virtual void getOpndList(SmallVectorImpl< SDValue > &Ops, std::deque< std::pair< unsigned, SDValue > > &RegsToPass, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const
This function fills Ops, which is the list of operands that will later be used when a function call n...
EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const override
Return the type that should be used to zero or sign extend a zeroext/signext integer return value.
bool isCheapToSpeculateCtlz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
bool isCheapToSpeculateCttz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
bool shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to fold a pair of shifts into a mask.
SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN32OrN64) const
SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const
const MipsSubtarget & Subtarget
void HandleByVal(CCState *, unsigned &, Align) const override
Target-specific cleanup for formal ByVal parameters.
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const
bool IsConstantInSmallSection(const DataLayout &DL, const Constant *CN, const TargetMachine &TM) const
Return true if this constant should be placed into small data section.
Wrapper class representing virtual and physical registers.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
uint64_t getAsZExtVal() const
Helper method returns the zero-extended integer value of a ConstantSDNode.
const SDValue & getOperand(unsigned Num) const
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getValue(unsigned R) const
EVT getValueType() const
Return the ValueType of the referenced return value.
TypeSize getValueSizeInBits() const
Returns the size of the value in bits.
const SDValue & getOperand(unsigned i) const
unsigned getOpcode() const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, Register Reg, SDValue N)
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
SDValue getRegister(Register Reg, EVT VT)
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, const CallInst *CI, std::optional< bool > OverrideTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), BatchAAResults *BatchAA=nullptr)
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, Register Reg, EVT VT)
const DataLayout & getDataLayout() const
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getSignedTargetConstant(int64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue getSignedConstant(int64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
SDValue getExternalSymbol(const char *Sym, EVT VT)
const TargetMachine & getTarget() const
SDValue getSelectCC(const SDLoc &DL, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode Cond)
Helper function to make it easier to build SelectCC's if you just have an ISD::CondCode instead of an...
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
SDValue getValueType(EVT)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
bool isKnownNeverNaN(SDValue Op, bool SNaN=false, unsigned Depth=0) const
Test whether the given SDValue (or all elements of it, if it is a vector) is known to never be NaN.
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone.
MachineFunction & getMachineFunction() const
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
SDValue getRegisterMask(const uint32_t *RegMask)
void addCallSiteInfo(const SDNode *Node, CallSiteInfo &&CallInfo)
Set CallSiteInfo to be associated with Node.
LLVMContext * getContext() const
SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MOLoad|MachineMemOperand::MOStore, LocationSize Size=0, const AAMDNodes &AAInfo=AAMDNodes())
Creates a MemIntrinsicNode that may produce a result and takes a list of operands.
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offset=0, unsigned TargetFlags=0)
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
std::pair< SDValue, SDValue > SplitScalar(const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HiVT)
Split the scalar node with EXTRACT_ELEMENT using the provided VTs and return the low/high part.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
This class is used to represent ISD::STORE nodes.
const SDValue & getBasePtr() const
const SDValue & getValue() const
bool isTruncatingStore() const
Return true if the op does a truncation before store.
StringRef - Represent a constant reference to a string, i.e.
constexpr bool empty() const
empty - Check if the string is empty.
constexpr size_t size() const
size - Get the string size.
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
Information about stack frame layout on the target.
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
TargetInstrInfo - Interface to description of machine instruction set.
Provides information about what library functions are available for the current target.
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
void setMinStackArgumentAlignment(Align Alignment)
Set the minimum stack alignment of an argument.
const TargetMachine & getTargetMachine() const
virtual unsigned getNumRegisters(LLVMContext &Context, EVT VT, std::optional< MVT > RegisterVT=std::nullopt) const
Return the number of registers that this ValueType will eventually require.
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
@ ZeroOrOneBooleanContent
@ ZeroOrNegativeOneBooleanContent
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
void setTargetDAGCombine(ArrayRef< ISD::NodeType > NTs)
Targets should invoke this method for each target independent node that they want to provide a custom...
Align getMinStackArgumentAlignment() const
Return the minimum stack alignment of an argument.
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
std::vector< ArgListEntry > ArgListTy
unsigned MaxStoresPerMemcpy
Specify maximum number of store instructions per memcpy call.
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA, SelectionDAG &DAG) const
Lower TLS global address SDNode for target independent emulated TLS model.
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
bool isPositionIndependent() const
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
virtual void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
virtual unsigned getJumpTableEncoding() const
Return the entry encoding for a jump table in the current function.
virtual void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
TLSModel::Model getTLSModel(const GlobalValue *GV) const
Returns the TLS model which should be used for the given global variable.
bool useEmulatedTLS() const
Returns true if this target uses emulated TLS.
virtual TargetLoweringObjectFile * getObjFileLowering() const
unsigned NoNaNsFPMath
NoNaNsFPMath - This flag is enabled when the -enable-no-nans-fp-math flag is specified on the command...
iterator begin() const
begin/end - Return all of the registers in this class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
bool isVectorTy() const
True if this is an instance of VectorType.
bool isFloatTy() const
Return true if this is 'float', a 32-bit IEEE fp type.
static IntegerType * getIntNTy(LLVMContext &C, unsigned N)
bool isIntegerTy() const
True if this is an instance of IntegerType.
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
LLVM Value Representation.
Type * getType() const
All values are typed, get the type of this value.
constexpr ScalarTy getFixedValue() const
self_iterator getIterator()
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
@ Fast
Attempts to make calls as fast as possible (e.g.
@ C
The default llvm calling convention, compatible with C.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
@ BSWAP
Byte Swap and Counting operators.
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
@ ATOMIC_STORE
OUTCHAIN = ATOMIC_STORE(INCHAIN, val, ptr) This corresponds to "store atomic" instruction.
@ ADD
Simple integer binary arithmetic operators.
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
@ FADD
Simple binary floating point operators.
@ ATOMIC_FENCE
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
@ FP16_TO_FP
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
@ BUILD_PAIR
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
@ EH_RETURN
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin,...
@ SIGN_EXTEND
Conversion operators.
@ FSINCOS
FSINCOS - Compute both fsin and fcos as a single operation.
@ BR_CC
BR_CC - Conditional branch.
@ BR_JT
BR_JT - Jumptable branch.
@ FCANONICALIZE
Returns platform specific canonical encoding of a floating point number.
@ IS_FPCLASS
Performs a check of floating point class property, defined by IEEE-754.
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
@ ATOMIC_LOAD
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
@ SHL
Shift and rotation operations.
@ FMINNUM_IEEE
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimumNumber or maximumNumber on two values,...
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
@ EH_DWARF_CFA
EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical Frame Address (CFA),...
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ TRAP
TRAP - Trapping instruction.
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
@ BRCOND
BRCOND - Conditional branch.
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
@ CALLSEQ_START
CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end of a call sequence,...
CondCode getSetCCInverse(CondCode Operation, EVT Type)
Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
@ Bitcast
Perform the operation on a different, but equivalently sized type.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
@ MO_GOT_CALL
MO_GOT_CALL - Represents the offset into the global offset table at which the address of a call site ...
@ MO_TPREL_HI
MO_TPREL_HI/LO - Represents the hi and low part of the offset from.
@ MO_GOT
MO_GOT - Represents the offset into the global offset table at which the address the relocation entry...
@ MO_JALR
Helper operand used to generate R_MIPS_JALR.
@ MO_GOTTPREL
MO_GOTTPREL - Represents the offset from the thread pointer (Initial.
@ MO_GOT_HI16
MO_GOT_HI16/LO16, MO_CALL_HI16/LO16 - Relocations used for large GOTs.
@ MO_TLSLDM
MO_TLSLDM - Represents the offset into the global offset table at which.
@ MO_TLSGD
MO_TLSGD - Represents the offset into the global offset table at which.
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Define
Register definition.
@ Kill
The last use of a register.
@ EarlyClobber
Register definition happens before uses.
Not(const Pred &P) -> Not< Pred >
Reg
All possible values of the reg field in the ModR/M byte.
initializer< Ty > init(const Ty &Val)
NodeAddr< FuncNode * > Func
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
constexpr bool isShiftedMask_64(uint64_t Value)
Return true if the argument contains a non-empty sequence of ones with the remainder zero (64 bit ver...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
constexpr T divideCeil(U Numerator, V Denominator)
Returns the integer ceil(Numerator / Denominator).
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
const MipsTargetLowering * createMips16TargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Create MipsTargetLowering objects.
@ Or
Bitwise or logical OR of integers.
unsigned getKillRegState(bool B)
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
DWARFExpression::Operation Op
const MipsTargetLowering * createMipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
bool getAsUnsignedInteger(StringRef Str, unsigned Radix, unsigned long long &Result)
Helper functions for StringRef::getAsInteger.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
This struct is a compact representation of a valid (non-zero power of two) alignment.
uint64_t value() const
This is a hole in the type system and should not be abused.
EVT changeVectorElementTypeToInteger() const
Return a vector with the same number of elements as this vector, but with the element type converted ...
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
bool isPow2VectorType() const
Returns true if the given vector is a power of 2.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
static EVT getFloatingPointVT(unsigned BitWidth)
Returns the EVT that represents a floating-point type with the given number of bits.
bool isVector() const
Return true if this is a vector value type.
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
bool isRound() const
Return true if the size is a power-of-two number of bytes.
EVT getVectorElementType() const
Given a vector type, return the type of each element.
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
bool isInteger() const
Return true if this is an integer or a vector integer type.
Align getNonZeroOrigAlign() const
SmallVector< ArgRegPair, 1 > ArgRegPairs
Vector of call argument and its forwarding register.
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Align valueOrOne() const
For convenience, returns a valid alignment or 1 if undefined.
These are IR-level optimization flags that may be propagated to SDNodes.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
This structure contains all information that is necessary for lowering calls.
SmallVector< ISD::InputArg, 32 > Ins
SmallVector< ISD::OutputArg, 32 > Outs
SmallVector< SDValue, 32 > OutVals
bool isBeforeLegalizeOps() const
