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PPCISelLowering.h
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1//===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that PPC uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
15#define LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
16
17#include "PPCInstrInfo.h"
26#include "llvm/IR/Attributes.h"
27#include "llvm/IR/CallingConv.h"
28#include "llvm/IR/Function.h"
29#include "llvm/IR/InlineAsm.h"
30#include "llvm/IR/Metadata.h"
31#include "llvm/IR/Type.h"
32#include <optional>
33#include <utility>
34
35namespace llvm {
36
37 namespace PPCISD {
38
39 // When adding a NEW PPCISD node please add it to the correct position in
40 // the enum. The order of elements in this enum matters!
41 // Values that are added between FIRST_MEMORY_OPCODE and LAST_MEMORY_OPCODE
42 // are considered memory opcodes and are treated differently than other
43 // entries.
44 enum NodeType : unsigned {
45 // Start the numbering where the builtin ops and target ops leave off.
47
48 /// FSEL - Traditional three-operand fsel node.
49 ///
51
52 /// XSMAXC[DQ]P, XSMINC[DQ]P - C-type min/max instructions.
55
56 /// FCFID - The FCFID instruction, taking an f64 operand and producing
57 /// and f64 value containing the FP representation of the integer that
58 /// was temporarily in the f64 operand.
60
61 /// Newer FCFID[US] integer-to-floating-point conversion instructions for
62 /// unsigned integers and single-precision outputs.
66
67 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
68 /// operand, producing an f64 value containing the integer representation
69 /// of that FP value.
72
73 /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
74 /// unsigned integers with round toward zero.
77
78 /// VEXTS, ByteWidth - takes an input in VSFRC and produces an output in
79 /// VSFRC that is sign-extended from ByteWidth to a 64-byte integer.
81
82 /// Reciprocal estimate instructions (unary FP ops).
85
86 /// Test instruction for software square root.
88
89 /// Square root instruction.
91
92 /// VPERM - The PPC VPERM Instruction.
93 ///
95
96 /// XXSPLT - The PPC VSX splat instructions
97 ///
99
100 /// XXSPLTI_SP_TO_DP - The PPC VSX splat instructions for immediates for
101 /// converting immediate single precision numbers to double precision
102 /// vector or scalar.
104
105 /// XXSPLTI32DX - The PPC XXSPLTI32DX instruction.
106 ///
108
109 /// VECINSERT - The PPC vector insert instruction
110 ///
112
113 /// VECSHL - The PPC vector shift left instruction
114 ///
116
117 /// XXPERMDI - The PPC XXPERMDI instruction
118 ///
121
122 /// The CMPB instruction (takes two operands of i32 or i64).
124
125 /// Hi/Lo - These represent the high and low 16-bit parts of a global
126 /// address respectively. These nodes have two operands, the first of
127 /// which must be a TargetGlobalAddress, and the second of which must be a
128 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
129 /// though these are usually folded into other nodes.
132
133 /// The following two target-specific nodes are used for calls through
134 /// function pointers in the 64-bit SVR4 ABI.
135
136 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
137 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
138 /// compute an allocation on the stack.
140
141 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
142 /// compute an offset from native SP to the address of the most recent
143 /// dynamic alloca.
145
146 /// To avoid stack clash, allocation is performed by block and each block is
147 /// probed.
149
150 /// The result of the mflr at function entry, used for PIC code.
152
153 /// These nodes represent PPC shifts.
154 ///
155 /// For scalar types, only the last `n + 1` bits of the shift amounts
156 /// are used, where n is log2(sizeof(element) * 8). See sld/slw, etc.
157 /// for exact behaviors.
158 ///
159 /// For vector types, only the last n bits are used. See vsld.
163
164 /// These nodes represent PPC arithmetic operations with carry.
169
170 /// FNMSUB - Negated multiply-subtract instruction.
172
173 /// EXTSWSLI = The PPC extswsli instruction, which does an extend-sign
174 /// word and shift left immediate.
176
177 /// The combination of sra[wd]i and addze used to implemented signed
178 /// integer division by a power of 2. The first operand is the dividend,
179 /// and the second is the constant shift amount (representing the
180 /// divisor).
182
183 /// CALL - A direct function call.
184 /// CALL_NOP is a call with the special NOP which follows 64-bit
185 /// CALL_NOTOC the caller does not use the TOC.
186 /// SVR4 calls and 32-bit/64-bit AIX calls.
190
191 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
192 /// MTCTR instruction.
194
195 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
196 /// BCTRL instruction.
198
199 /// CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl
200 /// instruction and the TOC reload required on 64-bit ELF, 32-bit AIX
201 /// and 64-bit AIX.
203
204 /// The variants that implicitly define rounding mode for calls with
205 /// strictfp semantics.
211
212 /// Return with a glue operand, matched by 'blr'
214
215 /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
216 /// This copies the bits corresponding to the specified CRREG into the
217 /// resultant GPR. Bits corresponding to other CR regs are undefined.
219
220 /// Direct move from a VSX register to a GPR
222
223 /// Direct move from a GPR to a VSX register (algebraic)
225
226 /// Direct move from a GPR to a VSX register (zero)
228
229 /// Direct move of 2 consecutive GPR to a VSX register.
231
232 /// BUILD_SPE64 and EXTRACT_SPE are analogous to BUILD_PAIR and
233 /// EXTRACT_ELEMENT but take f64 arguments instead of i64, as i64 is
234 /// unsupported for this target.
235 /// Merge 2 GPRs to a single SPE register.
237
238 /// Extract SPE register component, second argument is high or low.
240
241 /// Extract a subvector from signed integer vector and convert to FP.
242 /// It is primarily used to convert a (widened) illegal integer vector
243 /// type to a legal floating point vector type.
244 /// For example v2i32 -> widened to v4i32 -> v2f64
246
247 /// Extract a subvector from unsigned integer vector and convert to FP.
248 /// As with SINT_VEC_TO_FP, used for converting illegal types.
250
251 /// PowerPC instructions that have SCALAR_TO_VECTOR semantics tend to
252 /// place the value into the least significant element of the most
253 /// significant doubleword in the vector. This is not element zero for
254 /// anything smaller than a doubleword on either endianness. This node has
255 /// the same semantics as SCALAR_TO_VECTOR except that the value remains in
256 /// the aforementioned location in the vector register.
258
259 // FIXME: Remove these once the ANDI glue bug is fixed:
260 /// i1 = ANDI_rec_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the
261 /// eq or gt bit of CR0 after executing andi. x, 1. This is used to
262 /// implement truncation of i32 or i64 to i1.
265
266 // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit
267 // target (returns (Lo, Hi)). It takes a chain operand.
269
270 // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
272
273 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
275
276 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
277 /// instructions. For lack of better number, we use the opcode number
278 /// encoding for the OPC field to identify the compare. For example, 838
279 /// is VCMPGTSH.
281
282 /// RESVEC, OUTFLAG = VCMP_rec(LHS, RHS, OPC) - Represents one of the
283 /// altivec VCMP*_rec instructions. For lack of better number, we use the
284 /// opcode number encoding for the OPC field to identify the compare. For
285 /// example, 838 is VCMPGTSH.
287
288 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
289 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
290 /// condition register to branch on, OPC is the branch opcode to use (e.g.
291 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
292 /// an optional input flag argument.
294
295 /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based
296 /// loops.
299
300 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding
301 /// towards zero. Used only as part of the long double-to-int
302 /// conversion sequence.
304
305 /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
307
308 /// TC_RETURN - A tail call return.
309 /// operand #0 chain
310 /// operand #1 callee (register or absolute)
311 /// operand #2 stack adjustment
312 /// operand #3 optional in flag
314
315 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
318
319 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS
320 /// for non-position independent code on PPC32.
322
323 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and
324 /// local dynamic TLS and position indendepent code on PPC32.
326
327 /// G8RC = ADDIS_GOT_TPREL_HA %x2, Symbol - Used by the initial-exec
328 /// TLS model, produces an ADDIS8 instruction that adds the GOT
329 /// base to sym\@got\@tprel\@ha.
331
332 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
333 /// TLS model, produces a LD instruction with base register G8RReg
334 /// and offset sym\@got\@tprel\@l. This completes the addition that
335 /// finds the offset of "sym" relative to the thread pointer.
337
338 /// G8RC = ADD_TLS G8RReg, Symbol - Can be used by the initial-exec
339 /// and local-exec TLS models, produces an ADD instruction that adds
340 /// the contents of G8RReg to the thread pointer. Symbol contains a
341 /// relocation sym\@tls which is to be replaced by the thread pointer
342 /// and identifies to the linker that the instruction is part of a
343 /// TLS sequence.
345
346 /// G8RC = ADDIS_TLSGD_HA %x2, Symbol - For the general-dynamic TLS
347 /// model, produces an ADDIS8 instruction that adds the GOT base
348 /// register to sym\@got\@tlsgd\@ha.
350
351 /// %x3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
352 /// model, produces an ADDI8 instruction that adds G8RReg to
353 /// sym\@got\@tlsgd\@l and stores the result in X3. Hidden by
354 /// ADDIS_TLSGD_L_ADDR until after register assignment.
356
357 /// %x3 = GET_TLS_ADDR %x3, Symbol - For the general-dynamic TLS
358 /// model, produces a call to __tls_get_addr(sym\@tlsgd). Hidden by
359 /// ADDIS_TLSGD_L_ADDR until after register assignment.
361
362 /// %x3 = GET_TPOINTER - Used for the local- and initial-exec TLS model on
363 /// 32-bit AIX, produces a call to .__get_tpointer to retrieve the thread
364 /// pointer. At the end of the call, the thread pointer is found in R3.
366
367 /// G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that
368 /// combines ADDI_TLSGD_L and GET_TLS_ADDR until expansion following
369 /// register assignment.
371
372 /// GPRC = TLSGD_AIX, TOC_ENTRY, TOC_ENTRY
373 /// G8RC = TLSGD_AIX, TOC_ENTRY, TOC_ENTRY
374 /// Op that combines two register copies of TOC entries
375 /// (region handle into R3 and variable offset into R4) followed by a
376 /// GET_TLS_ADDR node which will be expanded to a call to .__tls_get_addr.
377 /// This node is used in 64-bit mode as well (in which case the result is
378 /// G8RC and inputs are X3/X4).
380
381 /// %x3 = GET_TLS_MOD_AIX _$TLSML - For the AIX local-dynamic TLS model,
382 /// produces a call to .__tls_get_mod(_$TLSML\@ml).
384
385 /// [GP|G8]RC = TLSLD_AIX, TOC_ENTRY(module handle)
386 /// Op that requires a single input of the module handle TOC entry in R3,
387 /// and generates a GET_TLS_MOD_AIX node which will be expanded into a call
388 /// to .__tls_get_mod. This node is used in both 32-bit and 64-bit modes.
389 /// The only difference is the register class.
391
392 /// G8RC = ADDIS_TLSLD_HA %x2, Symbol - For the local-dynamic TLS
393 /// model, produces an ADDIS8 instruction that adds the GOT base
394 /// register to sym\@got\@tlsld\@ha.
396
397 /// %x3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
398 /// model, produces an ADDI8 instruction that adds G8RReg to
399 /// sym\@got\@tlsld\@l and stores the result in X3. Hidden by
400 /// ADDIS_TLSLD_L_ADDR until after register assignment.
402
403 /// %x3 = GET_TLSLD_ADDR %x3, Symbol - For the local-dynamic TLS
404 /// model, produces a call to __tls_get_addr(sym\@tlsld). Hidden by
405 /// ADDIS_TLSLD_L_ADDR until after register assignment.
407
408 /// G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that
409 /// combines ADDI_TLSLD_L and GET_TLSLD_ADDR until expansion
410 /// following register assignment.
412
413 /// G8RC = ADDIS_DTPREL_HA %x3, Symbol - For the local-dynamic TLS
414 /// model, produces an ADDIS8 instruction that adds X3 to
415 /// sym\@dtprel\@ha.
417
418 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS
419 /// model, produces an ADDI8 instruction that adds G8RReg to
420 /// sym\@got\@dtprel\@l.
422
423 /// G8RC = PADDI_DTPREL %x3, Symbol - For the pc-rel based local-dynamic TLS
424 /// model, produces a PADDI8 instruction that adds X3 to sym\@dtprel.
426
427 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
428 /// during instruction selection to optimize a BUILD_VECTOR into
429 /// operations on splats. This is necessary to avoid losing these
430 /// optimizations due to constant folding.
432
433 /// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little
434 /// endian. Maps to an xxswapd instruction that corrects an lxvd2x
435 /// or stxvd2x instruction. The chain is necessary because the
436 /// sequence replaces a load and needs to provide the same number
437 /// of outputs.
439
440 /// An SDNode for swaps that are not associated with any loads/stores
441 /// and thereby have no chain.
443
444 /// FP_EXTEND_HALF(VECTOR, IDX) - Custom extend upper (IDX=0) half or
445 /// lower (IDX=1) half of v4f32 to v2f64.
447
448 /// MAT_PCREL_ADDR = Materialize a PC Relative address. This can be done
449 /// either through an add like PADDI or through a PC Relative load like
450 /// PLD.
452
453 /// TLS_DYNAMIC_MAT_PCREL_ADDR = Materialize a PC Relative address for
454 /// TLS global address when using dynamic access models. This can be done
455 /// through an add like PADDI.
457
458 /// TLS_LOCAL_EXEC_MAT_ADDR = Materialize an address for TLS global address
459 /// when using local exec access models, and when prefixed instructions are
460 /// available. This is used with ADD_TLS to produce an add like PADDI.
462
463 /// ACC_BUILD = Build an accumulator register from 4 VSX registers.
465
466 /// PAIR_BUILD = Build a vector pair register from 2 VSX registers.
468
469 /// EXTRACT_VSX_REG = Extract one of the underlying vsx registers of
470 /// an accumulator or pair register. This node is needed because
471 /// EXTRACT_SUBVECTOR expects the input and output vectors to have the same
472 /// element type.
474
475 /// XXMFACC = This corresponds to the xxmfacc instruction.
477
478 // Constrained conversion from floating point to int
484
485 /// Constrained integer-to-floating-point conversion instructions.
490
491 /// Constrained floating point add in round-to-zero mode.
494
495 /// SETBC - The ISA 3.1 (P10) SETBC instruction.
497
498 /// SETBCR - The ISA 3.1 (P10) SETBCR instruction.
500
501 /// VSRQ - The ISA 3.1 (P10) Vector Shift right quadword instruction
503
504 // NOTE: The nodes below may require PC-Rel specific patterns if the
505 // address could be PC-Relative. When adding new nodes below, consider
506 // whether or not the address can be PC-Relative and add the corresponding
507 // PC-relative patterns and tests.
508
509 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
510 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
511 /// the GPRC input, then stores it through Ptr. Type can be either i16 or
512 /// i32.
515
516 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
517 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
518 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
519 /// or i32.
521
522 /// STFIWX - The STFIWX instruction. The first operand is an input token
523 /// chain, then an f64 value to store, then an address to store it to.
525
526 /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point
527 /// load which sign-extends from a 32-bit integer value into the
528 /// destination 64-bit register.
530
531 /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point
532 /// load which zero-extends from a 32-bit integer value into the
533 /// destination 64-bit register.
535
536 /// GPRC, CHAIN = LXSIZX, CHAIN, Ptr, ByteWidth - This is a load of an
537 /// integer smaller than 64 bits into a VSR. The integer is zero-extended.
538 /// This can be used for converting loaded integers to floating point.
540
541 /// STXSIX - The STXSI[bh]X instruction. The first operand is an input
542 /// chain, then an f64 value to store, then an address to store it to,
543 /// followed by a byte-width for the store.
545
546 /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
547 /// Maps directly to an lxvd2x instruction that will be followed by
548 /// an xxswapd.
550
551 /// LXVRZX - Load VSX Vector Rightmost and Zero Extend
552 /// This node represents v1i128 BUILD_VECTOR of a zero extending load
553 /// instruction from <byte, halfword, word, or doubleword> to i128.
554 /// Allows utilization of the Load VSX Vector Rightmost Instructions.
556
557 /// VSRC, CHAIN = LOAD_VEC_BE CHAIN, Ptr - Occurs only for little endian.
558 /// Maps directly to one of lxvd2x/lxvw4x/lxvh8x/lxvb16x depending on
559 /// the vector type to load vector in big-endian element order.
561
562 /// VSRC, CHAIN = LD_VSX_LH CHAIN, Ptr - This is a floating-point load of a
563 /// v2f32 value into the lower half of a VSR register.
565
566 /// VSRC, CHAIN = LD_SPLAT, CHAIN, Ptr - a splatting load memory
567 /// instructions such as LXVDSX, LXVWSX.
569
570 /// VSRC, CHAIN = ZEXT_LD_SPLAT, CHAIN, Ptr - a splatting load memory
571 /// that zero-extends.
573
574 /// VSRC, CHAIN = SEXT_LD_SPLAT, CHAIN, Ptr - a splatting load memory
575 /// that sign-extends.
577
578 /// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
579 /// Maps directly to an stxvd2x instruction that will be preceded by
580 /// an xxswapd.
582
583 /// CHAIN = STORE_VEC_BE CHAIN, VSRC, Ptr - Occurs only for little endian.
584 /// Maps directly to one of stxvd2x/stxvw4x/stxvh8x/stxvb16x depending on
585 /// the vector type to store vector in big-endian element order.
587
588 /// Store scalar integers from VSR.
590
591 /// ATOMIC_CMP_SWAP - the exact same as the target-independent nodes
592 /// except they ensure that the compare input is zero-extended for
593 /// sub-word versions because the atomic loads zero-extend.
596
597 /// CHAIN,Glue = STORE_COND CHAIN, GPR, Ptr
598 /// The store conditional instruction ST[BHWD]ARX that produces a glue
599 /// result to attach it to a conditional branch.
601
602 /// GPRC = TOC_ENTRY GA, TOC
603 /// Loads the entry for GA from the TOC, where the TOC base is given by
604 /// the last operand.
607 };
608
609 } // end namespace PPCISD
610
611 /// Define some predicates that are used for node matching.
612 namespace PPC {
613
614 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
615 /// VPKUHUM instruction.
616 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
617 SelectionDAG &DAG);
618
619 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
620 /// VPKUWUM instruction.
621 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
622 SelectionDAG &DAG);
623
624 /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
625 /// VPKUDUM instruction.
626 bool isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
627 SelectionDAG &DAG);
628
629 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
630 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
631 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
632 unsigned ShuffleKind, SelectionDAG &DAG);
633
634 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
635 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
636 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
637 unsigned ShuffleKind, SelectionDAG &DAG);
638
639 /// isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for
640 /// a VMRGEW or VMRGOW instruction
641 bool isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
642 unsigned ShuffleKind, SelectionDAG &DAG);
643 /// isXXSLDWIShuffleMask - Return true if this is a shuffle mask suitable
644 /// for a XXSLDWI instruction.
645 bool isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
646 bool &Swap, bool IsLE);
647
648 /// isXXBRHShuffleMask - Return true if this is a shuffle mask suitable
649 /// for a XXBRH instruction.
650 bool isXXBRHShuffleMask(ShuffleVectorSDNode *N);
651
652 /// isXXBRWShuffleMask - Return true if this is a shuffle mask suitable
653 /// for a XXBRW instruction.
654 bool isXXBRWShuffleMask(ShuffleVectorSDNode *N);
655
656 /// isXXBRDShuffleMask - Return true if this is a shuffle mask suitable
657 /// for a XXBRD instruction.
658 bool isXXBRDShuffleMask(ShuffleVectorSDNode *N);
659
660 /// isXXBRQShuffleMask - Return true if this is a shuffle mask suitable
661 /// for a XXBRQ instruction.
662 bool isXXBRQShuffleMask(ShuffleVectorSDNode *N);
663
664 /// isXXPERMDIShuffleMask - Return true if this is a shuffle mask suitable
665 /// for a XXPERMDI instruction.
666 bool isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
667 bool &Swap, bool IsLE);
668
669 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the
670 /// shift amount, otherwise return -1.
671 int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
672 SelectionDAG &DAG);
673
674 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
675 /// specifies a splat of a single element that is suitable for input to
676 /// VSPLTB/VSPLTH/VSPLTW.
677 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
678
679 /// isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by
680 /// the XXINSERTW instruction introduced in ISA 3.0. This is essentially any
681 /// shuffle of v4f32/v4i32 vectors that just inserts one element from one
682 /// vector into the other. This function will also set a couple of
683 /// output parameters for how much the source vector needs to be shifted and
684 /// what byte number needs to be specified for the instruction to put the
685 /// element in the desired location of the target vector.
686 bool isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
687 unsigned &InsertAtByte, bool &Swap, bool IsLE);
688
689 /// getSplatIdxForPPCMnemonics - Return the splat index as a value that is
690 /// appropriate for PPC mnemonics (which have a big endian bias - namely
691 /// elements are counted from the left of the vector register).
692 unsigned getSplatIdxForPPCMnemonics(SDNode *N, unsigned EltSize,
693 SelectionDAG &DAG);
694
695 /// get_VSPLTI_elt - If this is a build_vector of constants which can be
696 /// formed by using a vspltis[bhw] instruction of the specified element
697 /// size, return the constant being splatted. The ByteSize field indicates
698 /// the number of bytes of each element [124] -> [bhw].
699 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
700
701 // Flags for computing the optimal addressing mode for loads and stores.
704
705 // Extension mode for integer loads.
707 MOF_ZExt = 1 << 1,
708 MOF_NoExt = 1 << 2,
709
710 // Address computation flags.
711 MOF_NotAddNorCst = 1 << 5, // Not const. or sum of ptr and scalar.
712 MOF_RPlusSImm16 = 1 << 6, // Reg plus signed 16-bit constant.
713 MOF_RPlusLo = 1 << 7, // Reg plus signed 16-bit relocation
714 MOF_RPlusSImm16Mult4 = 1 << 8, // Reg plus 16-bit signed multiple of 4.
715 MOF_RPlusSImm16Mult16 = 1 << 9, // Reg plus 16-bit signed multiple of 16.
716 MOF_RPlusSImm34 = 1 << 10, // Reg plus 34-bit signed constant.
717 MOF_RPlusR = 1 << 11, // Sum of two variables.
718 MOF_PCRel = 1 << 12, // PC-Relative relocation.
719 MOF_AddrIsSImm32 = 1 << 13, // A simple 32-bit constant.
720
721 // The in-memory type.
722 MOF_SubWordInt = 1 << 15,
723 MOF_WordInt = 1 << 16,
725 MOF_ScalarFloat = 1 << 18, // Scalar single or double precision.
726 MOF_Vector = 1 << 19, // Vector types and quad precision scalars.
727 MOF_Vector256 = 1 << 20,
728
729 // Subtarget features.
733 MOF_SubtargetSPE = 1 << 25
734 };
735
736 // The addressing modes for loads and stores.
737 enum AddrMode {
745 };
746 } // end namespace PPC
747
749 const PPCSubtarget &Subtarget;
750
751 public:
752 explicit PPCTargetLowering(const PPCTargetMachine &TM,
753 const PPCSubtarget &STI);
754
755 /// getTargetNodeName() - This method returns the name of a target specific
756 /// DAG node.
757 const char *getTargetNodeName(unsigned Opcode) const override;
758
759 bool isSelectSupported(SelectSupportKind Kind) const override {
760 // PowerPC does not support scalar condition selects on vectors.
762 }
763
764 /// getPreferredVectorAction - The code we generate when vector types are
765 /// legalized by promoting the integer element type is often much worse
766 /// than code we generate if we widen the type for applicable vector types.
767 /// The issue with promoting is that the vector is scalaraized, individual
768 /// elements promoted and then the vector is rebuilt. So say we load a pair
769 /// of v4i8's and shuffle them. This will turn into a mess of 8 extending
770 /// loads, moves back into VSR's (or memory ops if we don't have moves) and
771 /// then the VPERM for the shuffle. All in all a very slow sequence.
773 const override {
774 // Default handling for scalable and single-element vectors.
775 if (VT.isScalableVector() || VT.getVectorNumElements() == 1)
777
778 // Split and promote vNi1 vectors so we don't produce v256i1/v512i1
779 // types as those are only for MMA instructions.
780 if (VT.getScalarSizeInBits() == 1 && VT.getSizeInBits() > 16)
781 return TypeSplitVector;
782 if (VT.getScalarSizeInBits() == 1)
783 return TypePromoteInteger;
784
785 // Widen vectors that have reasonably sized elements.
786 if (VT.getScalarSizeInBits() % 8 == 0)
787 return TypeWidenVector;
789 }
790
791 bool useSoftFloat() const override;
792
793 bool hasSPE() const;
794
795 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
796 return MVT::i32;
797 }
798
799 bool isCheapToSpeculateCttz(Type *Ty) const override {
800 return true;
801 }
802
803 bool isCheapToSpeculateCtlz(Type *Ty) const override {
804 return true;
805 }
806
807 bool
809 unsigned ElemSizeInBits,
810 unsigned &Index) const override;
811
812 bool isCtlzFast() const override {
813 return true;
814 }
815
816 bool isEqualityCmpFoldedWithSignedCmp() const override {
817 return false;
818 }
819
820 bool hasAndNotCompare(SDValue) const override {
821 return true;
822 }
823
824 bool preferIncOfAddToSubOfNot(EVT VT) const override;
825
826 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
827 return VT.isScalarInteger();
828 }
829
831 bool OptForSize, NegatibleCost &Cost,
832 unsigned Depth = 0) const override;
833
834 /// getSetCCResultType - Return the ISD::SETCC ValueType
836 EVT VT) const override;
837
838 /// Return true if target always benefits from combining into FMA for a
839 /// given value type. This must typically return false on targets where FMA
840 /// takes more cycles to execute than FADD.
841 bool enableAggressiveFMAFusion(EVT VT) const override;
842
843 /// getPreIndexedAddressParts - returns true by value, base pointer and
844 /// offset pointer and addressing mode by reference if the node's address
845 /// can be legally represented as pre-indexed load / store address.
849 SelectionDAG &DAG) const override;
850
851 /// SelectAddressEVXRegReg - Given the specified addressed, check to see if
852 /// it can be more efficiently represented as [r+imm].
854 SelectionDAG &DAG) const;
855
856 /// SelectAddressRegReg - Given the specified addressed, check to see if it
857 /// can be more efficiently represented as [r+imm]. If \p EncodingAlignment
858 /// is non-zero, only accept displacement which is not suitable for [r+imm].
859 /// Returns false if it can be represented by [r+imm], which are preferred.
861 SelectionDAG &DAG,
862 MaybeAlign EncodingAlignment = std::nullopt) const;
863
864 /// SelectAddressRegImm - Returns true if the address N can be represented
865 /// by a base register plus a signed 16-bit displacement [r+imm], and if it
866 /// is not better represented as reg+reg. If \p EncodingAlignment is
867 /// non-zero, only accept displacements suitable for instruction encoding
868 /// requirement, i.e. multiples of 4 for DS form.
870 SelectionDAG &DAG,
871 MaybeAlign EncodingAlignment) const;
873 SelectionDAG &DAG) const;
874
875 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
876 /// represented as an indexed [r+r] operation.
878 SelectionDAG &DAG) const;
879
880 /// SelectAddressPCRel - Represent the specified address as pc relative to
881 /// be represented as [pc+imm]
883
885
886 /// LowerOperation - Provide custom lowering hooks for some operations.
887 ///
888 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
889
890 /// ReplaceNodeResults - Replace the results of node with an illegal result
891 /// type with new values built out of custom code.
892 ///
894 SelectionDAG &DAG) const override;
895
896 SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const;
897 SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const;
898
899 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
900
901 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
902 SmallVectorImpl<SDNode *> &Created) const override;
903
904 Register getRegisterByName(const char* RegName, LLT VT,
905 const MachineFunction &MF) const override;
906
908 KnownBits &Known,
909 const APInt &DemandedElts,
910 const SelectionDAG &DAG,
911 unsigned Depth = 0) const override;
912
913 Align getPrefLoopAlignment(MachineLoop *ML) const override;
914
915 bool shouldInsertFencesForAtomic(const Instruction *I) const override {
916 return true;
917 }
918
919 Value *emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr,
920 AtomicOrdering Ord) const override;
921
923 AtomicOrdering Ord) const override;
924
926 AtomicOrdering Ord) const override;
928 AtomicOrdering Ord) const override;
929
930 bool shouldInlineQuadwordAtomics() const;
931
933 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
934
937
939 AtomicRMWInst *AI, Value *AlignedAddr,
940 Value *Incr, Value *Mask,
941 Value *ShiftAmt,
942 AtomicOrdering Ord) const override;
945 Value *AlignedAddr, Value *CmpVal,
946 Value *NewVal, Value *Mask,
947 AtomicOrdering Ord) const override;
948
951 MachineBasicBlock *MBB) const override;
954 unsigned AtomicSize,
955 unsigned BinOpcode,
956 unsigned CmpOpcode = 0,
957 unsigned CmpPred = 0) const;
960 bool is8bit,
961 unsigned Opcode,
962 unsigned CmpOpcode = 0,
963 unsigned CmpPred = 0) const;
964
966 MachineBasicBlock *MBB) const;
967
969 MachineBasicBlock *MBB) const;
970
972 MachineBasicBlock *MBB) const;
973
974 bool hasInlineStackProbe(const MachineFunction &MF) const override;
975
976 unsigned getStackProbeSize(const MachineFunction &MF) const;
977
978 ConstraintType getConstraintType(StringRef Constraint) const override;
979
980 /// Examine constraint string and operand type and determine a weight value.
981 /// The operand object must already have been set up with the operand type.
983 AsmOperandInfo &info, const char *constraint) const override;
984
985 std::pair<unsigned, const TargetRegisterClass *>
987 StringRef Constraint, MVT VT) const override;
988
989 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
990 /// function arguments in the caller parameter area.
991 Align getByValTypeAlignment(Type *Ty, const DataLayout &DL) const override;
992
993 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
994 /// vector. If it is invalid, don't add anything to Ops.
996 std::vector<SDValue> &Ops,
997 SelectionDAG &DAG) const override;
998
1000 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
1001 if (ConstraintCode == "es")
1003 else if (ConstraintCode == "Q")
1005 else if (ConstraintCode == "Z")
1007 else if (ConstraintCode == "Zy")
1009 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
1010 }
1011
1014 SelectionDAG &DAG) const override;
1015
1016 /// isLegalAddressingMode - Return true if the addressing mode represented
1017 /// by AM is legal for this target, for a load/store of the specified type.
1018 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
1019 Type *Ty, unsigned AS,
1020 Instruction *I = nullptr) const override;
1021
1022 /// isLegalICmpImmediate - Return true if the specified immediate is legal
1023 /// icmp immediate, that is the target has icmp instructions which can
1024 /// compare a register against the immediate without having to materialize
1025 /// the immediate into a register.
1026 bool isLegalICmpImmediate(int64_t Imm) const override;
1027
1028 /// isLegalAddImmediate - Return true if the specified immediate is legal
1029 /// add immediate, that is the target has add instructions which can
1030 /// add a register and the immediate without having to materialize
1031 /// the immediate into a register.
1032 bool isLegalAddImmediate(int64_t Imm) const override;
1033
1034 /// isTruncateFree - Return true if it's free to truncate a value of
1035 /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in
1036 /// register X1 to i32 by referencing its sub-register R1.
1037 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
1038 bool isTruncateFree(EVT VT1, EVT VT2) const override;
1039
1040 bool isZExtFree(SDValue Val, EVT VT2) const override;
1041
1042 bool isFPExtFree(EVT DestVT, EVT SrcVT) const override;
1043
1044 /// Returns true if it is beneficial to convert a load of a constant
1045 /// to just the constant itself.
1047 Type *Ty) const override;
1048
1049 bool convertSelectOfConstantsToMath(EVT VT) const override {
1050 return true;
1051 }
1052
1053 bool decomposeMulByConstant(LLVMContext &Context, EVT VT,
1054 SDValue C) const override;
1055
1057 EVT VT) const override {
1058 // Only handle float load/store pair because float(fpr) load/store
1059 // instruction has more cycles than integer(gpr) load/store in PPC.
1060 if (Opc != ISD::LOAD && Opc != ISD::STORE)
1061 return false;
1062 if (VT != MVT::f32 && VT != MVT::f64)
1063 return false;
1064
1065 return true;
1066 }
1067
1068 // Returns true if the address of the global is stored in TOC entry.
1069 bool isAccessedAsGotIndirect(SDValue N) const;
1070
1071 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
1072
1073 bool getTgtMemIntrinsic(IntrinsicInfo &Info,
1074 const CallInst &I,
1075 MachineFunction &MF,
1076 unsigned Intrinsic) const override;
1077
1078 /// It returns EVT::Other if the type should be determined using generic
1079 /// target-independent logic.
1080 EVT getOptimalMemOpType(LLVMContext &Context, const MemOp &Op,
1081 const AttributeList &FuncAttributes) const override;
1082
1083 /// Is unaligned memory access allowed for the given type, and is it fast
1084 /// relative to software emulation.
1086 EVT VT, unsigned AddrSpace, Align Alignment = Align(1),
1088 unsigned *Fast = nullptr) const override;
1089
1090 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
1091 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
1092 /// expanded to FMAs when this method returns true, otherwise fmuladd is
1093 /// expanded to fmul + fadd.
1095 EVT VT) const override;
1096
1097 bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *Ty) const override;
1098
1099 /// isProfitableToHoist - Check if it is profitable to hoist instruction
1100 /// \p I to its dominator block.
1101 /// For example, it is not profitable if \p I and it's only user can form a
1102 /// FMA instruction, because Powerpc prefers FMADD.
1103 bool isProfitableToHoist(Instruction *I) const override;
1104
1105 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
1106
1107 // Should we expand the build vector with shuffles?
1108 bool
1110 unsigned DefinedValues) const override;
1111
1112 // Keep the zero-extensions for arguments to libcalls.
1113 bool shouldKeepZExtForFP16Conv() const override { return true; }
1114
1115 /// createFastISel - This method returns a target-specific FastISel object,
1116 /// or null if the target does not support "fast" instruction selection.
1118 const TargetLibraryInfo *LibInfo) const override;
1119
1120 /// Returns true if an argument of type Ty needs to be passed in a
1121 /// contiguous block of registers in calling convention CallConv.
1123 Type *Ty, CallingConv::ID CallConv, bool isVarArg,
1124 const DataLayout &DL) const override {
1125 // We support any array type as "consecutive" block in the parameter
1126 // save area. The element type defines the alignment requirement and
1127 // whether the argument should go in GPRs, FPRs, or VRs if available.
1128 //
1129 // Note that clang uses this capability both to implement the ELFv2
1130 // homogeneous float/vector aggregate ABI, and to avoid having to use
1131 // "byval" when passing aggregates that might fully fit in registers.
1132 return Ty->isArrayTy();
1133 }
1134
1135 /// If a physical register, this returns the register that receives the
1136 /// exception address on entry to an EH pad.
1137 Register
1138 getExceptionPointerRegister(const Constant *PersonalityFn) const override;
1139
1140 /// If a physical register, this returns the register that receives the
1141 /// exception typeid on entry to a landing pad.
1142 Register
1143 getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
1144
1145 /// Override to support customized stack guard loading.
1146 bool useLoadStackGuardNode(const Module &M) const override;
1147
1148 bool isFPImmLegal(const APFloat &Imm, EVT VT,
1149 bool ForCodeSize) const override;
1150
1151 unsigned getJumpTableEncoding() const override;
1152 bool isJumpTableRelative() const override;
1154 SelectionDAG &DAG) const override;
1156 unsigned JTI,
1157 MCContext &Ctx) const override;
1158
1159 /// SelectOptimalAddrMode - Based on a node N and it's Parent (a MemSDNode),
1160 /// compute the address flags of the node, get the optimal address mode
1161 /// based on the flags, and set the Base and Disp based on the address mode.
1163 SDValue &Disp, SDValue &Base,
1164 SelectionDAG &DAG,
1165 MaybeAlign Align) const;
1166 /// SelectForceXFormMode - Given the specified address, force it to be
1167 /// represented as an indexed [r+r] operation (an XForm instruction).
1169 SelectionDAG &DAG) const;
1170
1172 SelectionDAG & DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
1173 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
1174 const override;
1175 /// Structure that collects some common arguments that get passed around
1176 /// between the functions for call lowering.
1177 struct CallFlags {
1179 const bool IsTailCall : 1;
1180 const bool IsVarArg : 1;
1181 const bool IsPatchPoint : 1;
1182 const bool IsIndirect : 1;
1183 const bool HasNest : 1;
1184 const bool NoMerge : 1;
1185
1187 bool IsPatchPoint, bool IsIndirect, bool HasNest, bool NoMerge)
1191 };
1192
1194 bool IsVarArg) const;
1195 bool supportsTailCallFor(const CallBase *CB) const;
1196
1197 bool hasMultipleConditionRegisters(EVT VT) const override;
1198
1199 private:
1200 struct ReuseLoadInfo {
1201 SDValue Ptr;
1202 SDValue Chain;
1203 SDValue ResChain;
1205 bool IsDereferenceable = false;
1206 bool IsInvariant = false;
1207 Align Alignment;
1208 AAMDNodes AAInfo;
1209 const MDNode *Ranges = nullptr;
1210
1211 ReuseLoadInfo() = default;
1212
1213 MachineMemOperand::Flags MMOFlags() const {
1215 if (IsDereferenceable)
1217 if (IsInvariant)
1219 return F;
1220 }
1221 };
1222
1223 // Map that relates a set of common address flags to PPC addressing modes.
1224 std::map<PPC::AddrMode, SmallVector<unsigned, 16>> AddrModesMap;
1225 void initializeAddrModeMap();
1226
1227 bool canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI,
1228 SelectionDAG &DAG,
1230
1231 void LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
1232 SelectionDAG &DAG, const SDLoc &dl) const;
1233 SDValue LowerFP_TO_INTDirectMove(SDValue Op, SelectionDAG &DAG,
1234 const SDLoc &dl) const;
1235
1236 bool directMoveIsProfitable(const SDValue &Op) const;
1237 SDValue LowerINT_TO_FPDirectMove(SDValue Op, SelectionDAG &DAG,
1238 const SDLoc &dl) const;
1239
1240 SDValue LowerINT_TO_FPVector(SDValue Op, SelectionDAG &DAG,
1241 const SDLoc &dl) const;
1242
1243 SDValue LowerTRUNCATEVector(SDValue Op, SelectionDAG &DAG) const;
1244
1245 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
1246 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
1247
1248 bool IsEligibleForTailCallOptimization(
1249 const GlobalValue *CalleeGV, CallingConv::ID CalleeCC,
1250 CallingConv::ID CallerCC, bool isVarArg,
1251 const SmallVectorImpl<ISD::InputArg> &Ins) const;
1252
1253 bool IsEligibleForTailCallOptimization_64SVR4(
1254 const GlobalValue *CalleeGV, CallingConv::ID CalleeCC,
1255 CallingConv::ID CallerCC, const CallBase *CB, bool isVarArg,
1256 const SmallVectorImpl<ISD::OutputArg> &Outs,
1257 const SmallVectorImpl<ISD::InputArg> &Ins, const Function *CallerFunc,
1258 bool isCalleeExternalSymbol) const;
1259
1260 bool isEligibleForTCO(const GlobalValue *CalleeGV, CallingConv::ID CalleeCC,
1261 CallingConv::ID CallerCC, const CallBase *CB,
1262 bool isVarArg,
1263 const SmallVectorImpl<ISD::OutputArg> &Outs,
1264 const SmallVectorImpl<ISD::InputArg> &Ins,
1265 const Function *CallerFunc,
1266 bool isCalleeExternalSymbol) const;
1267
1268 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG &DAG, int SPDiff,
1269 SDValue Chain, SDValue &LROpOut,
1270 SDValue &FPOpOut,
1271 const SDLoc &dl) const;
1272
1273 SDValue getTOCEntry(SelectionDAG &DAG, const SDLoc &dl, SDValue GA) const;
1274
1275 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
1276 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
1277 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
1278 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
1279 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
1280 SDValue LowerGlobalTLSAddressAIX(SDValue Op, SelectionDAG &DAG) const;
1281 SDValue LowerGlobalTLSAddressLinux(SDValue Op, SelectionDAG &DAG) const;
1282 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
1283 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
1284 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
1285 SDValue LowerSSUBO(SDValue Op, SelectionDAG &DAG) const;
1286 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
1287 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
1288 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
1289 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
1290 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
1291 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
1292 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
1293 SDValue LowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const;
1294 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
1295 SDValue LowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
1296 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
1297 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
1298 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
1299 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
1300 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
1301 const SDLoc &dl) const;
1302 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1303 SDValue LowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
1304 SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
1305 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
1306 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
1307 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
1308 SDValue LowerFunnelShift(SDValue Op, SelectionDAG &DAG) const;
1309 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1310 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
1311 SDValue LowerVPERM(SDValue Op, SelectionDAG &DAG, ArrayRef<int> PermMask,
1312 EVT VT, SDValue V1, SDValue V2) const;
1313 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
1314 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
1315 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
1316 SDValue LowerBSWAP(SDValue Op, SelectionDAG &DAG) const;
1317 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
1318 SDValue LowerIS_FPCLASS(SDValue Op, SelectionDAG &DAG) const;
1319 SDValue LowerADDSUBO_CARRY(SDValue Op, SelectionDAG &DAG) const;
1320 SDValue LowerADDSUBO(SDValue Op, SelectionDAG &DAG) const;
1321 SDValue lowerToLibCall(const char *LibCallName, SDValue Op,
1322 SelectionDAG &DAG) const;
1323 SDValue lowerLibCallBasedOnType(const char *LibCallFloatName,
1324 const char *LibCallDoubleName, SDValue Op,
1325 SelectionDAG &DAG) const;
1326 bool isLowringToMASSFiniteSafe(SDValue Op) const;
1327 bool isLowringToMASSSafe(SDValue Op) const;
1328 bool isScalarMASSConversionEnabled() const;
1329 SDValue lowerLibCallBase(const char *LibCallDoubleName,
1330 const char *LibCallFloatName,
1331 const char *LibCallDoubleNameFinite,
1332 const char *LibCallFloatNameFinite, SDValue Op,
1333 SelectionDAG &DAG) const;
1334 SDValue lowerPow(SDValue Op, SelectionDAG &DAG) const;
1335 SDValue lowerSin(SDValue Op, SelectionDAG &DAG) const;
1336 SDValue lowerCos(SDValue Op, SelectionDAG &DAG) const;
1337 SDValue lowerLog(SDValue Op, SelectionDAG &DAG) const;
1338 SDValue lowerLog10(SDValue Op, SelectionDAG &DAG) const;
1339 SDValue lowerExp(SDValue Op, SelectionDAG &DAG) const;
1340 SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) const;
1341 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1342 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
1343 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
1344 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
1345 SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const;
1346
1347 SDValue LowerVectorLoad(SDValue Op, SelectionDAG &DAG) const;
1348 SDValue LowerVectorStore(SDValue Op, SelectionDAG &DAG) const;
1349 SDValue LowerDMFVectorLoad(SDValue Op, SelectionDAG &DAG) const;
1350 SDValue LowerDMFVectorStore(SDValue Op, SelectionDAG &DAG) const;
1351 SDValue DMFInsert1024(const SmallVectorImpl<SDValue> &Pairs,
1352 const SDLoc &dl, SelectionDAG &DAG) const;
1353
1354 SDValue LowerCallResult(SDValue Chain, SDValue InGlue,
1355 CallingConv::ID CallConv, bool isVarArg,
1356 const SmallVectorImpl<ISD::InputArg> &Ins,
1357 const SDLoc &dl, SelectionDAG &DAG,
1358 SmallVectorImpl<SDValue> &InVals) const;
1359
1360 SDValue FinishCall(CallFlags CFlags, const SDLoc &dl, SelectionDAG &DAG,
1361 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
1362 SDValue InGlue, SDValue Chain, SDValue CallSeqStart,
1363 SDValue &Callee, int SPDiff, unsigned NumBytes,
1364 const SmallVectorImpl<ISD::InputArg> &Ins,
1365 SmallVectorImpl<SDValue> &InVals,
1366 const CallBase *CB) const;
1367
1368 SDValue
1369 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1370 const SmallVectorImpl<ISD::InputArg> &Ins,
1371 const SDLoc &dl, SelectionDAG &DAG,
1372 SmallVectorImpl<SDValue> &InVals) const override;
1373
1374 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
1375 SmallVectorImpl<SDValue> &InVals) const override;
1376
1377 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
1378 bool isVarArg,
1379 const SmallVectorImpl<ISD::OutputArg> &Outs,
1380 LLVMContext &Context, const Type *RetTy) const override;
1381
1382 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1383 const SmallVectorImpl<ISD::OutputArg> &Outs,
1384 const SmallVectorImpl<SDValue> &OutVals,
1385 const SDLoc &dl, SelectionDAG &DAG) const override;
1386
1387 SDValue extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
1388 SelectionDAG &DAG, SDValue ArgVal,
1389 const SDLoc &dl) const;
1390
1391 SDValue LowerFormalArguments_AIX(
1392 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1393 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1394 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
1395 SDValue LowerFormalArguments_64SVR4(
1396 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1397 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1398 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
1399 SDValue LowerFormalArguments_32SVR4(
1400 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1401 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1402 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
1403
1404 SDValue createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
1405 SDValue CallSeqStart,
1406 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1407 const SDLoc &dl) const;
1408
1409 SDValue LowerCall_64SVR4(SDValue Chain, SDValue Callee, CallFlags CFlags,
1410 const SmallVectorImpl<ISD::OutputArg> &Outs,
1411 const SmallVectorImpl<SDValue> &OutVals,
1412 const SmallVectorImpl<ISD::InputArg> &Ins,
1413 const SDLoc &dl, SelectionDAG &DAG,
1414 SmallVectorImpl<SDValue> &InVals,
1415 const CallBase *CB) const;
1416 SDValue LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallFlags CFlags,
1417 const SmallVectorImpl<ISD::OutputArg> &Outs,
1418 const SmallVectorImpl<SDValue> &OutVals,
1419 const SmallVectorImpl<ISD::InputArg> &Ins,
1420 const SDLoc &dl, SelectionDAG &DAG,
1421 SmallVectorImpl<SDValue> &InVals,
1422 const CallBase *CB) const;
1423 SDValue LowerCall_AIX(SDValue Chain, SDValue Callee, CallFlags CFlags,
1424 const SmallVectorImpl<ISD::OutputArg> &Outs,
1425 const SmallVectorImpl<SDValue> &OutVals,
1426 const SmallVectorImpl<ISD::InputArg> &Ins,
1427 const SDLoc &dl, SelectionDAG &DAG,
1428 SmallVectorImpl<SDValue> &InVals,
1429 const CallBase *CB) const;
1430
1431 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
1432 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
1433 SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
1434
1435 SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const;
1436 SDValue DAGCombineBuildVector(SDNode *N, DAGCombinerInfo &DCI) const;
1437 SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const;
1438 SDValue combineStoreFPToInt(SDNode *N, DAGCombinerInfo &DCI) const;
1439 SDValue combineFPToIntToFP(SDNode *N, DAGCombinerInfo &DCI) const;
1440 SDValue combineSHL(SDNode *N, DAGCombinerInfo &DCI) const;
1441 SDValue combineVectorShift(SDNode *N, DAGCombinerInfo &DCI) const;
1442 SDValue combineSRA(SDNode *N, DAGCombinerInfo &DCI) const;
1443 SDValue combineSRL(SDNode *N, DAGCombinerInfo &DCI) const;
1444 SDValue combineMUL(SDNode *N, DAGCombinerInfo &DCI) const;
1445 SDValue combineADD(SDNode *N, DAGCombinerInfo &DCI) const;
1446 SDValue combineFMALike(SDNode *N, DAGCombinerInfo &DCI) const;
1447 SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const;
1448 SDValue combineSetCC(SDNode *N, DAGCombinerInfo &DCI) const;
1449 SDValue combineVectorShuffle(ShuffleVectorSDNode *SVN,
1450 SelectionDAG &DAG) const;
1451 SDValue combineVReverseMemOP(ShuffleVectorSDNode *SVN, LSBaseSDNode *LSBase,
1452 DAGCombinerInfo &DCI) const;
1453
1454 /// ConvertSETCCToSubtract - looks at SETCC that compares ints. It replaces
1455 /// SETCC with integer subtraction when (1) there is a legal way of doing it
1456 /// (2) keeping the result of comparison in GPR has performance benefit.
1457 SDValue ConvertSETCCToSubtract(SDNode *N, DAGCombinerInfo &DCI) const;
1458
1459 SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1460 int &RefinementSteps, bool &UseOneConstNR,
1461 bool Reciprocal) const override;
1462 SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1463 int &RefinementSteps) const override;
1464 SDValue getSqrtInputTest(SDValue Operand, SelectionDAG &DAG,
1465 const DenormalMode &Mode) const override;
1466 SDValue getSqrtResultForDenormInput(SDValue Operand,
1467 SelectionDAG &DAG) const override;
1468 unsigned combineRepeatedFPDivisors() const override;
1469
1470 SDValue
1471 combineElementTruncationToVectorTruncation(SDNode *N,
1472 DAGCombinerInfo &DCI) const;
1473
1474 /// lowerToVINSERTH - Return the SDValue if this VECTOR_SHUFFLE can be
1475 /// handled by the VINSERTH instruction introduced in ISA 3.0. This is
1476 /// essentially any shuffle of v8i16 vectors that just inserts one element
1477 /// from one vector into the other.
1478 SDValue lowerToVINSERTH(ShuffleVectorSDNode *N, SelectionDAG &DAG) const;
1479
1480 /// lowerToVINSERTB - Return the SDValue if this VECTOR_SHUFFLE can be
1481 /// handled by the VINSERTB instruction introduced in ISA 3.0. This is
1482 /// essentially v16i8 vector version of VINSERTH.
1483 SDValue lowerToVINSERTB(ShuffleVectorSDNode *N, SelectionDAG &DAG) const;
1484
1485 /// lowerToXXSPLTI32DX - Return the SDValue if this VECTOR_SHUFFLE can be
1486 /// handled by the XXSPLTI32DX instruction introduced in ISA 3.1.
1487 SDValue lowerToXXSPLTI32DX(ShuffleVectorSDNode *N, SelectionDAG &DAG) const;
1488
1489 // Return whether the call instruction can potentially be optimized to a
1490 // tail call. This will cause the optimizers to attempt to move, or
1491 // duplicate return instructions to help enable tail call optimizations.
1492 bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
1493 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
1494
1495 /// getAddrModeForFlags - Based on the set of address flags, select the most
1496 /// optimal instruction format to match by.
1497 PPC::AddrMode getAddrModeForFlags(unsigned Flags) const;
1498
1499 /// computeMOFlags - Given a node N and it's Parent (a MemSDNode), compute
1500 /// the address flags of the load/store instruction that is to be matched.
1501 /// The address flags are stored in a map, which is then searched
1502 /// through to determine the optimal load/store instruction format.
1503 unsigned computeMOFlags(const SDNode *Parent, SDValue N,
1504 SelectionDAG &DAG) const;
1505 }; // end class PPCTargetLowering
1506
1507 namespace PPC {
1508
1509 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
1510 const TargetLibraryInfo *LibInfo);
1511
1512 } // end namespace PPC
1513
1514 bool isIntS16Immediate(SDNode *N, int16_t &Imm);
1515 bool isIntS16Immediate(SDValue Op, int16_t &Imm);
1516 bool isIntS34Immediate(SDNode *N, int64_t &Imm);
1517 bool isIntS34Immediate(SDValue Op, int64_t &Imm);
1518
1519 bool convertToNonDenormSingle(APInt &ArgAPInt);
1520 bool convertToNonDenormSingle(APFloat &ArgAPFloat);
1521 bool checkConvertToNonDenormSingle(APFloat &ArgAPFloat);
1522
1523} // end namespace llvm
1524
1525#endif // LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Function Alias Analysis Results
This file contains the simple types necessary to represent the attributes associated with functions a...
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
return RetTy
uint64_t Addr
uint32_t Index
IRTranslator LLVM IR MI
#define RegName(no)
lazy value info
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
Register const TargetRegisterInfo * TRI
This file contains the declarations for metadata subclasses.
static cl::opt< RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Development, "development", "for training")))
This file describes how to lower LLVM code to machine code.
Class for arbitrary precision integers.
Definition: APInt.h:78
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:506
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:709
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1116
This class represents a function call, abstracting a target machine's calling convention.
This is an important base class in LLVM.
Definition: Constant.h:43
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:63
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:66
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:114
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
Context object for machine code objects.
Definition: MCContext.h:83
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:34
Metadata node.
Definition: Metadata.h:1077
Machine Value Type.
uint64_t getScalarSizeInBits() const
unsigned getVectorNumElements() const
bool isScalableVector() const
Return true if this is a vector value type where the runtime length is machine dependent.
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
Representation of each machine instruction.
Definition: MachineInstr.h:72
Flags
Flags values. These may be or'd together.
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
@ MOInvariant
The memory access always returns the same value (or traps).
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:67
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
MachineBasicBlock * emitEHSjLjLongJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
CCAssignFn * ccAssignFnForCall(CallingConv::ID CC, bool Return, bool IsVarArg) const
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
isTruncateFree - Return true if it's free to truncate a value of type Ty1 to type Ty2.
Value * emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const override
Perform a masked atomicrmw using a target-specific intrinsic.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
bool isFPExtFree(EVT DestVT, EVT SrcVT) const override
Return true if an fpext operation is free (for instance, because single-precision floating-point numb...
PPC::AddrMode SelectForceXFormMode(SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG) const
SelectForceXFormMode - Given the specified address, force it to be represented as an indexed [r+r] op...
Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
bool hasInlineStackProbe(const MachineFunction &MF) const override
MachineBasicBlock * emitEHSjLjSetJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
bool isCheapToSpeculateCtlz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName() - This method returns the name of a target specific DAG node.
bool supportsTailCallFor(const CallBase *CB) const
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
MachineBasicBlock * emitProbedAlloca(MachineInstr &MI, MachineBasicBlock *MBB) const
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
MachineBasicBlock * EmitPartwordAtomicBinary(MachineInstr &MI, MachineBasicBlock *MBB, bool is8bit, unsigned Opcode, unsigned CmpOpcode=0, unsigned CmpPred=0) const
SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, NegatibleCost &Cost, unsigned Depth=0) const override
Return the newly negated expression if the cost is not expensive and set the cost in Cost to indicate...
bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG, MaybeAlign EncodingAlignment) const
SelectAddressRegImm - Returns true if the address N can be represented by a base register plus a sign...
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.
bool isCtlzFast() const override
Return true if ctlz instruction is fast.
bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) const override
Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calli...
bool isSelectSupported(SelectSupportKind Kind) const override
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const
bool isCheapToSpeculateCttz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, std::optional< CallingConv::ID > CC) const override
Target-specific splitting of values into parts that fit a register storing a legal type.
void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector.
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...
bool hasMultipleConditionRegisters(EVT VT) const override
Does the target have multiple (allocatable) condition registers that can be used to store the results...
TargetLowering::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Align getByValTypeAlignment(Type *Ty, const DataLayout &DL) const override
getByValTypeAlignment - Return the desired alignment for ByVal aggregate function arguments in the ca...
bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG, MaybeAlign EncodingAlignment=std::nullopt) const
SelectAddressRegReg - Given the specified addressed, check to see if it can be more efficiently repre...
MachineBasicBlock * EmitAtomicBinary(MachineInstr &MI, MachineBasicBlock *MBB, unsigned AtomicSize, unsigned BinOpcode, unsigned CmpOpcode=0, unsigned CmpPred=0) const
bool hasAndNotCompare(SDValue) const override
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) !...
SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl< SDNode * > &Created) const override
Targets may override this function to provide custom SDIV lowering for power-of-2 denominators.
Value * emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override
Perform a store-conditional operation to Addr.
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG) const
SelectAddressRegRegOnly - Given the specified addressed, force it to be represented as an indexed [r+...
bool useSoftFloat() const override
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
Value * emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const override
Perform a masked cmpxchg using a target-specific intrinsic.
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
bool enableAggressiveFMAFusion(EVT VT) const override
Return true if target always benefits from combining into FMA for a given value type.
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
bool decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const override
Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...
InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const override
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
bool preferIncOfAddToSubOfNot(EVT VT) const override
These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR...
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Returns true if it is beneficial to convert a load of a constant to just the constant itself.
const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const override
Returns a 0 terminated array of registers that can be safely used as scratch registers.
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
getPreIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mod...
bool isProfitableToHoist(Instruction *I) const override
isProfitableToHoist - Check if it is profitable to hoist instruction I to its dominator block.
bool convertSelectOfConstantsToMath(EVT VT) const override
Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops...
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
Value * emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, AtomicOrdering Ord) const override
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint, return the type of constraint it is for this target.
const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const override
This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase,...
bool shallExtractConstSplatVectorElementToStore(Type *VectorTy, unsigned ElemSizeInBits, unsigned &Index) const override
Return true if the target shall perform extract vector element and store given that the vector is kno...
bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override
Return true if it is profitable for dag combiner to transform a floating point op of specified opcode...
bool isEqualityCmpFoldedWithSignedCmp() const override
Return true if instruction generated for equality comparison is folded with instruction generated for...
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
getPreferredVectorAction - The code we generate when vector types are legalized by promoting the inte...
EVT getOptimalMemOpType(LLVMContext &Context, const MemOp &Op, const AttributeList &FuncAttributes) const override
It returns EVT::Other if the type should be determined using generic target-independent logic.
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const
void CollectTargetIntrinsicOperands(const CallInst &I, SmallVectorImpl< SDValue > &Ops, SelectionDAG &DAG) const override
unsigned getStackProbeSize(const MachineFunction &MF) const
TargetLowering::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
bool useLoadStackGuardNode(const Module &M) const override
Override to support customized stack guard loading.
bool shouldKeepZExtForFP16Conv() const override
Does this target require the clearing of high-order bits in a register passed to the fp16 to fp conve...
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster than a pair of fmul and fadd i...
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const override
Is unaligned memory access allowed for the given type, and is it fast relative to software emulation.
bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override
bool SelectAddressRegImm34(SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG) const
Similar to the 16-bit case but for instructions that take a 34-bit displacement field (prefixed loads...
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
bool isJumpTableRelative() const override
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
PPC::AddrMode SelectOptimalAddrMode(const SDNode *Parent, SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG, MaybeAlign Align) const
SelectOptimalAddrMode - Based on a node N and it's Parent (a MemSDNode), compute the address flags of...
bool SelectAddressPCRel(SDValue N, SDValue &Base) const
SelectAddressPCRel - Represent the specified address as pc relative to be represented as [pc+imm].
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the ISD::SETCC ValueType
bool SelectAddressEVXRegReg(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG) const
SelectAddressEVXRegReg - Given the specified addressed, check to see if it can be more efficiently re...
bool isLegalICmpImmediate(int64_t Imm) const override
isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate,...
bool isAccessedAsGotIndirect(SDValue N) const
Align getPrefLoopAlignment(MachineLoop *ML) const override
Return the preferred loop alignment.
FastISel * createFastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo) const override
createFastISel - This method returns a target-specific FastISel object, or null if the target does no...
bool shouldInlineQuadwordAtomics() const
Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Inserts in the IR a target-specific intrinsic specifying a fence.
bool isLegalAddImmediate(int64_t Imm) const override
isLegalAddImmediate - Return true if the specified immediate is legal add immediate,...
Common code between 32-bit and 64-bit PowerPC targets.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:229
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:574
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:55
Provides information about what library functions are available for the current target.
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
SelectSupportKind
Enum that describes what type of support for selects the target has.
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const
Return the preferred vector type legalization action.
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
NegatibleCost
Enum that specifies when a float negation is beneficial.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
bool isArrayTy() const
True if this is an instance of ArrayType.
Definition: Type.h:264
LLVM Value Representation.
Definition: Value.h:75
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:1141
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1574
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1640
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:1671
@ SEXT_LD_SPLAT
VSRC, CHAIN = SEXT_LD_SPLAT, CHAIN, Ptr - a splatting load memory that sign-extends.
@ FCTIDUZ
Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for unsigned integers with round ...
@ ADDI_TLSGD_L_ADDR
G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that combines ADDI_TLSGD_L and GET_TLS_ADDR unti...
@ FSQRT
Square root instruction.
@ STRICT_FCFID
Constrained integer-to-floating-point conversion instructions.
@ DYNALLOC
The following two target-specific nodes are used for calls through function pointers in the 64-bit SV...
@ COND_BRANCH
CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This corresponds to the COND_BRANCH pseudo ...
@ TLSLD_AIX
[GP|G8]RC = TLSLD_AIX, TOC_ENTRY(module handle) Op that requires a single input of the module handle ...
@ CALL_RM
The variants that implicitly define rounding mode for calls with strictfp semantics.
@ STORE_VEC_BE
CHAIN = STORE_VEC_BE CHAIN, VSRC, Ptr - Occurs only for little endian.
@ BDNZ
CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based loops.
@ MTVSRZ
Direct move from a GPR to a VSX register (zero)
@ SRL
These nodes represent PPC shifts.
@ VECINSERT
VECINSERT - The PPC vector insert instruction.
@ LXSIZX
GPRC, CHAIN = LXSIZX, CHAIN, Ptr, ByteWidth - This is a load of an integer smaller than 64 bits into ...
@ FNMSUB
FNMSUB - Negated multiply-subtract instruction.
@ FCTIDZ
FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 operand, producing an f64 value...
@ GET_TLS_ADDR
x3 = GET_TLS_ADDR x3, Symbol - For the general-dynamic TLS model, produces a call to __tls_get_addr(s...
@ XXSPLTI32DX
XXSPLTI32DX - The PPC XXSPLTI32DX instruction.
@ ANDI_rec_1_EQ_BIT
i1 = ANDI_rec_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the eq or gt bit of CR0 after ex...
@ FRE
Reciprocal estimate instructions (unary FP ops).
@ ADDIS_GOT_TPREL_HA
G8RC = ADDIS_GOT_TPREL_HA x2, Symbol - Used by the initial-exec TLS model, produces an ADDIS8 instruc...
@ STORE_COND
CHAIN,Glue = STORE_COND CHAIN, GPR, Ptr The store conditional instruction ST[BHWD]ARX that produces a...
@ SINT_VEC_TO_FP
Extract a subvector from signed integer vector and convert to FP.
@ EXTRACT_SPE
Extract SPE register component, second argument is high or low.
@ XXSWAPD
VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little endian.
@ ADDI_TLSLD_L_ADDR
G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that combines ADDI_TLSLD_L and GET_TLSLD_ADDR un...
@ ATOMIC_CMP_SWAP_8
ATOMIC_CMP_SWAP - the exact same as the target-independent nodes except they ensure that the compare ...
@ ST_VSR_SCAL_INT
Store scalar integers from VSR.
@ VCMP
RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* instructions.
@ BCTRL
CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a BCTRL instruction.
@ BUILD_SPE64
BUILD_SPE64 and EXTRACT_SPE are analogous to BUILD_PAIR and EXTRACT_ELEMENT but take f64 arguments in...
@ LFIWZX
GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point load which zero-extends from a 32-bit inte...
@ FIRST_MEMORY_OPCODE
CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a byte-swapping store instruction.
@ RET_GLUE
Return with a glue operand, matched by 'blr'.
@ SCALAR_TO_VECTOR_PERMUTED
PowerPC instructions that have SCALAR_TO_VECTOR semantics tend to place the value into the least sign...
@ EXTRACT_VSX_REG
EXTRACT_VSX_REG = Extract one of the underlying vsx registers of an accumulator or pair register.
@ STXSIX
STXSIX - The STXSI[bh]X instruction.
@ MAT_PCREL_ADDR
MAT_PCREL_ADDR = Materialize a PC Relative address.
@ MFOCRF
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
@ XXSPLT
XXSPLT - The PPC VSX splat instructions.
@ TOC_ENTRY
GPRC = TOC_ENTRY GA, TOC Loads the entry for GA from the TOC, where the TOC base is given by the last...
@ XXPERMDI
XXPERMDI - The PPC XXPERMDI instruction.
@ ADDIS_DTPREL_HA
G8RC = ADDIS_DTPREL_HA x3, Symbol - For the local-dynamic TLS model, produces an ADDIS8 instruction t...
@ ADD_TLS
G8RC = ADD_TLS G8RReg, Symbol - Can be used by the initial-exec and local-exec TLS models,...
@ MTVSRA
Direct move from a GPR to a VSX register (algebraic)
@ VADD_SPLAT
VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded during instruction selection to optimi...
@ PPC32_GOT
GPRC = address of GLOBAL_OFFSET_TABLE.
@ ADDI_DTPREL_L
G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS model, produces an ADDI8 instruction ...
@ BCTRL_LOAD_TOC
CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl instruction and the TOC reload r...
@ PPC32_PICGOT
GPRC = address of GLOBAL_OFFSET_TABLE.
@ FCFID
FCFID - The FCFID instruction, taking an f64 operand and producing and f64 value containing the FP re...
@ CR6SET
ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
@ LBRX
GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a byte-swapping load instruction.
@ GET_TLS_MOD_AIX
x3 = GET_TLS_MOD_AIX _$TLSML - For the AIX local-dynamic TLS model, produces a call to ....
@ SETBC
SETBC - The ISA 3.1 (P10) SETBC instruction.
@ LD_VSX_LH
VSRC, CHAIN = LD_VSX_LH CHAIN, Ptr - This is a floating-point load of a v2f32 value into the lower ha...
@ PROBED_ALLOCA
To avoid stack clash, allocation is performed by block and each block is probed.
@ XXMFACC
XXMFACC = This corresponds to the xxmfacc instruction.
@ ADDIS_TLSGD_HA
G8RC = ADDIS_TLSGD_HA x2, Symbol - For the general-dynamic TLS model, produces an ADDIS8 instruction ...
@ SETBCR
SETBCR - The ISA 3.1 (P10) SETBCR instruction.
@ ACC_BUILD
ACC_BUILD = Build an accumulator register from 4 VSX registers.
@ GlobalBaseReg
The result of the mflr at function entry, used for PIC code.
@ LXVD2X
VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
@ XSMAXC
XSMAXC[DQ]P, XSMINC[DQ]P - C-type min/max instructions.
@ CALL
CALL - A direct function call.
@ MTCTR
CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a MTCTR instruction.
@ TC_RETURN
TC_RETURN - A tail call return.
@ STFIWX
STFIWX - The STFIWX instruction.
@ LD_SPLAT
VSRC, CHAIN = LD_SPLAT, CHAIN, Ptr - a splatting load memory instructions such as LXVDSX,...
@ VCMP_rec
RESVEC, OUTFLAG = VCMP_rec(LHS, RHS, OPC) - Represents one of the altivec VCMP*_rec instructions.
@ MFFS
F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
@ VSRQ
VSRQ - The ISA 3.1 (P10) Vector Shift right quadword instruction.
@ PADDI_DTPREL
G8RC = PADDI_DTPREL x3, Symbol - For the pc-rel based local-dynamic TLS model, produces a PADDI8 inst...
@ BUILD_FP128
Direct move of 2 consecutive GPR to a VSX register.
@ VEXTS
VEXTS, ByteWidth - takes an input in VSFRC and produces an output in VSFRC that is sign-extended from...
@ TLS_LOCAL_EXEC_MAT_ADDR
TLS_LOCAL_EXEC_MAT_ADDR = Materialize an address for TLS global address when using local exec access ...
@ VPERM
VPERM - The PPC VPERM Instruction.
@ ADDIS_TLSLD_HA
G8RC = ADDIS_TLSLD_HA x2, Symbol - For the local-dynamic TLS model, produces an ADDIS8 instruction th...
@ XXSPLTI_SP_TO_DP
XXSPLTI_SP_TO_DP - The PPC VSX splat instructions for immediates for converting immediate single prec...
@ GET_TLSLD_ADDR
x3 = GET_TLSLD_ADDR x3, Symbol - For the local-dynamic TLS model, produces a call to __tls_get_addr(s...
@ ADDI_TLSGD_L
x3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS model, produces an ADDI8 instruction t...
@ DYNAREAOFFSET
This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to compute an offset from native ...
@ PAIR_BUILD
PAIR_BUILD = Build a vector pair register from 2 VSX registers.
@ STRICT_FADDRTZ
Constrained floating point add in round-to-zero mode.
@ FTSQRT
Test instruction for software square root.
@ FP_EXTEND_HALF
FP_EXTEND_HALF(VECTOR, IDX) - Custom extend upper (IDX=0) half or lower (IDX=1) half of v4f32 to v2f6...
@ CMPB
The CMPB instruction (takes two operands of i32 or i64).
@ VECSHL
VECSHL - The PPC vector shift left instruction.
@ ADDI_TLSLD_L
x3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS model, produces an ADDI8 instruction tha...
@ FADDRTZ
F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding towards zero.
@ ZEXT_LD_SPLAT
VSRC, CHAIN = ZEXT_LD_SPLAT, CHAIN, Ptr - a splatting load memory that zero-extends.
@ SRA_ADDZE
The combination of sra[wd]i and addze used to implemented signed integer division by a power of 2.
@ EXTSWSLI
EXTSWSLI = The PPC extswsli instruction, which does an extend-sign word and shift left immediate.
@ STXVD2X
CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
@ ADDC
These nodes represent PPC arithmetic operations with carry.
@ TLSGD_AIX
GPRC = TLSGD_AIX, TOC_ENTRY, TOC_ENTRY G8RC = TLSGD_AIX, TOC_ENTRY, TOC_ENTRY Op that combines two re...
@ UINT_VEC_TO_FP
Extract a subvector from unsigned integer vector and convert to FP.
@ GET_TPOINTER
x3 = GET_TPOINTER - Used for the local- and initial-exec TLS model on 32-bit AIX, produces a call to ...
@ LXVRZX
LXVRZX - Load VSX Vector Rightmost and Zero Extend This node represents v1i128 BUILD_VECTOR of a zero...
@ FCFIDU
Newer FCFID[US] integer-to-floating-point conversion instructions for unsigned integers and single-pr...
@ FSEL
FSEL - Traditional three-operand fsel node.
@ SWAP_NO_CHAIN
An SDNode for swaps that are not associated with any loads/stores and thereby have no chain.
@ LOAD_VEC_BE
VSRC, CHAIN = LOAD_VEC_BE CHAIN, Ptr - Occurs only for little endian.
@ LFIWAX
GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point load which sign-extends from a 32-bit inte...
@ LD_GOT_TPREL_L
G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec TLS model, produces a LD instruction ...
@ MFVSR
Direct move from a VSX register to a GPR.
@ TLS_DYNAMIC_MAT_PCREL_ADDR
TLS_DYNAMIC_MAT_PCREL_ADDR = Materialize a PC Relative address for TLS global address when using dyna...
@ Hi
Hi/Lo - These represent the high and low 16-bit parts of a global address respectively.
SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG)
get_VSPLTI_elt - If this is a build_vector of constants which can be formed by using a vspltis[bhw] i...
bool isXXBRDShuffleMask(ShuffleVectorSDNode *N)
isXXBRDShuffleMask - Return true if this is a shuffle mask suitable for a XXBRD instruction.
FastISel * createFastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo)
bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG)
isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for a VRGH* instruction with the ...
bool isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a VPKUDUM instruction.
bool isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven, unsigned ShuffleKind, SelectionDAG &DAG)
isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for a VMRGEW or VMRGOW instructi...
bool isXXBRQShuffleMask(ShuffleVectorSDNode *N)
isXXBRQShuffleMask - Return true if this is a shuffle mask suitable for a XXBRQ instruction.
bool isXXBRWShuffleMask(ShuffleVectorSDNode *N)
isXXBRWShuffleMask - Return true if this is a shuffle mask suitable for a XXBRW instruction.
bool isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, bool &Swap, bool IsLE)
isXXPERMDIShuffleMask - Return true if this is a shuffle mask suitable for a XXPERMDI instruction.
bool isXXBRHShuffleMask(ShuffleVectorSDNode *N)
isXXBRHShuffleMask - Return true if this is a shuffle mask suitable for a XXBRH instruction.
unsigned getSplatIdxForPPCMnemonics(SDNode *N, unsigned EltSize, SelectionDAG &DAG)
getSplatIdxForPPCMnemonics - Return the splat index as a value that is appropriate for PPC mnemonics ...
bool isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, bool &Swap, bool IsLE)
isXXSLDWIShuffleMask - Return true if this is a shuffle mask suitable for a XXSLDWI instruction.
int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift amount, otherwise return -1.
bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG)
isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for a VRGL* instruction with the ...
bool isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, unsigned &InsertAtByte, bool &Swap, bool IsLE)
isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by the XXINSERTW instruction intr...
bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize)
isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand specifies a splat of a singl...
bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a VPKUWUM instruction.
bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a VPKUHUM instruction.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:477
bool checkConvertToNonDenormSingle(APFloat &ArgAPFloat)
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
bool isIntS16Immediate(SDNode *N, int16_t &Imm)
isIntS16Immediate - This method tests to see if the node is either a 32-bit or 64-bit immediate,...
bool convertToNonDenormSingle(APInt &ArgAPInt)
AtomicOrdering
Atomic ordering for LLVM's memory model.
bool isIntS34Immediate(SDNode *N, int64_t &Imm)
isIntS34Immediate - This method tests if value of node given can be accurately represented as a sign ...
DWARFExpression::Operation Op
#define N
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:760
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:35
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:157
This class contains a discriminated union of information about pointers in memory operands,...
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:117
Structure that collects some common arguments that get passed around between the functions for call l...
CallFlags(CallingConv::ID CC, bool IsTailCall, bool IsVarArg, bool IsPatchPoint, bool IsIndirect, bool HasNest, bool NoMerge)