LLVM 22.0.0git
RISCVExpandPseudoInsts.cpp
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1//===-- RISCVExpandPseudoInsts.cpp - Expand pseudo instructions -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a pass that expands pseudo instructions into target
10// instructions. This pass should be run after register allocation but before
11// the post-regalloc scheduling pass.
12//
13//===----------------------------------------------------------------------===//
14
15#include "RISCV.h"
16#include "RISCVInstrInfo.h"
17#include "RISCVTargetMachine.h"
18
19#include "llvm/CodeGen/LivePhysRegs.h"
20#include "llvm/CodeGen/MachineFunctionPass.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/MC/MCContext.h"
23
24using namespace llvm;
25
26#define RISCV_EXPAND_PSEUDO_NAME "RISC-V pseudo instruction expansion pass"
27#define RISCV_PRERA_EXPAND_PSEUDO_NAME "RISC-V Pre-RA pseudo instruction expansion pass"
28
29namespace {
30
31class RISCVExpandPseudo : public MachineFunctionPass {
32public:
33 const RISCVSubtarget *STI;
34 const RISCVInstrInfo *TII;
35 static char ID;
36
37 RISCVExpandPseudo() : MachineFunctionPass(ID) {}
38
39 bool runOnMachineFunction(MachineFunction &MF) override;
40
41 StringRef getPassName() const override { return RISCV_EXPAND_PSEUDO_NAME; }
42
43private:
44 bool expandMBB(MachineBasicBlock &MBB);
45 bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
46 MachineBasicBlock::iterator &NextMBBI);
47 bool expandCCOp(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
48 MachineBasicBlock::iterator &NextMBBI);
49 bool expandCCOpToCMov(MachineBasicBlock &MBB,
50 MachineBasicBlock::iterator MBBI);
51 bool expandVMSET_VMCLR(MachineBasicBlock &MBB,
52 MachineBasicBlock::iterator MBBI, unsigned Opcode);
53 bool expandMV_FPR16INX(MachineBasicBlock &MBB,
54 MachineBasicBlock::iterator MBBI);
55 bool expandMV_FPR32INX(MachineBasicBlock &MBB,
56 MachineBasicBlock::iterator MBBI);
57 bool expandRV32ZdinxStore(MachineBasicBlock &MBB,
58 MachineBasicBlock::iterator MBBI);
59 bool expandRV32ZdinxLoad(MachineBasicBlock &MBB,
60 MachineBasicBlock::iterator MBBI);
61 bool expandPseudoReadVLENBViaVSETVLIX0(MachineBasicBlock &MBB,
62 MachineBasicBlock::iterator MBBI);
63#ifndef NDEBUG
64 unsigned getInstSizeInBytes(const MachineFunction &MF) const {
65 unsigned Size = 0;
66 for (auto &MBB : MF)
67 for (auto &MI : MBB)
68 Size += TII->getInstSizeInBytes(MI);
69 return Size;
70 }
71#endif
72};
73
74char RISCVExpandPseudo::ID = 0;
75
76bool RISCVExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
77 STI = &MF.getSubtarget<RISCVSubtarget>();
78 TII = STI->getInstrInfo();
79
80#ifndef NDEBUG
81 const unsigned OldSize = getInstSizeInBytes(MF);
82#endif
83
84 bool Modified = false;
85 for (auto &MBB : MF)
86 Modified |= expandMBB(MBB);
87
88#ifndef NDEBUG
89 const unsigned NewSize = getInstSizeInBytes(MF);
90 assert(OldSize >= NewSize);
91#endif
92 return Modified;
93}
94
95bool RISCVExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
96 bool Modified = false;
97
98 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
99 while (MBBI != E) {
100 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
101 Modified |= expandMI(MBB, MBBI, NMBBI);
102 MBBI = NMBBI;
103 }
104
105 return Modified;
106}
107
108bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
109 MachineBasicBlock::iterator MBBI,
110 MachineBasicBlock::iterator &NextMBBI) {
111 // RISCVInstrInfo::getInstSizeInBytes expects that the total size of the
112 // expanded instructions for each pseudo is correct in the Size field of the
113 // tablegen definition for the pseudo.
114 switch (MBBI->getOpcode()) {
115 case RISCV::PseudoMV_FPR16INX:
116 return expandMV_FPR16INX(MBB, MBBI);
117 case RISCV::PseudoMV_FPR32INX:
118 return expandMV_FPR32INX(MBB, MBBI);
119 case RISCV::PseudoRV32ZdinxSD:
120 return expandRV32ZdinxStore(MBB, MBBI);
121 case RISCV::PseudoRV32ZdinxLD:
122 return expandRV32ZdinxLoad(MBB, MBBI);
123 case RISCV::PseudoCCMOVGPRNoX0:
124 case RISCV::PseudoCCMOVGPR:
125 case RISCV::PseudoCCADD:
126 case RISCV::PseudoCCSUB:
127 case RISCV::PseudoCCAND:
128 case RISCV::PseudoCCOR:
129 case RISCV::PseudoCCXOR:
130 case RISCV::PseudoCCADDW:
131 case RISCV::PseudoCCSUBW:
132 case RISCV::PseudoCCSLL:
133 case RISCV::PseudoCCSRL:
134 case RISCV::PseudoCCSRA:
135 case RISCV::PseudoCCADDI:
136 case RISCV::PseudoCCSLLI:
137 case RISCV::PseudoCCSRLI:
138 case RISCV::PseudoCCSRAI:
139 case RISCV::PseudoCCANDI:
140 case RISCV::PseudoCCORI:
141 case RISCV::PseudoCCXORI:
142 case RISCV::PseudoCCSLLW:
143 case RISCV::PseudoCCSRLW:
144 case RISCV::PseudoCCSRAW:
145 case RISCV::PseudoCCADDIW:
146 case RISCV::PseudoCCSLLIW:
147 case RISCV::PseudoCCSRLIW:
148 case RISCV::PseudoCCSRAIW:
149 case RISCV::PseudoCCANDN:
150 case RISCV::PseudoCCORN:
151 case RISCV::PseudoCCXNOR:
152 case RISCV::PseudoCCNDS_BFOS:
153 case RISCV::PseudoCCNDS_BFOZ:
154 return expandCCOp(MBB, MBBI, NextMBBI);
155 case RISCV::PseudoVMCLR_M_B1:
156 case RISCV::PseudoVMCLR_M_B2:
157 case RISCV::PseudoVMCLR_M_B4:
158 case RISCV::PseudoVMCLR_M_B8:
159 case RISCV::PseudoVMCLR_M_B16:
160 case RISCV::PseudoVMCLR_M_B32:
161 case RISCV::PseudoVMCLR_M_B64:
162 // vmclr.m vd => vmxor.mm vd, vd, vd
163 return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXOR_MM);
164 case RISCV::PseudoVMSET_M_B1:
165 case RISCV::PseudoVMSET_M_B2:
166 case RISCV::PseudoVMSET_M_B4:
167 case RISCV::PseudoVMSET_M_B8:
168 case RISCV::PseudoVMSET_M_B16:
169 case RISCV::PseudoVMSET_M_B32:
170 case RISCV::PseudoVMSET_M_B64:
171 // vmset.m vd => vmxnor.mm vd, vd, vd
172 return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXNOR_MM);
173 case RISCV::PseudoReadVLENBViaVSETVLIX0:
174 return expandPseudoReadVLENBViaVSETVLIX0(MBB, MBBI);
175 }
176
177 return false;
178}
179
180bool RISCVExpandPseudo::expandCCOp(MachineBasicBlock &MBB,
181 MachineBasicBlock::iterator MBBI,
182 MachineBasicBlock::iterator &NextMBBI) {
183 // First try expanding to a Conditional Move rather than a branch+mv
184 if (expandCCOpToCMov(MBB, MBBI))
185 return true;
186
187 MachineFunction *MF = MBB.getParent();
188 MachineInstr &MI = *MBBI;
189 DebugLoc DL = MI.getDebugLoc();
190
191 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
192 MachineBasicBlock *MergeBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
193
194 MF->insert(++MBB.getIterator(), TrueBB);
195 MF->insert(++TrueBB->getIterator(), MergeBB);
196
197 // We want to copy the "true" value when the condition is true which means
198 // we need to invert the branch condition to jump over TrueBB when the
199 // condition is false.
200 auto CC = static_cast<RISCVCC::CondCode>(MI.getOperand(3).getImm());
201 CC = RISCVCC::getInverseBranchCondition(CC);
202
203 // Insert branch instruction.
204 BuildMI(MBB, MBBI, DL, TII->get(RISCVCC::getBrCond(CC)))
205 .addReg(MI.getOperand(1).getReg())
206 .addReg(MI.getOperand(2).getReg())
207 .addMBB(MergeBB);
208
209 Register DestReg = MI.getOperand(0).getReg();
210 assert(MI.getOperand(4).getReg() == DestReg);
211
212 if (MI.getOpcode() == RISCV::PseudoCCMOVGPR ||
213 MI.getOpcode() == RISCV::PseudoCCMOVGPRNoX0) {
214 // Add MV.
215 BuildMI(TrueBB, DL, TII->get(RISCV::ADDI), DestReg)
216 .add(MI.getOperand(5))
217 .addImm(0);
218 } else {
219 unsigned NewOpc;
220 switch (MI.getOpcode()) {
221 default:
222 llvm_unreachable("Unexpected opcode!");
223 case RISCV::PseudoCCADD: NewOpc = RISCV::ADD; break;
224 case RISCV::PseudoCCSUB: NewOpc = RISCV::SUB; break;
225 case RISCV::PseudoCCSLL: NewOpc = RISCV::SLL; break;
226 case RISCV::PseudoCCSRL: NewOpc = RISCV::SRL; break;
227 case RISCV::PseudoCCSRA: NewOpc = RISCV::SRA; break;
228 case RISCV::PseudoCCAND: NewOpc = RISCV::AND; break;
229 case RISCV::PseudoCCOR: NewOpc = RISCV::OR; break;
230 case RISCV::PseudoCCXOR: NewOpc = RISCV::XOR; break;
231 case RISCV::PseudoCCADDI: NewOpc = RISCV::ADDI; break;
232 case RISCV::PseudoCCSLLI: NewOpc = RISCV::SLLI; break;
233 case RISCV::PseudoCCSRLI: NewOpc = RISCV::SRLI; break;
234 case RISCV::PseudoCCSRAI: NewOpc = RISCV::SRAI; break;
235 case RISCV::PseudoCCANDI: NewOpc = RISCV::ANDI; break;
236 case RISCV::PseudoCCORI: NewOpc = RISCV::ORI; break;
237 case RISCV::PseudoCCXORI: NewOpc = RISCV::XORI; break;
238 case RISCV::PseudoCCADDW: NewOpc = RISCV::ADDW; break;
239 case RISCV::PseudoCCSUBW: NewOpc = RISCV::SUBW; break;
240 case RISCV::PseudoCCSLLW: NewOpc = RISCV::SLLW; break;
241 case RISCV::PseudoCCSRLW: NewOpc = RISCV::SRLW; break;
242 case RISCV::PseudoCCSRAW: NewOpc = RISCV::SRAW; break;
243 case RISCV::PseudoCCADDIW: NewOpc = RISCV::ADDIW; break;
244 case RISCV::PseudoCCSLLIW: NewOpc = RISCV::SLLIW; break;
245 case RISCV::PseudoCCSRLIW: NewOpc = RISCV::SRLIW; break;
246 case RISCV::PseudoCCSRAIW: NewOpc = RISCV::SRAIW; break;
247 case RISCV::PseudoCCANDN: NewOpc = RISCV::ANDN; break;
248 case RISCV::PseudoCCORN: NewOpc = RISCV::ORN; break;
249 case RISCV::PseudoCCXNOR: NewOpc = RISCV::XNOR; break;
250 case RISCV::PseudoCCNDS_BFOS: NewOpc = RISCV::NDS_BFOS; break;
251 case RISCV::PseudoCCNDS_BFOZ: NewOpc = RISCV::NDS_BFOZ; break;
252 }
253
254 if (NewOpc == RISCV::NDS_BFOZ || NewOpc == RISCV::NDS_BFOS) {
255 BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg)
256 .add(MI.getOperand(5))
257 .add(MI.getOperand(6))
258 .add(MI.getOperand(7));
259 } else {
260 BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg)
261 .add(MI.getOperand(5))
262 .add(MI.getOperand(6));
263 }
264 }
265
266 TrueBB->addSuccessor(MergeBB);
267
268 MergeBB->splice(MergeBB->end(), &MBB, MI, MBB.end());
269 MergeBB->transferSuccessors(&MBB);
270
271 MBB.addSuccessor(TrueBB);
272 MBB.addSuccessor(MergeBB);
273
274 NextMBBI = MBB.end();
275 MI.eraseFromParent();
276
277 // Make sure live-ins are correctly attached to this new basic block.
278 LivePhysRegs LiveRegs;
279 computeAndAddLiveIns(LiveRegs, *TrueBB);
280 computeAndAddLiveIns(LiveRegs, *MergeBB);
281
282 return true;
283}
284
285bool RISCVExpandPseudo::expandCCOpToCMov(MachineBasicBlock &MBB,
286 MachineBasicBlock::iterator MBBI) {
287 MachineInstr &MI = *MBBI;
288 DebugLoc DL = MI.getDebugLoc();
289
290 if (MI.getOpcode() != RISCV::PseudoCCMOVGPR &&
291 MI.getOpcode() != RISCV::PseudoCCMOVGPRNoX0)
292 return false;
293
294 if (!STI->hasVendorXqcicm())
295 return false;
296
297 // FIXME: Would be wonderful to support LHS=X0, but not very easy.
298 if (MI.getOperand(1).getReg() == RISCV::X0 ||
299 MI.getOperand(4).getReg() == RISCV::X0 ||
300 MI.getOperand(5).getReg() == RISCV::X0)
301 return false;
302
303 auto CC = static_cast<RISCVCC::CondCode>(MI.getOperand(3).getImm());
304
305 unsigned CMovOpcode, CMovIOpcode;
306 switch (CC) {
307 default:
308 llvm_unreachable("Unhandled CC");
309 case RISCVCC::COND_EQ:
310 CMovOpcode = RISCV::QC_MVEQ;
311 CMovIOpcode = RISCV::QC_MVEQI;
312 break;
313 case RISCVCC::COND_NE:
314 CMovOpcode = RISCV::QC_MVNE;
315 CMovIOpcode = RISCV::QC_MVNEI;
316 break;
317 case RISCVCC::COND_LT:
318 CMovOpcode = RISCV::QC_MVLT;
319 CMovIOpcode = RISCV::QC_MVLTI;
320 break;
321 case RISCVCC::COND_GE:
322 CMovOpcode = RISCV::QC_MVGE;
323 CMovIOpcode = RISCV::QC_MVGEI;
324 break;
325 case RISCVCC::COND_LTU:
326 CMovOpcode = RISCV::QC_MVLTU;
327 CMovIOpcode = RISCV::QC_MVLTUI;
328 break;
329 case RISCVCC::COND_GEU:
330 CMovOpcode = RISCV::QC_MVGEU;
331 CMovIOpcode = RISCV::QC_MVGEUI;
332 break;
333 }
334
335 if (MI.getOperand(2).getReg() == RISCV::X0) {
336 // $dst = PseudoCCMOVGPR $lhs, X0, $cc, $falsev (=$dst), $truev
337 // $dst = PseudoCCMOVGPRNoX0 $lhs, X0, $cc, $falsev (=$dst), $truev
338 // =>
339 // $dst = QC_MVccI $falsev (=$dst), $lhs, 0, $truev
340 BuildMI(MBB, MBBI, DL, TII->get(CMovIOpcode))
341 .addDef(MI.getOperand(0).getReg())
342 .addReg(MI.getOperand(4).getReg())
343 .addReg(MI.getOperand(1).getReg())
344 .addImm(0)
345 .addReg(MI.getOperand(5).getReg());
346
347 MI.eraseFromParent();
348 return true;
349 }
350
351 // $dst = PseudoCCMOVGPR $lhs, $rhs, $cc, $falsev (=$dst), $truev
352 // $dst = PseudoCCMOVGPRNoX0 $lhs, $rhs, $cc, $falsev (=$dst), $truev
353 // =>
354 // $dst = QC_MVcc $falsev (=$dst), $lhs, $rhs, $truev
355 BuildMI(MBB, MBBI, DL, TII->get(CMovOpcode))
356 .addDef(MI.getOperand(0).getReg())
357 .addReg(MI.getOperand(4).getReg())
358 .addReg(MI.getOperand(1).getReg())
359 .addReg(MI.getOperand(2).getReg())
360 .addReg(MI.getOperand(5).getReg());
361 MI.eraseFromParent();
362 return true;
363}
364
365bool RISCVExpandPseudo::expandVMSET_VMCLR(MachineBasicBlock &MBB,
366 MachineBasicBlock::iterator MBBI,
367 unsigned Opcode) {
368 DebugLoc DL = MBBI->getDebugLoc();
369 Register DstReg = MBBI->getOperand(0).getReg();
370 const MCInstrDesc &Desc = TII->get(Opcode);
371 BuildMI(MBB, MBBI, DL, Desc, DstReg)
372 .addReg(DstReg, RegState::Undef)
373 .addReg(DstReg, RegState::Undef);
374 MBBI->eraseFromParent(); // The pseudo instruction is gone now.
375 return true;
376}
377
378bool RISCVExpandPseudo::expandMV_FPR16INX(MachineBasicBlock &MBB,
379 MachineBasicBlock::iterator MBBI) {
380 DebugLoc DL = MBBI->getDebugLoc();
381 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
382 Register DstReg = TRI->getMatchingSuperReg(
383 MBBI->getOperand(0).getReg(), RISCV::sub_16, &RISCV::GPRRegClass);
384 Register SrcReg = TRI->getMatchingSuperReg(
385 MBBI->getOperand(1).getReg(), RISCV::sub_16, &RISCV::GPRRegClass);
386
387 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DstReg)
388 .addReg(SrcReg, getKillRegState(MBBI->getOperand(1).isKill()))
389 .addImm(0);
390
391 MBBI->eraseFromParent(); // The pseudo instruction is gone now.
392 return true;
393}
394
395bool RISCVExpandPseudo::expandMV_FPR32INX(MachineBasicBlock &MBB,
396 MachineBasicBlock::iterator MBBI) {
397 DebugLoc DL = MBBI->getDebugLoc();
398 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
399 Register DstReg = TRI->getMatchingSuperReg(
400 MBBI->getOperand(0).getReg(), RISCV::sub_32, &RISCV::GPRRegClass);
401 Register SrcReg = TRI->getMatchingSuperReg(
402 MBBI->getOperand(1).getReg(), RISCV::sub_32, &RISCV::GPRRegClass);
403
404 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DstReg)
405 .addReg(SrcReg, getKillRegState(MBBI->getOperand(1).isKill()))
406 .addImm(0);
407
408 MBBI->eraseFromParent(); // The pseudo instruction is gone now.
409 return true;
410}
411
412// This function expands the PseudoRV32ZdinxSD for storing a double-precision
413// floating-point value into memory by generating an equivalent instruction
414// sequence for RV32.
415bool RISCVExpandPseudo::expandRV32ZdinxStore(MachineBasicBlock &MBB,
416 MachineBasicBlock::iterator MBBI) {
417 DebugLoc DL = MBBI->getDebugLoc();
418 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
419 Register Lo =
420 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even);
421 Register Hi =
422 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);
423 if (Hi == RISCV::DUMMY_REG_PAIR_WITH_X0)
424 Hi = RISCV::X0;
425
426 auto MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
427 .addReg(Lo, getKillRegState(MBBI->getOperand(0).isKill()))
428 .addReg(MBBI->getOperand(1).getReg())
429 .add(MBBI->getOperand(2));
430
431 MachineInstrBuilder MIBHi;
432 if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
433 assert(MBBI->getOperand(2).getOffset() % 8 == 0);
434 MBBI->getOperand(2).setOffset(MBBI->getOperand(2).getOffset() + 4);
435 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
436 .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
437 .add(MBBI->getOperand(1))
438 .add(MBBI->getOperand(2));
439 } else {
440 assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
441 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
442 .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
443 .add(MBBI->getOperand(1))
444 .addImm(MBBI->getOperand(2).getImm() + 4);
445 }
446
447 MachineFunction *MF = MBB.getParent();
448 SmallVector<MachineMemOperand *> NewLoMMOs;
449 SmallVector<MachineMemOperand *> NewHiMMOs;
450 for (const MachineMemOperand *MMO : MBBI->memoperands()) {
451 NewLoMMOs.push_back(MF->getMachineMemOperand(MMO, 0, 4));
452 NewHiMMOs.push_back(MF->getMachineMemOperand(MMO, 4, 4));
453 }
454 MIBLo.setMemRefs(NewLoMMOs);
455 MIBHi.setMemRefs(NewHiMMOs);
456
457 MBBI->eraseFromParent();
458 return true;
459}
460
461// This function expands PseudoRV32ZdinxLoad for loading a double-precision
462// floating-point value from memory into an equivalent instruction sequence for
463// RV32.
464bool RISCVExpandPseudo::expandRV32ZdinxLoad(MachineBasicBlock &MBB,
465 MachineBasicBlock::iterator MBBI) {
466 DebugLoc DL = MBBI->getDebugLoc();
467 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
468 Register Lo =
469 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even);
470 Register Hi =
471 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);
472 assert(Hi != RISCV::DUMMY_REG_PAIR_WITH_X0 && "Cannot write to X0_Pair");
473
474 MachineInstrBuilder MIBLo, MIBHi;
475
476 // If the register of operand 1 is equal to the Lo register, then swap the
477 // order of loading the Lo and Hi statements.
478 bool IsOp1EqualToLo = Lo == MBBI->getOperand(1).getReg();
479 // Order: Lo, Hi
480 if (!IsOp1EqualToLo) {
481 MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
482 .addReg(MBBI->getOperand(1).getReg())
483 .add(MBBI->getOperand(2));
484 }
485
486 if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
487 auto Offset = MBBI->getOperand(2).getOffset();
488 assert(Offset % 8 == 0);
489 MBBI->getOperand(2).setOffset(Offset + 4);
490 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
491 .addReg(MBBI->getOperand(1).getReg())
492 .add(MBBI->getOperand(2));
493 MBBI->getOperand(2).setOffset(Offset);
494 } else {
495 assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
496 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
497 .addReg(MBBI->getOperand(1).getReg())
498 .addImm(MBBI->getOperand(2).getImm() + 4);
499 }
500
501 // Order: Hi, Lo
502 if (IsOp1EqualToLo) {
503 MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
504 .addReg(MBBI->getOperand(1).getReg())
505 .add(MBBI->getOperand(2));
506 }
507
508 MachineFunction *MF = MBB.getParent();
509 SmallVector<MachineMemOperand *> NewLoMMOs;
510 SmallVector<MachineMemOperand *> NewHiMMOs;
511 for (const MachineMemOperand *MMO : MBBI->memoperands()) {
512 NewLoMMOs.push_back(MF->getMachineMemOperand(MMO, 0, 4));
513 NewHiMMOs.push_back(MF->getMachineMemOperand(MMO, 4, 4));
514 }
515 MIBLo.setMemRefs(NewLoMMOs);
516 MIBHi.setMemRefs(NewHiMMOs);
517
518 MBBI->eraseFromParent();
519 return true;
520}
521
522bool RISCVExpandPseudo::expandPseudoReadVLENBViaVSETVLIX0(
523 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
524 DebugLoc DL = MBBI->getDebugLoc();
525 Register Dst = MBBI->getOperand(0).getReg();
526 unsigned Mul = MBBI->getOperand(1).getImm();
527 RISCVVType::VLMUL VLMUL = RISCVVType::encodeLMUL(Mul, /*Fractional=*/false);
528 unsigned VTypeImm = RISCVVType::encodeVTYPE(
529 VLMUL, /*SEW=*/8, /*TailAgnostic=*/true, /*MaskAgnostic=*/true);
530
531 BuildMI(MBB, MBBI, DL, TII->get(RISCV::PseudoVSETVLIX0))
532 .addReg(Dst, RegState::Define)
533 .addReg(RISCV::X0, RegState::Kill)
534 .addImm(VTypeImm);
535
536 MBBI->eraseFromParent();
537 return true;
538}
539
540class RISCVPreRAExpandPseudo : public MachineFunctionPass {
541public:
542 const RISCVSubtarget *STI;
543 const RISCVInstrInfo *TII;
544 static char ID;
545
546 RISCVPreRAExpandPseudo() : MachineFunctionPass(ID) {}
547
548 bool runOnMachineFunction(MachineFunction &MF) override;
549
550 void getAnalysisUsage(AnalysisUsage &AU) const override {
551 AU.setPreservesCFG();
552 MachineFunctionPass::getAnalysisUsage(AU);
553 }
554 StringRef getPassName() const override {
555 return RISCV_PRERA_EXPAND_PSEUDO_NAME;
556 }
557
558private:
559 bool expandMBB(MachineBasicBlock &MBB);
560 bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
561 MachineBasicBlock::iterator &NextMBBI);
562 bool expandAuipcInstPair(MachineBasicBlock &MBB,
563 MachineBasicBlock::iterator MBBI,
564 MachineBasicBlock::iterator &NextMBBI,
565 unsigned FlagsHi, unsigned SecondOpcode);
566 bool expandLoadLocalAddress(MachineBasicBlock &MBB,
567 MachineBasicBlock::iterator MBBI,
568 MachineBasicBlock::iterator &NextMBBI);
569 bool expandLoadGlobalAddress(MachineBasicBlock &MBB,
570 MachineBasicBlock::iterator MBBI,
571 MachineBasicBlock::iterator &NextMBBI);
572 bool expandLoadTLSIEAddress(MachineBasicBlock &MBB,
573 MachineBasicBlock::iterator MBBI,
574 MachineBasicBlock::iterator &NextMBBI);
575 bool expandLoadTLSGDAddress(MachineBasicBlock &MBB,
576 MachineBasicBlock::iterator MBBI,
577 MachineBasicBlock::iterator &NextMBBI);
578 bool expandLoadTLSDescAddress(MachineBasicBlock &MBB,
579 MachineBasicBlock::iterator MBBI,
580 MachineBasicBlock::iterator &NextMBBI);
581
582#ifndef NDEBUG
583 unsigned getInstSizeInBytes(const MachineFunction &MF) const {
584 unsigned Size = 0;
585 for (auto &MBB : MF)
586 for (auto &MI : MBB)
587 Size += TII->getInstSizeInBytes(MI);
588 return Size;
589 }
590#endif
591};
592
593char RISCVPreRAExpandPseudo::ID = 0;
594
595bool RISCVPreRAExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
596 STI = &MF.getSubtarget<RISCVSubtarget>();
597 TII = STI->getInstrInfo();
598
599#ifndef NDEBUG
600 const unsigned OldSize = getInstSizeInBytes(MF);
601#endif
602
603 bool Modified = false;
604 for (auto &MBB : MF)
605 Modified |= expandMBB(MBB);
606
607#ifndef NDEBUG
608 const unsigned NewSize = getInstSizeInBytes(MF);
609 assert(OldSize >= NewSize);
610#endif
611 return Modified;
612}
613
614bool RISCVPreRAExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
615 bool Modified = false;
616
617 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
618 while (MBBI != E) {
619 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
620 Modified |= expandMI(MBB, MBBI, NMBBI);
621 MBBI = NMBBI;
622 }
623
624 return Modified;
625}
626
627bool RISCVPreRAExpandPseudo::expandMI(MachineBasicBlock &MBB,
628 MachineBasicBlock::iterator MBBI,
629 MachineBasicBlock::iterator &NextMBBI) {
630
631 switch (MBBI->getOpcode()) {
632 case RISCV::PseudoLLA:
633 return expandLoadLocalAddress(MBB, MBBI, NextMBBI);
634 case RISCV::PseudoLGA:
635 return expandLoadGlobalAddress(MBB, MBBI, NextMBBI);
636 case RISCV::PseudoLA_TLS_IE:
637 return expandLoadTLSIEAddress(MBB, MBBI, NextMBBI);
638 case RISCV::PseudoLA_TLS_GD:
639 return expandLoadTLSGDAddress(MBB, MBBI, NextMBBI);
640 case RISCV::PseudoLA_TLSDESC:
641 return expandLoadTLSDescAddress(MBB, MBBI, NextMBBI);
642 }
643 return false;
644}
645
646bool RISCVPreRAExpandPseudo::expandAuipcInstPair(
647 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
648 MachineBasicBlock::iterator &NextMBBI, unsigned FlagsHi,
649 unsigned SecondOpcode) {
650 MachineFunction *MF = MBB.getParent();
651 MachineInstr &MI = *MBBI;
652 DebugLoc DL = MI.getDebugLoc();
653
654 Register DestReg = MI.getOperand(0).getReg();
655 Register ScratchReg =
656 MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
657
658 MachineOperand &Symbol = MI.getOperand(1);
659 Symbol.setTargetFlags(FlagsHi);
660 MCSymbol *AUIPCSymbol = MF->getContext().createNamedTempSymbol("pcrel_hi");
661
662 MachineInstr *MIAUIPC =
663 BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol);
664 MIAUIPC->setPreInstrSymbol(*MF, AUIPCSymbol);
665
666 MachineInstr *SecondMI =
667 BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
668 .addReg(ScratchReg)
669 .addSym(AUIPCSymbol, RISCVII::MO_PCREL_LO);
670
671 if (MI.hasOneMemOperand())
672 SecondMI->addMemOperand(*MF, *MI.memoperands_begin());
673
674 MI.eraseFromParent();
675 return true;
676}
677
678bool RISCVPreRAExpandPseudo::expandLoadLocalAddress(
679 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
680 MachineBasicBlock::iterator &NextMBBI) {
681 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_PCREL_HI,
682 RISCV::ADDI);
683}
684
685bool RISCVPreRAExpandPseudo::expandLoadGlobalAddress(
686 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
687 MachineBasicBlock::iterator &NextMBBI) {
688 unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;
689 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_GOT_HI,
690 SecondOpcode);
691}
692
693bool RISCVPreRAExpandPseudo::expandLoadTLSIEAddress(
694 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
695 MachineBasicBlock::iterator &NextMBBI) {
696 unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;
697 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GOT_HI,
698 SecondOpcode);
699}
700
701bool RISCVPreRAExpandPseudo::expandLoadTLSGDAddress(
702 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
703 MachineBasicBlock::iterator &NextMBBI) {
704 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GD_HI,
705 RISCV::ADDI);
706}
707
708bool RISCVPreRAExpandPseudo::expandLoadTLSDescAddress(
709 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
710 MachineBasicBlock::iterator &NextMBBI) {
711 MachineFunction *MF = MBB.getParent();
712 MachineInstr &MI = *MBBI;
713 DebugLoc DL = MI.getDebugLoc();
714
715 const auto &STI = MF->getSubtarget<RISCVSubtarget>();
716 unsigned SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW;
717
718 Register FinalReg = MI.getOperand(0).getReg();
719 Register DestReg =
720 MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
721 Register ScratchReg =
722 MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
723
724 MachineOperand &Symbol = MI.getOperand(1);
725 Symbol.setTargetFlags(RISCVII::MO_TLSDESC_HI);
726 MCSymbol *AUIPCSymbol = MF->getContext().createNamedTempSymbol("tlsdesc_hi");
727
728 MachineInstr *MIAUIPC =
729 BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol);
730 MIAUIPC->setPreInstrSymbol(*MF, AUIPCSymbol);
731
732 BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
733 .addReg(ScratchReg)
734 .addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_LOAD_LO);
735
736 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), RISCV::X10)
737 .addReg(ScratchReg)
738 .addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_ADD_LO);
739
740 BuildMI(MBB, MBBI, DL, TII->get(RISCV::PseudoTLSDESCCall), RISCV::X5)
741 .addReg(DestReg)
742 .addImm(0)
743 .addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_CALL);
744
745 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADD), FinalReg)
746 .addReg(RISCV::X10)
747 .addReg(RISCV::X4);
748
749 MI.eraseFromParent();
750 return true;
751}
752
753} // end of anonymous namespace
754
755INITIALIZE_PASS(RISCVExpandPseudo, "riscv-expand-pseudo",
756 RISCV_EXPAND_PSEUDO_NAME, false, false)
757
758INITIALIZE_PASS(RISCVPreRAExpandPseudo, "riscv-prera-expand-pseudo",
759 RISCV_PRERA_EXPAND_PSEUDO_NAME, false, false)
760
761namespace llvm {
762
763FunctionPass *createRISCVExpandPseudoPass() { return new RISCVExpandPseudo(); }
764FunctionPass *createRISCVPreRAExpandPseudoPass() { return new RISCVPreRAExpandPseudo(); }
765
766} // end of namespace llvm
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
MBB
MachineBasicBlock & MBB
Definition ARMSLSHardening.cpp:71
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition ARMSLSHardening.cpp:73
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition ARMSLSHardening.cpp:72
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
TII
const HexagonInstrInfo * TII
Definition HexagonCopyToCombine.cpp:118
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:110
LivePhysRegs.h
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
TRI
Register const TargetRegisterInfo * TRI
Definition MachineSink.cpp:2118
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition PassSupport.h:56
RISCV_PRERA_EXPAND_PSEUDO_NAME
#define RISCV_PRERA_EXPAND_PSEUDO_NAME
Definition RISCVExpandPseudoInsts.cpp:27
RISCV_EXPAND_PSEUDO_NAME
#define RISCV_EXPAND_PSEUDO_NAME
Definition RISCVExpandPseudoInsts.cpp:26
getInstSizeInBytes
static unsigned getInstSizeInBytes(const MachineInstr &MI, const SystemZInstrInfo *TII)
Definition SystemZLongBranch.cpp:211
Mul
BinaryOperator * Mul
Definition X86PartialReduction.cpp:68
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition PassAnalysisSupport.h:48
llvm::AnalysisUsage::setPreservesCFG
LLVM_ABI void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition Pass.cpp:270
llvm::DebugLoc
A debug info location.
Definition DebugLoc.h:124
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition Pass.h:314
llvm::LivePhysRegs
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition LivePhysRegs.h:52
llvm::MCContext::createNamedTempSymbol
LLVM_ABI MCSymbol * createNamedTempSymbol()
Create a temporary symbol with a unique name whose name cannot be omitted in the symbol table.
Definition MCContext.cpp:395
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition MCInstrDesc.h:210
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition MCSymbol.h:42
llvm::MachineBasicBlock::transferSuccessors
LLVM_ABI void transferSuccessors(MachineBasicBlock *FromMBB)
Transfers all the successors from MBB to this machine basic block (i.e., copies all the successors Fr...
Definition MachineBasicBlock.cpp:935
llvm::MachineBasicBlock::addSuccessor
LLVM_ABI void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition MachineBasicBlock.cpp:816
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition MachineBasicBlock.h:1156
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition MachineBasicBlock.h:341
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition MachineFunctionPass.h:31
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition MachineFunctionPass.cpp:184
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition MachineFunction.h:762
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition MachineFunction.cpp:536
llvm::MachineFunction::getContext
MCContext & getContext() const
Definition MachineFunction.h:719
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition MachineFunction.h:772
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)
CreateMachineInstr - Allocate a new MachineInstr.
Definition MachineFunction.cpp:499
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition MachineFunction.h:1003
llvm::MachineInstrBuilder::setMemRefs
const MachineInstrBuilder & setMemRefs(ArrayRef< MachineMemOperand * > MMOs) const
Definition MachineInstrBuilder.h:237
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition MachineInstrBuilder.h:160
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition MachineInstrBuilder.h:253
llvm::MachineInstrBuilder::addSym
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
Definition MachineInstrBuilder.h:295
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition MachineInstrBuilder.h:126
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition MachineInstrBuilder.h:175
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition MachineInstrBuilder.h:145
llvm::MachineInstr
Representation of each machine instruction.
Definition MachineInstr.h:72
llvm::MachineInstr::setPreInstrSymbol
LLVM_ABI void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
Definition MachineInstr.cpp:478
llvm::MachineInstr::addMemOperand
LLVM_ABI void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
Definition MachineInstr.cpp:383
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition MachineMemOperand.h:130
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition MachineOperand.h:48
llvm::MachineRegisterInfo::createVirtualRegister
LLVM_ABI Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition MachineRegisterInfo.cpp:156
llvm::RISCVSubtarget::getRegisterInfo
const RISCVRegisterInfo * getRegisterInfo() const override
Definition RISCVSubtarget.h:142
llvm::RISCVSubtarget::getInstrInfo
const RISCVInstrInfo * getInstrInfo() const override
Definition RISCVSubtarget.h:141
llvm::Register
Wrapper class representing virtual and physical registers.
Definition Register.h:19
llvm::SmallVectorTemplateBase::push_back
void push_back(const T &Elt)
Definition SmallVector.h:416
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition SmallVector.h:1196
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition StringRef.h:55
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition TargetRegisterInfo.h:237
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition ilist_node.h:123
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition ErrorHandling.h:164
INITIALIZE_PASS
TargetPassConfig.
Definition TargetPassConfig.cpp:375
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition CallingConv.h:24
llvm::RISCVCC::getInverseBranchCondition
CondCode getInverseBranchCondition(CondCode)
Definition RISCVInstrInfo.cpp:1168
llvm::RISCVCC::getBrCond
unsigned getBrCond(CondCode CC, unsigned SelectOpc=0)
Definition RISCVInstrInfo.cpp:1057
llvm::RISCVVType::encodeLMUL
static VLMUL encodeLMUL(unsigned LMUL, bool Fractional)
Definition RISCVTargetParser.h:113
llvm::RISCVVType::encodeVTYPE
LLVM_ABI unsigned encodeVTYPE(VLMUL VLMUL, unsigned SEW, bool TailAgnostic, bool MaskAgnostic, bool AltFmt=false)
Definition RISCVTargetParser.cpp:161
llvm::RegState::Define
@ Define
Register definition.
Definition MachineInstrBuilder.h:47
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition MachineInstrBuilder.h:51
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition MachineInstrBuilder.h:55
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition AddressRanges.h:18
llvm::Offset
@ Offset
Definition DWP.cpp:477
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition MachineInstrBuilder.h:369
llvm::isInt
constexpr bool isInt(int64_t x)
Checks if an integer fits into the given bit width.
Definition MathExtras.h:174
llvm::Desc
Op::Description Desc
Definition DWARFExpressionPrinter.cpp:23
llvm::getImm
MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)
Definition SPIRVUtils.cpp:990
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition MachineInstrBuilder.h:543
llvm::computeAndAddLiveIns
void computeAndAddLiveIns(LivePhysRegs &LiveRegs, MachineBasicBlock &MBB)
Convenience function combining computeLiveIns() and addLiveIns().
Definition LivePhysRegs.cpp:345
llvm::createRISCVExpandPseudoPass
FunctionPass * createRISCVExpandPseudoPass()
Definition RISCVExpandPseudoInsts.cpp:763
llvm::createRISCVPreRAExpandPseudoPass
FunctionPass * createRISCVPreRAExpandPseudoPass()
Definition RISCVExpandPseudoInsts.cpp:764
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