#include "RISCVInstrInfo.h"
#include "MCTargetDesc/RISCVBaseInfo.h"
#include "MCTargetDesc/RISCVMatInt.h"
#include "RISCV.h"
#include "RISCVMachineFunctionInfo.h"
#include "RISCVSubtarget.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/MemoryLocation.h"
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineCombinerPattern.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineTraceMetrics.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/CodeGen/StackMaps.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/IR/Module.h"
#include "llvm/MC/MCInstBuilder.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/ErrorHandling.h"
#include "RISCVGenCompressInstEmitter.inc"
#include "RISCVGenInstrInfo.inc"
#include "RISCVGenSearchableTables.inc"

Namespaces
namespace	llvm
	This is an optimization pass for GlobalISel generic memory operations.

namespace	llvm::RISCVVPseudosTable

namespace	llvm::RISCV

Macros
#define	GEN_CHECK_COMPRESS_INSTR

#define	GET_INSTRINFO_CTOR_DTOR

#define	GET_INSTRINFO_NAMED_OPS

#define	DEBUG_TYPE "riscv-instr-info"

#define	GET_RISCVVPseudosTable_IMPL

#define	GET_RISCVMaskedPseudosTable_IMPL

#define	GET_INSTRINFO_HELPERS

#define	OPCODE_LMUL_CASE(OPC)

#define	OPCODE_LMUL_MASK_CASE(OPC)

#define	RVV_OPC_LMUL_CASE(OPC, INV)

#define	RVV_OPC_LMUL_MASK_CASE(OPC, INV)

#define	CASE_OPERAND_UIMM(NUM)

#define	CASE_OPERAND_SIMM(NUM)

#define	CASE_RVV_OPCODE_UNMASK_LMUL(OP, LMUL) RISCV::Pseudo##OP##_##LMUL

#define	CASE_RVV_OPCODE_MASK_LMUL(OP, LMUL) RISCV::Pseudo##OP##_##LMUL##_MASK

#define	CASE_RVV_OPCODE_LMUL(OP, LMUL)

#define	CASE_RVV_OPCODE_UNMASK_WIDEN(OP)

#define	CASE_RVV_OPCODE_UNMASK(OP)

#define	CASE_RVV_OPCODE_MASK_WIDEN(OP)

#define	CASE_RVV_OPCODE_MASK(OP)

#define	CASE_RVV_OPCODE_WIDEN(OP)

#define	CASE_RVV_OPCODE(OP)

#define	CASE_VMA_OPCODE_COMMON(OP, TYPE, LMUL) RISCV::PseudoV##OP##_##TYPE##_##LMUL

#define	CASE_VMA_OPCODE_LMULS(OP, TYPE)

#define	CASE_VFMA_OPCODE_COMMON(OP, TYPE, LMUL, SEW) RISCV::PseudoV##OP##_##TYPE##_##LMUL##_##SEW

#define	CASE_VFMA_OPCODE_LMULS_M1(OP, TYPE, SEW)

#define	CASE_VFMA_OPCODE_LMULS_MF2(OP, TYPE, SEW)

#define	CASE_VFMA_OPCODE_LMULS_MF4(OP, TYPE, SEW)

#define	CASE_VFMA_OPCODE_VV(OP)

#define	CASE_VFMA_SPLATS(OP)

#define	CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, LMUL)

#define	CASE_VMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, TYPE)

#define	CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, LMUL, SEW)

#define	CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, TYPE, SEW)

#define	CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, TYPE, SEW)

#define	CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, TYPE, SEW)

#define	CASE_VFMA_CHANGE_OPCODE_VV(OLDOP, NEWOP)

#define	CASE_VFMA_CHANGE_OPCODE_SPLATS(OLDOP, NEWOP)

#define	CASE_WIDEOP_OPCODE_COMMON(OP, LMUL) RISCV::PseudoV##OP##_##LMUL##_TIED

#define	CASE_WIDEOP_OPCODE_LMULS(OP)

#define	CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, LMUL)

#define	CASE_WIDEOP_CHANGE_OPCODE_LMULS(OP)

#define	CASE_FP_WIDEOP_OPCODE_COMMON(OP, LMUL, SEW) RISCV::PseudoV##OP##_##LMUL##_##SEW##_TIED

#define	CASE_FP_WIDEOP_OPCODE_LMULS(OP)

#define	CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, LMUL, SEW)

#define	CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS(OP)

Enumerations
enum	MachineOutlinerConstructionID { MachineOutlinerTailCall , MachineOutlinerDefault }

Functions
	STATISTIC (NumVRegSpilled, "Number of registers within vector register groups spilled")

	STATISTIC (NumVRegReloaded, "Number of registers within vector register groups reloaded")

static std::optional< unsigned >	getLMULForRVVWholeLoadStore (unsigned Opcode)

static bool	forwardCopyWillClobberTuple (unsigned DstReg, unsigned SrcReg, unsigned NumRegs)

static bool	isConvertibleToVMV_V_V (const RISCVSubtarget &STI, const MachineBasicBlock &MBB, MachineBasicBlock::const_iterator MBBI, MachineBasicBlock::const_iterator &DefMBBI, RISCVVType::VLMUL LMul)

std::optional< unsigned >	getFoldedOpcode (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, const RISCVSubtarget &ST)

static void	parseCondBranch (MachineInstr &LastInst, MachineBasicBlock *&Target, SmallVectorImpl< MachineOperand > &Cond)

static bool	isLoadImm (const MachineInstr *MI, int64_t &Imm)

unsigned	getPredicatedOpcode (unsigned Opcode)

static MachineInstr *	canFoldAsPredicatedOp (Register Reg, const MachineRegisterInfo &MRI, const TargetInstrInfo *TII)
	Identify instructions that can be folded into a CCMOV instruction, and return the defining instruction.

static bool	isFADD (unsigned Opc)

static bool	isFSUB (unsigned Opc)

static bool	isFMUL (unsigned Opc)

static bool	canCombineFPFusedMultiply (const MachineInstr &Root, const MachineOperand &MO, bool DoRegPressureReduce)

static bool	getFPFusedMultiplyPatterns (MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce)

static bool	getFPPatterns (MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce)

static const MachineInstr *	canCombine (const MachineBasicBlock &MBB, const MachineOperand &MO, unsigned CombineOpc)
	Utility routine that checks if.

static bool	canCombineShiftIntoShXAdd (const MachineBasicBlock &MBB, const MachineOperand &MO, unsigned OuterShiftAmt)
	Utility routine that checks if.

static unsigned	getSHXADDShiftAmount (unsigned Opc)

static unsigned	getSHXADDUWShiftAmount (unsigned Opc)

static bool	getSHXADDPatterns (const MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns)

static unsigned	getFPFusedMultiplyOpcode (unsigned RootOpc, unsigned Pattern)

static unsigned	getAddendOperandIdx (unsigned Pattern)

static void	combineFPFusedMultiply (MachineInstr &Root, MachineInstr &Prev, unsigned Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs)

static void	genShXAddAddShift (MachineInstr &Root, unsigned AddOpIdx, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< Register, unsigned > &InstrIdxForVirtReg)

static bool	memOpsHaveSameBasePtr (const MachineInstr &MI1, ArrayRef< const MachineOperand * > BaseOps1, const MachineInstr &MI2, ArrayRef< const MachineOperand * > BaseOps2)

static bool	isCandidatePatchable (const MachineBasicBlock &MBB)

static bool	isMIReadsReg (const MachineInstr &MI, const TargetRegisterInfo *TRI, MCRegister RegNo)

static bool	isMIModifiesReg (const MachineInstr &MI, const TargetRegisterInfo *TRI, MCRegister RegNo)

static bool	cannotInsertTailCall (const MachineBasicBlock &MBB)

static bool	analyzeCandidate (outliner::Candidate &C)

Variables
static cl::opt< bool >	PreferWholeRegisterMove ("riscv-prefer-whole-register-move", cl::init(false), cl::Hidden, cl::desc("Prefer whole register move for vector registers."))

static cl::opt< MachineTraceStrategy >	ForceMachineCombinerStrategy ("riscv-force-machine-combiner-strategy", cl::Hidden, cl::desc("Force machine combiner to use a specific strategy for machine " "trace metrics evaluation."), cl::init(MachineTraceStrategy::TS_NumStrategies), cl::values(clEnumValN(MachineTraceStrategy::TS_Local, "local", "Local strategy."), clEnumValN(MachineTraceStrategy::TS_MinInstrCount, "min-instr", "MinInstrCount strategy.")))

Macro Definition Documentation

◆ CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON

#define CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON	(	OP,
		LMUL,
		SEW
	)

Value:

  case RISCV::PseudoV##OP##_##LMUL##_##SEW##_TIED:                             \
    NewOpc = RISCV::PseudoV##OP##_##LMUL##_##SEW;                              \
    break;

Definition at line 4352 of file RISCVInstrInfo.cpp.

◆ CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS

#define CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS ( OP )

Value:

  CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF4, E16)                            \
  CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF2, E16)                            \
  CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF2, E32)                            \
  CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M1, E16)                             \
  CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M1, E32)                             \
  CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M2, E16)                             \
  CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M2, E32)                             \
  CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M4, E16)                             \
  CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M4, E32)                             \

Definition at line 4357 of file RISCVInstrInfo.cpp.

◆ CASE_FP_WIDEOP_OPCODE_COMMON

#define CASE_FP_WIDEOP_OPCODE_COMMON	(	OP,
		LMUL,
		SEW
	)	RISCV::PseudoV##OP##_##LMUL##_##SEW##_TIED

Definition at line 4338 of file RISCVInstrInfo.cpp.

◆ CASE_FP_WIDEOP_OPCODE_LMULS

#define CASE_FP_WIDEOP_OPCODE_LMULS ( OP )

Value:

  CASE_FP_WIDEOP_OPCODE_COMMON(OP, MF4, E16):                                  \
  case CASE_FP_WIDEOP_OPCODE_COMMON(OP, MF2, E16):                             \
  case CASE_FP_WIDEOP_OPCODE_COMMON(OP, MF2, E32):                             \
  case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M1, E16):                              \
  case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M1, E32):                              \
  case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M2, E16):                              \
  case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M2, E32):                              \
  case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M4, E16):                              \
  case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M4, E32)                               \

Definition at line 4341 of file RISCVInstrInfo.cpp.

◆ CASE_OPERAND_SIMM

#define CASE_OPERAND_SIMM ( NUM )

Value:

  case RISCVOp::OPERAND_SIMM##NUM:                                             \
    Ok = isInt<NUM>(Imm);                                                      \
    break;

◆ CASE_OPERAND_UIMM

#define CASE_OPERAND_UIMM ( NUM )

Value:

  case RISCVOp::OPERAND_UIMM##NUM:                                             \
    Ok = isUInt<NUM>(Imm);                                                     \
    break;

◆ CASE_RVV_OPCODE

#define CASE_RVV_OPCODE ( OP )

Value:

CASE_RVV_OPCODE_UNMASK(OP): \

case CASE_RVV_OPCODE_MASK(OP)

CASE_RVV_OPCODE_UNMASK

#define CASE_RVV_OPCODE_UNMASK(OP)

Definition: RISCVInstrInfo.cpp:3655

CASE_RVV_OPCODE_MASK

#define CASE_RVV_OPCODE_MASK(OP)

Definition: RISCVInstrInfo.cpp:3667

Definition at line 3675 of file RISCVInstrInfo.cpp.

◆ CASE_RVV_OPCODE_LMUL

#define CASE_RVV_OPCODE_LMUL	(	OP,
		LMUL
	)

Value:

CASE_RVV_OPCODE_UNMASK_LMUL(OP, LMUL): \

case CASE_RVV_OPCODE_MASK_LMUL(OP, LMUL)

CASE_RVV_OPCODE_UNMASK_LMUL

#define CASE_RVV_OPCODE_UNMASK_LMUL(OP, LMUL)

Definition: RISCVInstrInfo.cpp:3637

CASE_RVV_OPCODE_MASK_LMUL

#define CASE_RVV_OPCODE_MASK_LMUL(OP, LMUL)

Definition: RISCVInstrInfo.cpp:3640

Definition at line 3643 of file RISCVInstrInfo.cpp.

◆ CASE_RVV_OPCODE_MASK

#define CASE_RVV_OPCODE_MASK ( OP )

Value:

CASE_RVV_OPCODE_MASK_WIDEN(OP): \

case CASE_RVV_OPCODE_MASK_LMUL(OP, M8)

CASE_RVV_OPCODE_MASK_WIDEN

#define CASE_RVV_OPCODE_MASK_WIDEN(OP)

Definition: RISCVInstrInfo.cpp:3659

Definition at line 3667 of file RISCVInstrInfo.cpp.

◆ CASE_RVV_OPCODE_MASK_LMUL

#define CASE_RVV_OPCODE_MASK_LMUL	(	OP,
		LMUL
	)	RISCV::Pseudo##OP##_##LMUL##_MASK

Definition at line 3640 of file RISCVInstrInfo.cpp.

◆ CASE_RVV_OPCODE_MASK_WIDEN

#define CASE_RVV_OPCODE_MASK_WIDEN ( OP )

Value:

  CASE_RVV_OPCODE_MASK_LMUL(OP, MF8):                                         \
  case CASE_RVV_OPCODE_MASK_LMUL(OP, MF4):                                    \
  case CASE_RVV_OPCODE_MASK_LMUL(OP, MF2):                                    \
  case CASE_RVV_OPCODE_MASK_LMUL(OP, M1):                                     \
  case CASE_RVV_OPCODE_MASK_LMUL(OP, M2):                                     \
  case CASE_RVV_OPCODE_MASK_LMUL(OP, M4)

Definition at line 3659 of file RISCVInstrInfo.cpp.

◆ CASE_RVV_OPCODE_UNMASK

#define CASE_RVV_OPCODE_UNMASK ( OP )

Value:

CASE_RVV_OPCODE_UNMASK_WIDEN(OP): \

case CASE_RVV_OPCODE_UNMASK_LMUL(OP, M8)

CASE_RVV_OPCODE_UNMASK_WIDEN

#define CASE_RVV_OPCODE_UNMASK_WIDEN(OP)

Definition: RISCVInstrInfo.cpp:3647

Definition at line 3655 of file RISCVInstrInfo.cpp.

◆ CASE_RVV_OPCODE_UNMASK_LMUL

#define CASE_RVV_OPCODE_UNMASK_LMUL	(	OP,
		LMUL
	)	RISCV::Pseudo##OP##_##LMUL

Definition at line 3637 of file RISCVInstrInfo.cpp.

◆ CASE_RVV_OPCODE_UNMASK_WIDEN

#define CASE_RVV_OPCODE_UNMASK_WIDEN ( OP )

Value:

  CASE_RVV_OPCODE_UNMASK_LMUL(OP, MF8):                                       \
  case CASE_RVV_OPCODE_UNMASK_LMUL(OP, MF4):                                  \
  case CASE_RVV_OPCODE_UNMASK_LMUL(OP, MF2):                                  \
  case CASE_RVV_OPCODE_UNMASK_LMUL(OP, M1):                                   \
  case CASE_RVV_OPCODE_UNMASK_LMUL(OP, M2):                                   \
  case CASE_RVV_OPCODE_UNMASK_LMUL(OP, M4)

Definition at line 3647 of file RISCVInstrInfo.cpp.

◆ CASE_RVV_OPCODE_WIDEN

#define CASE_RVV_OPCODE_WIDEN ( OP )

Value:

CASE_RVV_OPCODE_UNMASK_WIDEN(OP): \

case CASE_RVV_OPCODE_MASK_WIDEN(OP)

Definition at line 3671 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_CHANGE_OPCODE_COMMON

#define CASE_VFMA_CHANGE_OPCODE_COMMON	(	OLDOP,
		NEWOP,
		TYPE,
		LMUL,
		SEW
	)

Value:

  case RISCV::PseudoV##OLDOP##_##TYPE##_##LMUL##_##SEW:                        \
    Opc = RISCV::PseudoV##NEWOP##_##TYPE##_##LMUL##_##SEW;                     \
    break;

Definition at line 3902 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_CHANGE_OPCODE_LMULS_M1

#define CASE_VFMA_CHANGE_OPCODE_LMULS_M1	(	OLDOP,
		NEWOP,
		TYPE,
		SEW
	)

Value:

  CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M1, SEW)                  \
  CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M2, SEW)                  \
  CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M4, SEW)                  \
  CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M8, SEW)

Definition at line 3907 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_CHANGE_OPCODE_LMULS_MF2

#define CASE_VFMA_CHANGE_OPCODE_LMULS_MF2	(	OLDOP,
		NEWOP,
		TYPE,
		SEW
	)

Value:

CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF2, SEW) \

CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, TYPE, SEW)

Definition at line 3913 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_CHANGE_OPCODE_LMULS_MF4

#define CASE_VFMA_CHANGE_OPCODE_LMULS_MF4	(	OLDOP,
		NEWOP,
		TYPE,
		SEW
	)

Value:

CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF4, SEW) \

CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, TYPE, SEW)

Definition at line 3917 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_CHANGE_OPCODE_SPLATS

#define CASE_VFMA_CHANGE_OPCODE_SPLATS	(	OLDOP,
		NEWOP
	)

Value:

  CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, VFPR16, E16)                 \
  CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, VFPR32, E32)                 \
  CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, VFPR64, E64)

Definition at line 3926 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_CHANGE_OPCODE_VV

#define CASE_VFMA_CHANGE_OPCODE_VV	(	OLDOP,
		NEWOP
	)

Value:

  CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, VV, E16)                     \
  CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, VV, E32)                     \
  CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, VV, E64)

Definition at line 3921 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_OPCODE_COMMON

#define CASE_VFMA_OPCODE_COMMON	(	OP,
		TYPE,
		LMUL,
		SEW
	)	RISCV::PseudoV##OP##_##TYPE##_##LMUL##_##SEW

Definition at line 3694 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_OPCODE_LMULS_M1

#define CASE_VFMA_OPCODE_LMULS_M1	(	OP,
		TYPE,
		SEW
	)

Value:

  CASE_VFMA_OPCODE_COMMON(OP, TYPE, M1, SEW):                                  \
  case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M2, SEW):                             \
  case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M4, SEW):                             \
  case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M8, SEW)

Definition at line 3697 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_OPCODE_LMULS_MF2

#define CASE_VFMA_OPCODE_LMULS_MF2	(	OP,
		TYPE,
		SEW
	)

Value:

CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF2, SEW): \

case CASE_VFMA_OPCODE_LMULS_M1(OP, TYPE, SEW)

CASE_VFMA_OPCODE_LMULS_M1

#define CASE_VFMA_OPCODE_LMULS_M1(OP, TYPE, SEW)

Definition: RISCVInstrInfo.cpp:3697

Definition at line 3703 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_OPCODE_LMULS_MF4

#define CASE_VFMA_OPCODE_LMULS_MF4	(	OP,
		TYPE,
		SEW
	)

Value:

CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF4, SEW): \

case CASE_VFMA_OPCODE_LMULS_MF2(OP, TYPE, SEW)

CASE_VFMA_OPCODE_LMULS_MF2

#define CASE_VFMA_OPCODE_LMULS_MF2(OP, TYPE, SEW)

Definition: RISCVInstrInfo.cpp:3703

Definition at line 3707 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_OPCODE_VV

#define CASE_VFMA_OPCODE_VV ( OP )

Value:

  CASE_VFMA_OPCODE_LMULS_MF4(OP, VV, E16):                                     \
  case CASE_VFMA_OPCODE_LMULS_MF2(OP, VV, E32):                                \
  case CASE_VFMA_OPCODE_LMULS_M1(OP, VV, E64)

Definition at line 3711 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_SPLATS

#define CASE_VFMA_SPLATS ( OP )

Value:

  CASE_VFMA_OPCODE_LMULS_MF4(OP, VFPR16, E16):                                 \
  case CASE_VFMA_OPCODE_LMULS_MF2(OP, VFPR32, E32):                            \
  case CASE_VFMA_OPCODE_LMULS_M1(OP, VFPR64, E64)

Definition at line 3716 of file RISCVInstrInfo.cpp.

◆ CASE_VMA_CHANGE_OPCODE_COMMON

#define CASE_VMA_CHANGE_OPCODE_COMMON	(	OLDOP,
		NEWOP,
		TYPE,
		LMUL
	)

Value:

  case RISCV::PseudoV##OLDOP##_##TYPE##_##LMUL:                                \
    Opc = RISCV::PseudoV##NEWOP##_##TYPE##_##LMUL;                             \
    break;

Definition at line 3887 of file RISCVInstrInfo.cpp.

◆ CASE_VMA_CHANGE_OPCODE_LMULS

#define CASE_VMA_CHANGE_OPCODE_LMULS	(	OLDOP,
		NEWOP,
		TYPE
	)

Value:

  CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF8)                       \
  CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF4)                       \
  CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF2)                       \
  CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M1)                        \
  CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M2)                        \
  CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M4)                        \
  CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M8)

Definition at line 3892 of file RISCVInstrInfo.cpp.

◆ CASE_VMA_OPCODE_COMMON

#define CASE_VMA_OPCODE_COMMON	(	OP,
		TYPE,
		LMUL
	)	RISCV::PseudoV##OP##_##TYPE##_##LMUL

Definition at line 3681 of file RISCVInstrInfo.cpp.

◆ CASE_VMA_OPCODE_LMULS

#define CASE_VMA_OPCODE_LMULS	(	OP,
		TYPE
	)

Value:

  CASE_VMA_OPCODE_COMMON(OP, TYPE, MF8):                                       \
  case CASE_VMA_OPCODE_COMMON(OP, TYPE, MF4):                                  \
  case CASE_VMA_OPCODE_COMMON(OP, TYPE, MF2):                                  \
  case CASE_VMA_OPCODE_COMMON(OP, TYPE, M1):                                   \
  case CASE_VMA_OPCODE_COMMON(OP, TYPE, M2):                                   \
  case CASE_VMA_OPCODE_COMMON(OP, TYPE, M4):                                   \
  case CASE_VMA_OPCODE_COMMON(OP, TYPE, M8)

Definition at line 3684 of file RISCVInstrInfo.cpp.

◆ CASE_WIDEOP_CHANGE_OPCODE_COMMON

#define CASE_WIDEOP_CHANGE_OPCODE_COMMON	(	OP,
		LMUL
	)

Value:

  case RISCV::PseudoV##OP##_##LMUL##_TIED:                                     \
    NewOpc = RISCV::PseudoV##OP##_##LMUL;                                      \
    break;

Definition at line 4324 of file RISCVInstrInfo.cpp.

◆ CASE_WIDEOP_CHANGE_OPCODE_LMULS

#define CASE_WIDEOP_CHANGE_OPCODE_LMULS ( OP )

Value:

  CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF8)                                    \
  CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF4)                                    \
  CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF2)                                    \
  CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, M1)                                     \
  CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, M2)                                     \
  CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, M4)

Definition at line 4329 of file RISCVInstrInfo.cpp.

◆ CASE_WIDEOP_OPCODE_COMMON

#define CASE_WIDEOP_OPCODE_COMMON	(	OP,
		LMUL
	)	RISCV::PseudoV##OP##_##LMUL##_TIED

Definition at line 4313 of file RISCVInstrInfo.cpp.

◆ CASE_WIDEOP_OPCODE_LMULS

#define CASE_WIDEOP_OPCODE_LMULS ( OP )

Value:

  CASE_WIDEOP_OPCODE_COMMON(OP, MF8):                                          \
  case CASE_WIDEOP_OPCODE_COMMON(OP, MF4):                                     \
  case CASE_WIDEOP_OPCODE_COMMON(OP, MF2):                                     \
  case CASE_WIDEOP_OPCODE_COMMON(OP, M1):                                      \
  case CASE_WIDEOP_OPCODE_COMMON(OP, M2):                                      \
  case CASE_WIDEOP_OPCODE_COMMON(OP, M4)

Definition at line 4316 of file RISCVInstrInfo.cpp.

◆ DEBUG_TYPE

#define DEBUG_TYPE "riscv-instr-info"

Definition at line 47 of file RISCVInstrInfo.cpp.

◆ GEN_CHECK_COMPRESS_INSTR

#define GEN_CHECK_COMPRESS_INSTR

Definition at line 40 of file RISCVInstrInfo.cpp.

◆ GET_INSTRINFO_CTOR_DTOR

#define GET_INSTRINFO_CTOR_DTOR

Definition at line 43 of file RISCVInstrInfo.cpp.

◆ GET_INSTRINFO_HELPERS

#define GET_INSTRINFO_HELPERS

Definition at line 87 of file RISCVInstrInfo.cpp.

◆ GET_INSTRINFO_NAMED_OPS

#define GET_INSTRINFO_NAMED_OPS

Definition at line 44 of file RISCVInstrInfo.cpp.

◆ GET_RISCVMaskedPseudosTable_IMPL

#define GET_RISCVMaskedPseudosTable_IMPL

Definition at line 78 of file RISCVInstrInfo.cpp.

◆ GET_RISCVVPseudosTable_IMPL

#define GET_RISCVVPseudosTable_IMPL

Definition at line 71 of file RISCVInstrInfo.cpp.

◆ OPCODE_LMUL_CASE

#define OPCODE_LMUL_CASE ( OPC )

Value:

  case RISCV::OPC##_M1:                                                        \
  case RISCV::OPC##_M2:                                                        \
  case RISCV::OPC##_M4:                                                        \
  case RISCV::OPC##_M8:                                                        \
  case RISCV::OPC##_MF2:                                                       \
  case RISCV::OPC##_MF4:                                                       \
  case RISCV::OPC##_MF8

◆ OPCODE_LMUL_MASK_CASE

#define OPCODE_LMUL_MASK_CASE ( OPC )

Value:

  case RISCV::OPC##_M1_MASK:                                                   \
  case RISCV::OPC##_M2_MASK:                                                   \
  case RISCV::OPC##_M4_MASK:                                                   \
  case RISCV::OPC##_M8_MASK:                                                   \
  case RISCV::OPC##_MF2_MASK:                                                  \
  case RISCV::OPC##_MF4_MASK:                                                  \
  case RISCV::OPC##_MF8_MASK

◆ RVV_OPC_LMUL_CASE

#define RVV_OPC_LMUL_CASE	(	OPC,
		INV
	)

Value:

  case RISCV::OPC##_M1:                                                        \
    return RISCV::INV##_M1;                                                    \
  case RISCV::OPC##_M2:                                                        \
    return RISCV::INV##_M2;                                                    \
  case RISCV::OPC##_M4:                                                        \
    return RISCV::INV##_M4;                                                    \
  case RISCV::OPC##_M8:                                                        \
    return RISCV::INV##_M8;                                                    \
  case RISCV::OPC##_MF2:                                                       \
    return RISCV::INV##_MF2;                                                   \
  case RISCV::OPC##_MF4:                                                       \
    return RISCV::INV##_MF4;                                                   \
  case RISCV::OPC##_MF8:                                                       \
    return RISCV::INV##_MF8

◆ RVV_OPC_LMUL_MASK_CASE

#define RVV_OPC_LMUL_MASK_CASE	(	OPC,
		INV
	)

Value:

  case RISCV::OPC##_M1_MASK:                                                   \
    return RISCV::INV##_M1_MASK;                                               \
  case RISCV::OPC##_M2_MASK:                                                   \
    return RISCV::INV##_M2_MASK;                                               \
  case RISCV::OPC##_M4_MASK:                                                   \
    return RISCV::INV##_M4_MASK;                                               \
  case RISCV::OPC##_M8_MASK:                                                   \
    return RISCV::INV##_M8_MASK;                                               \
  case RISCV::OPC##_MF2_MASK:                                                  \
    return RISCV::INV##_MF2_MASK;                                              \
  case RISCV::OPC##_MF4_MASK:                                                  \
    return RISCV::INV##_MF4_MASK;                                              \
  case RISCV::OPC##_MF8_MASK:                                                  \
    return RISCV::INV##_MF8_MASK

Enumeration Type Documentation

◆ MachineOutlinerConstructionID

enum MachineOutlinerConstructionID

Enumerator
MachineOutlinerTailCall
MachineOutlinerDefault

Definition at line 3365 of file RISCVInstrInfo.cpp.

Function Documentation

◆ analyzeCandidate()

static bool analyzeCandidate ( outliner::Candidate & C )

static

Definition at line 3415 of file RISCVInstrInfo.cpp.

References llvm::any_of(), assert(), llvm::CallingConv::C, cannotInsertTailCall(), isMIModifiesReg(), MI, and TRI.

Referenced by llvm::RISCVInstrInfo::getOutliningCandidateInfo().

◆ canCombine()

static const MachineInstr * canCombine	(	const MachineBasicBlock &	MBB,
		const MachineOperand &	MO,
		unsigned	CombineOpc
	)

static

Utility routine that checks if.

Parameters

MO	is defined by an
CombineOpc	instruction in the basic block
MBB

Definition at line 2476 of file RISCVInstrInfo.cpp.

References llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineOperand::isReg(), llvm::Register::isVirtual(), MBB, MI, and MRI.

◆ canCombineFPFusedMultiply()

static bool canCombineFPFusedMultiply	(	const MachineInstr &	Root,
		const MachineOperand &	MO,
		bool	DoRegPressureReduce
	)

static

Definition at line 2418 of file RISCVInstrInfo.cpp.

References llvm::MachineInstr::FmContract, llvm::MachineInstr::getFlag(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::RISCV::hasEqualFRM(), isFMUL(), llvm::MachineOperand::isReg(), llvm::Register::isVirtual(), MI, and MRI.

Referenced by getFPFusedMultiplyPatterns().

◆ canCombineShiftIntoShXAdd()

static bool canCombineShiftIntoShXAdd	(	const MachineBasicBlock &	MBB,
		const MachineOperand &	MO,
		unsigned	OuterShiftAmt
	)

static

Utility routine that checks if.

Parameters

MO	is defined by a SLLI in
MBB	that can be combined by splitting across 2 SHXADD instructions. The first SHXADD shift amount is given by
OuterShiftAmt.

Definition at line 2497 of file RISCVInstrInfo.cpp.

References canCombine(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOperand(), and MBB.

Referenced by getSHXADDPatterns().

◆ canFoldAsPredicatedOp()

static MachineInstr * canFoldAsPredicatedOp	(	Register	Reg,
		const MachineRegisterInfo &	MRI,
		const TargetInstrInfo *	TII
	)

static

Identify instructions that can be folded into a CCMOV instruction, and return the defining instruction.

Definition at line 1683 of file RISCVInstrInfo.cpp.

References llvm::drop_begin(), getPredicatedOpcode(), MI, and MRI.

Referenced by llvm::RISCVInstrInfo::optimizeSelect().

◆ cannotInsertTailCall()

static bool cannotInsertTailCall ( const MachineBasicBlock & MBB )

static

Definition at line 3394 of file RISCVInstrInfo.cpp.

References llvm::MachineBasicBlock::back(), llvm::MCSubtargetInfo::getFeatureBits(), llvm::MachineBasicBlock::getParent(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::RISCVII::getTailExpandUseRegNo(), isCandidatePatchable(), isMIModifiesReg(), isMIReadsReg(), llvm::MachineInstr::isReturn(), MBB, and MI.

Referenced by analyzeCandidate(), and llvm::RISCVInstrInfo::getOutliningTypeImpl().

◆ combineFPFusedMultiply()

static void combineFPFusedMultiply	(	MachineInstr &	Root,
		MachineInstr &	Prev,
		unsigned	Pattern,
		SmallVectorImpl< MachineInstr * > &	InsInstrs,
		SmallVectorImpl< MachineInstr * > &	DelInstrs
	)

static

◆ forwardCopyWillClobberTuple()

static bool forwardCopyWillClobberTuple	(	unsigned	DstReg,
		unsigned	SrcReg,
		unsigned	NumRegs
	)

static

Definition at line 250 of file RISCVInstrInfo.cpp.

◆ genShXAddAddShift()

static void genShXAddAddShift	(	MachineInstr &	Root,
		unsigned	AddOpIdx,
		SmallVectorImpl< MachineInstr * > &	InsInstrs,
		SmallVectorImpl< MachineInstr * > &	DelInstrs,
		DenseMap< Register, unsigned > &	InstrIdxForVirtReg
	)

static

◆ getAddendOperandIdx()

static unsigned getAddendOperandIdx ( unsigned Pattern )

static

Definition at line 2616 of file RISCVInstrInfo.cpp.

References llvm::FMADD_AX, llvm::FMADD_XA, llvm::FMSUB, llvm::FNMSUB, and llvm_unreachable.

Referenced by combineFPFusedMultiply().

◆ getFoldedOpcode()

std::optional< unsigned > getFoldedOpcode	(	MachineFunction &	MF,
		MachineInstr &	MI,
		ArrayRef< unsigned >	Ops,
		const RISCVSubtarget &	ST
	)

Definition at line 802 of file RISCVInstrInfo.cpp.

References llvm::MachineFunction::getDataLayout(), llvm::RISCV::getRVVMCOpcode(), llvm::RISCVII::getSEWOpNum(), llvm::DataLayout::isBigEndian(), llvm_unreachable, MI, and llvm::ArrayRef< T >::size().

Referenced by llvm::RISCVInstrInfo::foldMemoryOperandImpl().

◆ getFPFusedMultiplyOpcode()

static unsigned getFPFusedMultiplyOpcode	(	unsigned	RootOpc,
		unsigned	Pattern
	)

static

Definition at line 2594 of file RISCVInstrInfo.cpp.

References llvm::FMSUB, and llvm_unreachable.

Referenced by combineFPFusedMultiply().

◆ getFPFusedMultiplyPatterns()

static bool getFPFusedMultiplyPatterns	(	MachineInstr &	Root,
		SmallVectorImpl< unsigned > &	Patterns,
		bool	DoRegPressureReduce
	)

static

Definition at line 2445 of file RISCVInstrInfo.cpp.

References canCombineFPFusedMultiply(), llvm::FMADD_AX, llvm::FMADD_XA, llvm::FMSUB, llvm::FNMSUB, llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), isFADD(), isFSUB(), Opc, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced by getFPPatterns().

◆ getFPPatterns()

static bool getFPPatterns	(	MachineInstr &	Root,
		SmallVectorImpl< unsigned > &	Patterns,
		bool	DoRegPressureReduce
	)

static

Definition at line 2468 of file RISCVInstrInfo.cpp.

References getFPFusedMultiplyPatterns().

Referenced by llvm::RISCVInstrInfo::getMachineCombinerPatterns().

◆ getLMULForRVVWholeLoadStore()

static std::optional< unsigned > getLMULForRVVWholeLoadStore ( unsigned Opcode )

static

Definition at line 105 of file RISCVInstrInfo.cpp.

Referenced by llvm::RISCVInstrInfo::isLoadFromStackSlot(), llvm::RISCV::isRVVSpill(), and llvm::RISCVInstrInfo::isStoreToStackSlot().

◆ getPredicatedOpcode()

unsigned getPredicatedOpcode ( unsigned Opcode )

Definition at line 1640 of file RISCVInstrInfo.cpp.

Referenced by canFoldAsPredicatedOp(), and llvm::RISCVInstrInfo::optimizeSelect().

◆ getSHXADDPatterns()

static bool getSHXADDPatterns	(	const MachineInstr &	Root,
		SmallVectorImpl< unsigned > &	Patterns
	)

static

Definition at line 2543 of file RISCVInstrInfo.cpp.

References canCombine(), canCombineShiftIntoShXAdd(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), getSHXADDShiftAmount(), MBB, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SHXADD_ADD_SLLI_OP1, and llvm::SHXADD_ADD_SLLI_OP2.

Referenced by llvm::RISCVInstrInfo::getMachineCombinerPatterns().

◆ getSHXADDShiftAmount()

static unsigned getSHXADDShiftAmount ( unsigned Opc )

static

Definition at line 2513 of file RISCVInstrInfo.cpp.

References Opc.

Referenced by genShXAddAddShift(), getSHXADDPatterns(), and llvm::RISCVInstrInfo::simplifyInstruction().

◆ getSHXADDUWShiftAmount()

static unsigned getSHXADDUWShiftAmount ( unsigned Opc )

static

Definition at line 2528 of file RISCVInstrInfo.cpp.

References Opc.

Referenced by llvm::RISCVInstrInfo::simplifyInstruction().

◆ isCandidatePatchable()

static bool isCandidatePatchable ( const MachineBasicBlock & MBB )

static

Definition at line 3375 of file RISCVInstrInfo.cpp.

References F, llvm::MachineFunction::getFunction(), llvm::MachineBasicBlock::getParent(), and MBB.

Referenced by cannotInsertTailCall().

◆ isConvertibleToVMV_V_V()

static bool isConvertibleToVMV_V_V	(	const RISCVSubtarget &	STI,
		const MachineBasicBlock &	MBB,
		MachineBasicBlock::const_iterator	MBBI,
		MachineBasicBlock::const_iterator &	DefMBBI,
		RISCVVType::VLMUL	LMul
	)

static

Definition at line 255 of file RISCVInstrInfo.cpp.

References assert(), llvm::MachineBasicBlock::begin(), llvm::RISCVSubtarget::getRegisterInfo(), llvm::RISCVVType::getSEW(), llvm::RISCVVType::getVLMUL(), llvm::RISCVII::hasSEWOp(), llvm::RISCVII::hasVLOp(), llvm::RISCVII::isRVVWideningReduction(), llvm::RISCVVType::isTailAgnostic(), MBB, MBBI, PreferWholeRegisterMove, and TRI.

Referenced by llvm::RISCVInstrInfo::copyPhysRegVector().

◆ isFADD()

static bool isFADD ( unsigned Opc )

static

Definition at line 2020 of file RISCVInstrInfo.cpp.

References Opc.

Referenced by getFPFusedMultiplyPatterns(), and llvm::RISCVInstrInfo::isAssociativeAndCommutative().

◆ isFMUL()

static bool isFMUL ( unsigned Opc )

static

Definition at line 2042 of file RISCVInstrInfo.cpp.

References Opc.

Referenced by canCombineFPFusedMultiply(), and llvm::RISCVInstrInfo::isAssociativeAndCommutative().

◆ isFSUB()

static bool isFSUB ( unsigned Opc )

static

Definition at line 2031 of file RISCVInstrInfo.cpp.

References Opc.

Referenced by getFPFusedMultiplyPatterns().

◆ isLoadImm()

static bool isLoadImm	(	const MachineInstr *	MI,
		int64_t &	Imm
	)

static

Definition at line 1438 of file RISCVInstrInfo.cpp.

References MI.

Referenced by llvm::RISCVInstrInfo::isFromLoadImm(), and llvm::RISCVInstrInfo::optimizeCondBranch().

◆ isMIModifiesReg()

static bool isMIModifiesReg	(	const MachineInstr &	MI,
		const TargetRegisterInfo *	TRI,
		MCRegister	RegNo
	)

static

Definition at line 3388 of file RISCVInstrInfo.cpp.

References MI, and TRI.

Referenced by analyzeCandidate(), cannotInsertTailCall(), and llvm::RISCVInstrInfo::getOutliningTypeImpl().

◆ isMIReadsReg()

static bool isMIReadsReg	(	const MachineInstr &	MI,
		const TargetRegisterInfo *	TRI,
		MCRegister	RegNo
	)

static

Definition at line 3382 of file RISCVInstrInfo.cpp.

References MI, and TRI.

Referenced by cannotInsertTailCall().

◆ memOpsHaveSameBasePtr()

static bool memOpsHaveSameBasePtr	(	const MachineInstr &	MI1,
		ArrayRef< const MachineOperand * >	BaseOps1,
		const MachineInstr &	MI2,
		ArrayRef< const MachineOperand * >	BaseOps2
	)

static

Definition at line 3192 of file RISCVInstrInfo.cpp.

References llvm::ArrayRef< T >::front(), llvm::getUnderlyingObject(), llvm::MachineInstr::hasOneMemOperand(), and llvm::MachineInstr::memoperands_begin().

◆ parseCondBranch()

static void parseCondBranch	(	MachineInstr &	LastInst,
		MachineBasicBlock *&	Target,
		SmallVectorImpl< MachineOperand > &	Cond
	)

static

Definition at line 1013 of file RISCVInstrInfo.cpp.

References assert(), Cond, llvm::MachineOperand::CreateImm(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MCInstrDesc::isConditionalBranch().

◆ STATISTIC() [1/2]

STATISTIC	(	NumVRegReloaded	,
		"Number of registers within vector register groups reloaded"
	)

◆ STATISTIC() [2/2]

STATISTIC	(	NumVRegSpilled	,
		"Number of registers within vector register groups spilled"
	)

Variable Documentation

◆ ForceMachineCombinerStrategy

cl::opt< MachineTraceStrategy > ForceMachineCombinerStrategy("riscv-force-machine-combiner-strategy", cl::Hidden, cl::desc("Force machine combiner to use a specific strategy for machine " "trace metrics evaluation."), cl::init(MachineTraceStrategy::TS_NumStrategies), cl::values(clEnumValN(MachineTraceStrategy::TS_Local, "local", "Local strategy."), clEnumValN(MachineTraceStrategy::TS_MinInstrCount, "min-instr", "MinInstrCount strategy.")))	(	"riscv-force-machine-combiner-strategy"	,
		cl::Hidden	,
		cl::desc("Force machine combiner to use a specific strategy for machine " "trace metrics evaluation.")	,
		cl::init(MachineTraceStrategy::TS_NumStrategies)	,
		cl::values(clEnumValN(MachineTraceStrategy::TS_Local, "local", "Local strategy."), clEnumValN(MachineTraceStrategy::TS_MinInstrCount, "min-instr", "MinInstrCount strategy."))
	)

static

Referenced by llvm::RISCVInstrInfo::getMachineCombinerTraceStrategy().

◆ PreferWholeRegisterMove

cl::opt< bool > PreferWholeRegisterMove("riscv-prefer-whole-register-move", cl::init(false), cl::Hidden, cl::desc("Prefer whole register move for vector registers."))	(	"riscv-prefer-whole-register-move"	,
		cl::init(false)	,
		cl::Hidden	,
		cl::desc("Prefer whole register move for vector registers.")
	)

static

Referenced by isConvertibleToVMV_V_V().

Namespaces

Macros

Enumerations

Functions

Variables

Macro Definition Documentation

◆ CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON

◆ CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS

◆ CASE_FP_WIDEOP_OPCODE_COMMON

◆ CASE_FP_WIDEOP_OPCODE_LMULS

◆ CASE_OPERAND_SIMM

◆ CASE_OPERAND_UIMM

◆ CASE_RVV_OPCODE

◆ CASE_RVV_OPCODE_LMUL

◆ CASE_RVV_OPCODE_MASK

◆ CASE_RVV_OPCODE_MASK_LMUL

◆ CASE_RVV_OPCODE_MASK_WIDEN

◆ CASE_RVV_OPCODE_UNMASK

◆ CASE_RVV_OPCODE_UNMASK_LMUL

◆ CASE_RVV_OPCODE_UNMASK_WIDEN

◆ CASE_RVV_OPCODE_WIDEN

◆ CASE_VFMA_CHANGE_OPCODE_COMMON

◆ CASE_VFMA_CHANGE_OPCODE_LMULS_M1

◆ CASE_VFMA_CHANGE_OPCODE_LMULS_MF2

◆ CASE_VFMA_CHANGE_OPCODE_LMULS_MF4

◆ CASE_VFMA_CHANGE_OPCODE_SPLATS

◆ CASE_VFMA_CHANGE_OPCODE_VV

◆ CASE_VFMA_OPCODE_COMMON

◆ CASE_VFMA_OPCODE_LMULS_M1

◆ CASE_VFMA_OPCODE_LMULS_MF2

◆ CASE_VFMA_OPCODE_LMULS_MF4

◆ CASE_VFMA_OPCODE_VV

◆ CASE_VFMA_SPLATS

◆ CASE_VMA_CHANGE_OPCODE_COMMON

◆ CASE_VMA_CHANGE_OPCODE_LMULS

◆ CASE_VMA_OPCODE_COMMON

◆ CASE_VMA_OPCODE_LMULS

◆ CASE_WIDEOP_CHANGE_OPCODE_COMMON

◆ CASE_WIDEOP_CHANGE_OPCODE_LMULS

◆ CASE_WIDEOP_OPCODE_COMMON

◆ CASE_WIDEOP_OPCODE_LMULS

◆ DEBUG_TYPE

◆ GEN_CHECK_COMPRESS_INSTR

◆ GET_INSTRINFO_CTOR_DTOR

◆ GET_INSTRINFO_HELPERS

◆ GET_INSTRINFO_NAMED_OPS

◆ GET_RISCVMaskedPseudosTable_IMPL

◆ GET_RISCVVPseudosTable_IMPL

◆ OPCODE_LMUL_CASE

◆ OPCODE_LMUL_MASK_CASE

◆ RVV_OPC_LMUL_CASE

◆ RVV_OPC_LMUL_MASK_CASE

Enumeration Type Documentation

◆ MachineOutlinerConstructionID

Function Documentation

◆ analyzeCandidate()

◆ canCombine()

◆ canCombineFPFusedMultiply()

◆ canCombineShiftIntoShXAdd()

◆ canFoldAsPredicatedOp()

◆ cannotInsertTailCall()

◆ combineFPFusedMultiply()

◆ forwardCopyWillClobberTuple()

◆ genShXAddAddShift()

◆ getAddendOperandIdx()

◆ getFoldedOpcode()

◆ getFPFusedMultiplyOpcode()

◆ getFPFusedMultiplyPatterns()

◆ getFPPatterns()

◆ getLMULForRVVWholeLoadStore()

◆ getPredicatedOpcode()

◆ getSHXADDPatterns()

◆ getSHXADDShiftAmount()

◆ getSHXADDUWShiftAmount()

◆ isCandidatePatchable()

◆ isConvertibleToVMV_V_V()

◆ isFADD()

◆ isFMUL()

◆ isFSUB()

◆ isLoadImm()