24#include "llvm/Config/llvm-config.h"
38#define DEBUG_TYPE "pre-RA-sched"
40STATISTIC(NumNewPredsAdded,
"Number of times a single predecessor was added");
42 "Number of times the topological order has been recomputed");
47 cl::desc(
"Stress test instruction scheduling"));
50void SchedulingPriorityQueue::anchor() {}
53 : TM(mf.getTarget()),
TII(mf.getSubtarget().getInstrInfo()),
54 TRI(mf.getSubtarget().getRegisterInfo()), MF(mf),
55 MRI(mf.getRegInfo()) {
70 if (!Node || !Node->isMachineOpcode())
return nullptr;
71 return &
TII->
get(Node->getMachineOpcode());
94 switch(Contents.OrdKind) {
111 if (!
Required && PredDep.getSUnit() ==
D.getSUnit())
113 if (PredDep.overlaps(
D)) {
116 if (PredDep.getLatency() <
D.getLatency()) {
117 SUnit *PredSU = PredDep.getSUnit();
119 SDep ForwardD = PredDep;
122 if (SuccDep == ForwardD) {
127 PredDep.setLatency(
D.getLatency());
142 "NumPreds will overflow!");
143 assert(
N->NumSuccs < std::numeric_limits<unsigned>::max() &&
144 "NumSuccs will overflow!");
148 if (!
N->isScheduled) {
154 "NumPredsLeft will overflow!");
163 assert(
N->NumSuccsLeft < std::numeric_limits<unsigned>::max() &&
164 "NumSuccsLeft will overflow!");
169 N->Succs.push_back(
P);
185 assert(Succ !=
N->Succs.end() &&
"Mismatching preds / succs lists!");
189 assert(
N->NumSuccs > 0 &&
"NumSuccs will underflow!");
193 if (!
N->isScheduled) {
204 assert(
N->WeakSuccsLeft > 0 &&
"WeakSuccsLeft will underflow!");
207 assert(
N->NumSuccsLeft > 0 &&
"NumSuccsLeft will underflow!");
211 N->Succs.erase(Succ);
218 if (!isDepthCurrent)
return;
223 SU->isDepthCurrent =
false;
226 if (SuccSU->isDepthCurrent)
229 }
while (!WorkList.
empty());
233 if (!isHeightCurrent)
return;
238 SU->isHeightCurrent =
false;
241 if (PredSU->isHeightCurrent)
244 }
while (!WorkList.
empty());
252 isDepthCurrent =
true;
260 isHeightCurrent =
true;
264void SUnit::ComputeDepth() {
271 unsigned MaxPredDepth = 0;
274 if (PredSU->isDepthCurrent)
275 MaxPredDepth = std::max(MaxPredDepth,
285 if (MaxPredDepth != Cur->Depth) {
287 Cur->Depth = MaxPredDepth;
289 Cur->isDepthCurrent =
true;
291 }
while (!WorkList.
empty());
295void SUnit::ComputeHeight() {
302 unsigned MaxSuccHeight = 0;
305 if (SuccSU->isHeightCurrent)
306 MaxSuccHeight = std::max(MaxSuccHeight,
316 if (MaxSuccHeight != Cur->Height) {
318 Cur->Height = MaxSuccHeight;
320 Cur->isHeightCurrent =
true;
322 }
while (!WorkList.
empty());
330 unsigned MaxDepth = BestI->getSUnit()->getDepth();
333 if (
I->getKind() ==
SDep::Data &&
I->getSUnit()->getDepth() > MaxDepth) {
334 MaxDepth =
I->getSUnit()->getDepth();
338 if (BestI !=
Preds.begin())
342#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
371 if (SU.
Preds.size() > 0) {
372 dbgs() <<
" Predecessors:\n";
381 if (SU.
Succs.size() > 0) {
382 dbgs() <<
" Successors:\n";
396 bool AnyNotSched =
false;
397 unsigned DeadNodes = 0;
405 dbgs() <<
"*** Scheduling failed! ***\n";
407 dbgs() <<
"has not been scheduled!\n";
412 unsigned(std::numeric_limits<int>::max())) {
414 dbgs() <<
"*** Scheduling failed! ***\n";
416 dbgs() <<
"has an unexpected "
417 << (isBottomUp ?
"Height" :
"Depth") <<
" value!\n";
423 dbgs() <<
"*** Scheduling failed! ***\n";
425 dbgs() <<
"has successors left!\n";
431 dbgs() <<
"*** Scheduling failed! ***\n";
433 dbgs() <<
"has predecessors left!\n";
439 return SUnits.size() - DeadNodes;
475 unsigned DAGSize = SUnits.size();
476 std::vector<SUnit*> WorkList;
479 Index2Node.resize(DAGSize);
480 Node2Index.resize(DAGSize);
484 WorkList.push_back(ExitSU);
485 for (
SUnit &SU : SUnits) {
486 int NodeNum = SU.NodeNum;
487 unsigned Degree = SU.Succs.size();
489 Node2Index[NodeNum] = Degree;
493 assert(SU.Succs.empty() &&
"SUnit should have no successors");
495 WorkList.push_back(&SU);
500 while (!WorkList.empty()) {
501 SUnit *SU = WorkList.back();
510 WorkList.push_back(SU);
519 for (
SUnit &SU : SUnits) {
520 for (
const SDep &PD : SU.Preds) {
521 assert(Node2Index[SU.NodeNum] > Node2Index[PD.getSUnit()->NodeNum] &&
522 "Wrong topological sorting");
528void ScheduleDAGTopologicalSort::FixOrder() {
536 for (
auto &U : Updates)
545 Dirty = Dirty || Updates.size() > 10;
550 Updates.emplace_back(
Y,
X);
554 int UpperBound, LowerBound;
555 LowerBound = Node2Index[
Y->NodeNum];
556 UpperBound = Node2Index[
X->NodeNum];
557 bool HasLoop =
false;
559 if (LowerBound < UpperBound) {
562 DFS(
Y, UpperBound, HasLoop);
563 assert(!HasLoop &&
"Inserted edge creates a loop!");
565 Shift(Visited, LowerBound, UpperBound);
575void ScheduleDAGTopologicalSort::DFS(
const SUnit *SU,
int UpperBound,
577 std::vector<const SUnit*> WorkList;
578 WorkList.
reserve(SUnits.size());
580 WorkList.push_back(SU);
582 SU = WorkList.back();
588 if (s >= Node2Index.size())
590 if (Node2Index[s] == UpperBound) {
595 if (!Visited.
test(s) && Node2Index[s] < UpperBound) {
596 WorkList.push_back(SuccDep.
getSUnit());
599 }
while (!WorkList.empty());
603 const SUnit &TargetSU,
605 std::vector<const SUnit*> WorkList;
606 int LowerBound = Node2Index[StartSU.
NodeNum];
607 int UpperBound = Node2Index[TargetSU.
NodeNum];
610 std::vector<int> Nodes;
612 if (LowerBound > UpperBound) {
617 WorkList.reserve(SUnits.size());
624 const SUnit *SU = WorkList.back();
627 const SUnit *Succ = SD.getSUnit();
632 if (Node2Index[s] == UpperBound) {
637 if (!Visited.
test(s) && Node2Index[s] < UpperBound) {
642 }
while (!WorkList.empty());
650 VisitedBack.
resize(SUnits.size());
656 WorkList.push_back(&TargetSU);
658 const SUnit *SU = WorkList.back();
661 const SUnit *Pred = SD.getSUnit();
666 if (Node2Index[s] == LowerBound) {
670 if (!VisitedBack.
test(s) && Visited.
test(s)) {
676 }
while (!WorkList.empty());
678 assert(Found &&
"Error in SUnit Graph!");
683void ScheduleDAGTopologicalSort::Shift(
BitVector& Visited,
int LowerBound,
689 for (i = LowerBound; i <= UpperBound; ++i) {
691 int w = Index2Node[i];
692 if (Visited.
test(w)) {
698 Allocate(w, i - shift);
702 for (
unsigned LI : L) {
703 Allocate(LI, i - shift);
713 for (
const SDep &PredDep : TargetSU->
Preds)
721 assert(SU->
NodeNum == Index2Node.size() &&
"Node cannot be added at the end");
722 assert(SU->
NumPreds == 0 &&
"Can only add SU's with no predecessors");
723 Node2Index.push_back(Index2Node.size());
724 Index2Node.push_back(SU->
NodeNum);
725 Visited.
resize(Node2Index.size());
729 const SUnit *TargetSU) {
730 assert(TargetSU !=
nullptr &&
"Invalid target SUnit");
731 assert(SU !=
nullptr &&
"Invalid SUnit");
735 int UpperBound, LowerBound;
736 LowerBound = Node2Index[TargetSU->
NodeNum];
737 UpperBound = Node2Index[SU->
NodeNum];
738 bool HasLoop =
false;
740 if (LowerBound < UpperBound) {
743 DFS(TargetSU, UpperBound, HasLoop);
748void ScheduleDAGTopologicalSort::Allocate(
int n,
int index) {
749 Node2Index[n] = index;
750 Index2Node[index] = n;
755 : SUnits(sunits), ExitSU(exitsu) {}
unsigned const MachineRegisterInfo * MRI
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
const HexagonInstrInfo * TII
Register const TargetRegisterInfo * TRI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
static cl::opt< bool > StressSchedOpt("stress-sched", cl::Hidden, cl::init(false), cl::desc("Stress test instruction scheduling"))
This file defines the SmallVector class.
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
bool test(unsigned Idx) const
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Describe properties that are true of each instruction in the target description file.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Represents one node in the SelectionDAG.
Kind getKind() const
Returns an enum value representing the kind of the dependence.
@ Output
A register output-dependence (aka WAW).
@ Order
Any other ordering dependency.
@ Anti
A register anti-dependence (aka WAR).
@ Data
Regular data dependence (aka true-dependence).
void setLatency(unsigned Lat)
Sets the latency for this edge.
@ Cluster
Weak DAG edge linking a chain of clustered instrs.
@ Barrier
An unknown scheduling barrier.
@ Artificial
Arbitrary strong DAG edge (no real dependence).
@ MayAliasMem
Nonvolatile load/Store instructions that may alias.
@ Weak
Arbitrary weak DAG edge.
@ MustAliasMem
Nonvolatile load/Store instructions that must alias.
unsigned getLatency() const
Returns the latency value for this edge, which roughly means the minimum number of cycles that must e...
bool isAssignedRegDep() const
Tests if this is a Data dependence that is associated with a register.
Register getReg() const
Returns the register associated with this edge.
LLVM_ABI void dump(const TargetRegisterInfo *TRI=nullptr) const
Scheduling unit. This is a node in the scheduling DAG.
LLVM_ABI void setHeightToAtLeast(unsigned NewHeight)
If NewHeight is greater than this node's height value, set it to be the new height value.
unsigned NodeNum
Entry # of node in the node vector.
LLVM_ABI void biasCriticalPath()
Orders this node's predecessor edges such that the critical path edge occurs first.
unsigned getHeight() const
Returns the height of this node, which is the length of the maximum path down to any node which has n...
LLVM_ABI void setHeightDirty()
Sets a flag in this node to indicate that its stored Height value will require recomputation the next...
LLVM_ABI void removePred(const SDep &D)
Removes the specified edge as a pred of the current node if it exists.
unsigned short Latency
Node latency.
SmallVectorImpl< SDep >::iterator pred_iterator
bool isBoundaryNode() const
Boundary nodes are placeholders for the boundary of the scheduling region.
unsigned short NumRegDefsLeft
unsigned getDepth() const
Returns the depth of this node, which is the length of the maximum path up to any node which has no p...
bool isScheduled
True once scheduled.
unsigned ParentClusterIdx
The parent cluster id.
LLVM_ABI void dumpAttributes() const
SmallVector< SDep, 4 > Succs
All sunit successors.
LLVM_ABI void setDepthDirty()
Sets a flag in this node to indicate that its stored Depth value will require recomputation the next ...
SmallVector< SDep, 4 > Preds
All sunit predecessors.
LLVM_ABI void setDepthToAtLeast(unsigned NewDepth)
If NewDepth is greater than this node's depth value, sets it to be the new depth value.
LLVM_ABI bool addPred(const SDep &D, bool Required=true)
Adds the specified edge as a pred of the current node if not already.
LLVM_ABI void RemovePred(SUnit *M, SUnit *N)
Updates the topological ordering to accommodate an edge to be removed from the specified node N from ...
LLVM_ABI bool WillCreateCycle(SUnit *TargetSU, SUnit *SU)
Returns true if addPred(TargetSU, SU) creates a cycle.
LLVM_ABI void AddSUnitWithoutPredecessors(const SUnit *SU)
Add a SUnit without predecessors to the end of the topological order.
LLVM_ABI ScheduleDAGTopologicalSort(std::vector< SUnit > &SUnits, SUnit *ExitSU)
LLVM_ABI std::vector< int > GetSubGraph(const SUnit &StartSU, const SUnit &TargetSU, bool &Success)
Returns an array of SUs that are both in the successor subtree of StartSU and in the predecessor subt...
LLVM_ABI void InitDAGTopologicalSorting()
Creates the initial topological ordering from the DAG to be scheduled.
LLVM_ABI void AddPred(SUnit *Y, SUnit *X)
Updates the topological ordering to accommodate an edge to be added from SUnit X to SUnit Y.
LLVM_ABI bool IsReachable(const SUnit *SU, const SUnit *TargetSU)
Checks if SU is reachable from TargetSU.
LLVM_ABI void AddPredQueued(SUnit *Y, SUnit *X)
Queues an update to the topological ordering to accommodate an edge to be added from SUnit X to SUnit...
void clearDAG()
Clears the DAG state (between regions).
const TargetInstrInfo * TII
Target instruction information.
std::vector< SUnit > SUnits
The scheduling units.
const TargetRegisterInfo * TRI
Target processor register info.
SUnit EntrySU
Special node for the region entry.
ScheduleDAG(const ScheduleDAG &)=delete
void dumpNodeAll(const SUnit &SU) const
unsigned VerifyScheduledDAG(bool isBottomUp)
Verifies that all SUnits were scheduled and that their state is consistent.
virtual void dumpNode(const SUnit &SU) const =0
void dumpNodeName(const SUnit &SU) const
SUnit ExitSU
Special node for the region exit.
virtual ~ScheduleHazardRecognizer()
void reserve(size_type N)
typename SuperClass::iterator iterator
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
auto find(R &&Range, const T &Val)
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly.
auto reverse(ContainerTy &&C)
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
@ Success
The lock was released successfully.
constexpr unsigned InvalidClusterId
LLVM_ABI Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.