LLVM 22.0.0git
X86MCTargetDesc.cpp
Go to the documentation of this file.
1//===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides X86 specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
13#include "X86MCTargetDesc.h"
14#include "TargetInfo/X86TargetInfo.h"
15#include "X86ATTInstPrinter.h"
16#include "X86BaseInfo.h"
17#include "X86IntelInstPrinter.h"
18#include "X86MCAsmInfo.h"
19#include "X86TargetStreamer.h"
20#include "llvm-c/Visibility.h"
21#include "llvm/ADT/APInt.h"
22#include "llvm/DebugInfo/CodeView/CodeView.h"
23#include "llvm/MC/MCDwarf.h"
24#include "llvm/MC/MCInstrAnalysis.h"
25#include "llvm/MC/MCInstrInfo.h"
26#include "llvm/MC/MCRegisterInfo.h"
27#include "llvm/MC/MCStreamer.h"
28#include "llvm/MC/MCSubtargetInfo.h"
29#include "llvm/MC/TargetRegistry.h"
30#include "llvm/Support/ErrorHandling.h"
31#include "llvm/TargetParser/Host.h"
32#include "llvm/TargetParser/Triple.h"
33
34using namespace llvm;
35
36#define GET_REGINFO_MC_DESC
37#include "X86GenRegisterInfo.inc"
38
39#define GET_INSTRINFO_MC_DESC
40#define GET_INSTRINFO_MC_HELPERS
41#define ENABLE_INSTR_PREDICATE_VERIFIER
42#include "X86GenInstrInfo.inc"
43
44#define GET_SUBTARGETINFO_MC_DESC
45#include "X86GenSubtargetInfo.inc"
46
47std::string X86_MC::ParseX86Triple(const Triple &TT) {
48 std::string FS;
49 // SSE2 should default to enabled in 64-bit mode, but can be turned off
50 // explicitly.
51 if (TT.isArch64Bit())
52 FS = "+64bit-mode,-32bit-mode,-16bit-mode,+sse2";
53 else if (TT.getEnvironment() != Triple::CODE16)
54 FS = "-64bit-mode,+32bit-mode,-16bit-mode";
55 else
56 FS = "-64bit-mode,-32bit-mode,+16bit-mode";
57
58 return FS;
59}
60
61unsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) {
62 if (TT.getArch() == Triple::x86_64)
63 return DWARFFlavour::X86_64;
64
65 if (TT.isOSDarwin())
66 return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic;
67 if (TT.isOSCygMing())
68 // Unsupported by now, just quick fallback
69 return DWARFFlavour::X86_32_Generic;
70 return DWARFFlavour::X86_32_Generic;
71}
72
73bool X86_MC::hasLockPrefix(const MCInst &MI) {
74 return MI.getFlags() & X86::IP_HAS_LOCK;
75}
76
77static bool isMemOperand(const MCInst &MI, unsigned Op, unsigned RegClassID) {
78 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg);
79 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg);
80 const MCRegisterClass &RC = X86MCRegisterClasses[RegClassID];
81
82 return (Base.isReg() && Base.getReg() && RC.contains(Base.getReg())) ||
83 (Index.isReg() && Index.getReg() && RC.contains(Index.getReg()));
84}
85
86bool X86_MC::is16BitMemOperand(const MCInst &MI, unsigned Op,
87 const MCSubtargetInfo &STI) {
88 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg);
89 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg);
90
91 if (STI.hasFeature(X86::Is16Bit) && Base.isReg() && !Base.getReg() &&
92 Index.isReg() && !Index.getReg())
93 return true;
94 return isMemOperand(MI, Op, X86::GR16RegClassID);
95}
96
97bool X86_MC::is32BitMemOperand(const MCInst &MI, unsigned Op) {
98 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg);
99 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg);
100 if (Base.isReg() && Base.getReg() == X86::EIP) {
101 assert(Index.isReg() && !Index.getReg() && "Invalid eip-based address");
102 return true;
103 }
104 if (Index.isReg() && Index.getReg() == X86::EIZ)
105 return true;
106 return isMemOperand(MI, Op, X86::GR32RegClassID);
107}
108
109#ifndef NDEBUG
110bool X86_MC::is64BitMemOperand(const MCInst &MI, unsigned Op) {
111 return isMemOperand(MI, Op, X86::GR64RegClassID);
112}
113#endif
114
115bool X86_MC::needsAddressSizeOverride(const MCInst &MI,
116 const MCSubtargetInfo &STI,
117 int MemoryOperand, uint64_t TSFlags) {
118 uint64_t AdSize = TSFlags & X86II::AdSizeMask;
119 bool Is16BitMode = STI.hasFeature(X86::Is16Bit);
120 bool Is32BitMode = STI.hasFeature(X86::Is32Bit);
121 bool Is64BitMode = STI.hasFeature(X86::Is64Bit);
122 if ((Is16BitMode && AdSize == X86II::AdSize32) ||
123 (Is32BitMode && AdSize == X86II::AdSize16) ||
124 (Is64BitMode && AdSize == X86II::AdSize32))
125 return true;
126 uint64_t Form = TSFlags & X86II::FormMask;
127 switch (Form) {
128 default:
129 break;
130 case X86II::RawFrmDstSrc: {
131 MCRegister siReg = MI.getOperand(1).getReg();
132 assert(((siReg == X86::SI && MI.getOperand(0).getReg() == X86::DI) ||
133 (siReg == X86::ESI && MI.getOperand(0).getReg() == X86::EDI) ||
134 (siReg == X86::RSI && MI.getOperand(0).getReg() == X86::RDI)) &&
135 "SI and DI register sizes do not match");
136 return (!Is32BitMode && siReg == X86::ESI) ||
137 (Is32BitMode && siReg == X86::SI);
138 }
139 case X86II::RawFrmSrc: {
140 MCRegister siReg = MI.getOperand(0).getReg();
141 return (!Is32BitMode && siReg == X86::ESI) ||
142 (Is32BitMode && siReg == X86::SI);
143 }
144 case X86II::RawFrmDst: {
145 MCRegister siReg = MI.getOperand(0).getReg();
146 return (!Is32BitMode && siReg == X86::EDI) ||
147 (Is32BitMode && siReg == X86::DI);
148 }
149 }
150
151 // Determine where the memory operand starts, if present.
152 if (MemoryOperand < 0)
153 return false;
154
155 if (STI.hasFeature(X86::Is64Bit)) {
156 assert(!is16BitMemOperand(MI, MemoryOperand, STI));
157 return is32BitMemOperand(MI, MemoryOperand);
158 }
159 if (STI.hasFeature(X86::Is32Bit)) {
160 assert(!is64BitMemOperand(MI, MemoryOperand));
161 return is16BitMemOperand(MI, MemoryOperand, STI);
162 }
163 assert(STI.hasFeature(X86::Is16Bit));
164 assert(!is64BitMemOperand(MI, MemoryOperand));
165 return !is16BitMemOperand(MI, MemoryOperand, STI);
166}
167
168void X86_MC::initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI) {
169 // FIXME: TableGen these.
170 for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
171 unsigned SEH = MRI->getEncodingValue(Reg);
172 MRI->mapLLVMRegToSEHReg(Reg, SEH);
173 }
174
175 // Mapping from CodeView to MC register id.
176 static const struct {
177 codeview::RegisterId CVReg;
178 MCPhysReg Reg;
179 } RegMap[] = {
180 {codeview::RegisterId::AL, X86::AL},
181 {codeview::RegisterId::CL, X86::CL},
182 {codeview::RegisterId::DL, X86::DL},
183 {codeview::RegisterId::BL, X86::BL},
184 {codeview::RegisterId::AH, X86::AH},
185 {codeview::RegisterId::CH, X86::CH},
186 {codeview::RegisterId::DH, X86::DH},
187 {codeview::RegisterId::BH, X86::BH},
188 {codeview::RegisterId::AX, X86::AX},
189 {codeview::RegisterId::CX, X86::CX},
190 {codeview::RegisterId::DX, X86::DX},
191 {codeview::RegisterId::BX, X86::BX},
192 {codeview::RegisterId::SP, X86::SP},
193 {codeview::RegisterId::BP, X86::BP},
194 {codeview::RegisterId::SI, X86::SI},
195 {codeview::RegisterId::DI, X86::DI},
196 {codeview::RegisterId::EAX, X86::EAX},
197 {codeview::RegisterId::ECX, X86::ECX},
198 {codeview::RegisterId::EDX, X86::EDX},
199 {codeview::RegisterId::EBX, X86::EBX},
200 {codeview::RegisterId::ESP, X86::ESP},
201 {codeview::RegisterId::EBP, X86::EBP},
202 {codeview::RegisterId::ESI, X86::ESI},
203 {codeview::RegisterId::EDI, X86::EDI},
204
205 {codeview::RegisterId::EFLAGS, X86::EFLAGS},
206
207 {codeview::RegisterId::ST0, X86::ST0},
208 {codeview::RegisterId::ST1, X86::ST1},
209 {codeview::RegisterId::ST2, X86::ST2},
210 {codeview::RegisterId::ST3, X86::ST3},
211 {codeview::RegisterId::ST4, X86::ST4},
212 {codeview::RegisterId::ST5, X86::ST5},
213 {codeview::RegisterId::ST6, X86::ST6},
214 {codeview::RegisterId::ST7, X86::ST7},
215
216 {codeview::RegisterId::ST0, X86::FP0},
217 {codeview::RegisterId::ST1, X86::FP1},
218 {codeview::RegisterId::ST2, X86::FP2},
219 {codeview::RegisterId::ST3, X86::FP3},
220 {codeview::RegisterId::ST4, X86::FP4},
221 {codeview::RegisterId::ST5, X86::FP5},
222 {codeview::RegisterId::ST6, X86::FP6},
223 {codeview::RegisterId::ST7, X86::FP7},
224
225 {codeview::RegisterId::MM0, X86::MM0},
226 {codeview::RegisterId::MM1, X86::MM1},
227 {codeview::RegisterId::MM2, X86::MM2},
228 {codeview::RegisterId::MM3, X86::MM3},
229 {codeview::RegisterId::MM4, X86::MM4},
230 {codeview::RegisterId::MM5, X86::MM5},
231 {codeview::RegisterId::MM6, X86::MM6},
232 {codeview::RegisterId::MM7, X86::MM7},
233
234 {codeview::RegisterId::XMM0, X86::XMM0},
235 {codeview::RegisterId::XMM1, X86::XMM1},
236 {codeview::RegisterId::XMM2, X86::XMM2},
237 {codeview::RegisterId::XMM3, X86::XMM3},
238 {codeview::RegisterId::XMM4, X86::XMM4},
239 {codeview::RegisterId::XMM5, X86::XMM5},
240 {codeview::RegisterId::XMM6, X86::XMM6},
241 {codeview::RegisterId::XMM7, X86::XMM7},
242
243 {codeview::RegisterId::XMM8, X86::XMM8},
244 {codeview::RegisterId::XMM9, X86::XMM9},
245 {codeview::RegisterId::XMM10, X86::XMM10},
246 {codeview::RegisterId::XMM11, X86::XMM11},
247 {codeview::RegisterId::XMM12, X86::XMM12},
248 {codeview::RegisterId::XMM13, X86::XMM13},
249 {codeview::RegisterId::XMM14, X86::XMM14},
250 {codeview::RegisterId::XMM15, X86::XMM15},
251
252 {codeview::RegisterId::SIL, X86::SIL},
253 {codeview::RegisterId::DIL, X86::DIL},
254 {codeview::RegisterId::BPL, X86::BPL},
255 {codeview::RegisterId::SPL, X86::SPL},
256 {codeview::RegisterId::RAX, X86::RAX},
257 {codeview::RegisterId::RBX, X86::RBX},
258 {codeview::RegisterId::RCX, X86::RCX},
259 {codeview::RegisterId::RDX, X86::RDX},
260 {codeview::RegisterId::RSI, X86::RSI},
261 {codeview::RegisterId::RDI, X86::RDI},
262 {codeview::RegisterId::RBP, X86::RBP},
263 {codeview::RegisterId::RSP, X86::RSP},
264 {codeview::RegisterId::R8, X86::R8},
265 {codeview::RegisterId::R9, X86::R9},
266 {codeview::RegisterId::R10, X86::R10},
267 {codeview::RegisterId::R11, X86::R11},
268 {codeview::RegisterId::R12, X86::R12},
269 {codeview::RegisterId::R13, X86::R13},
270 {codeview::RegisterId::R14, X86::R14},
271 {codeview::RegisterId::R15, X86::R15},
272 {codeview::RegisterId::R8B, X86::R8B},
273 {codeview::RegisterId::R9B, X86::R9B},
274 {codeview::RegisterId::R10B, X86::R10B},
275 {codeview::RegisterId::R11B, X86::R11B},
276 {codeview::RegisterId::R12B, X86::R12B},
277 {codeview::RegisterId::R13B, X86::R13B},
278 {codeview::RegisterId::R14B, X86::R14B},
279 {codeview::RegisterId::R15B, X86::R15B},
280 {codeview::RegisterId::R8W, X86::R8W},
281 {codeview::RegisterId::R9W, X86::R9W},
282 {codeview::RegisterId::R10W, X86::R10W},
283 {codeview::RegisterId::R11W, X86::R11W},
284 {codeview::RegisterId::R12W, X86::R12W},
285 {codeview::RegisterId::R13W, X86::R13W},
286 {codeview::RegisterId::R14W, X86::R14W},
287 {codeview::RegisterId::R15W, X86::R15W},
288 {codeview::RegisterId::R8D, X86::R8D},
289 {codeview::RegisterId::R9D, X86::R9D},
290 {codeview::RegisterId::R10D, X86::R10D},
291 {codeview::RegisterId::R11D, X86::R11D},
292 {codeview::RegisterId::R12D, X86::R12D},
293 {codeview::RegisterId::R13D, X86::R13D},
294 {codeview::RegisterId::R14D, X86::R14D},
295 {codeview::RegisterId::R15D, X86::R15D},
296 {codeview::RegisterId::AMD64_YMM0, X86::YMM0},
297 {codeview::RegisterId::AMD64_YMM1, X86::YMM1},
298 {codeview::RegisterId::AMD64_YMM2, X86::YMM2},
299 {codeview::RegisterId::AMD64_YMM3, X86::YMM3},
300 {codeview::RegisterId::AMD64_YMM4, X86::YMM4},
301 {codeview::RegisterId::AMD64_YMM5, X86::YMM5},
302 {codeview::RegisterId::AMD64_YMM6, X86::YMM6},
303 {codeview::RegisterId::AMD64_YMM7, X86::YMM7},
304 {codeview::RegisterId::AMD64_YMM8, X86::YMM8},
305 {codeview::RegisterId::AMD64_YMM9, X86::YMM9},
306 {codeview::RegisterId::AMD64_YMM10, X86::YMM10},
307 {codeview::RegisterId::AMD64_YMM11, X86::YMM11},
308 {codeview::RegisterId::AMD64_YMM12, X86::YMM12},
309 {codeview::RegisterId::AMD64_YMM13, X86::YMM13},
310 {codeview::RegisterId::AMD64_YMM14, X86::YMM14},
311 {codeview::RegisterId::AMD64_YMM15, X86::YMM15},
312 {codeview::RegisterId::AMD64_YMM16, X86::YMM16},
313 {codeview::RegisterId::AMD64_YMM17, X86::YMM17},
314 {codeview::RegisterId::AMD64_YMM18, X86::YMM18},
315 {codeview::RegisterId::AMD64_YMM19, X86::YMM19},
316 {codeview::RegisterId::AMD64_YMM20, X86::YMM20},
317 {codeview::RegisterId::AMD64_YMM21, X86::YMM21},
318 {codeview::RegisterId::AMD64_YMM22, X86::YMM22},
319 {codeview::RegisterId::AMD64_YMM23, X86::YMM23},
320 {codeview::RegisterId::AMD64_YMM24, X86::YMM24},
321 {codeview::RegisterId::AMD64_YMM25, X86::YMM25},
322 {codeview::RegisterId::AMD64_YMM26, X86::YMM26},
323 {codeview::RegisterId::AMD64_YMM27, X86::YMM27},
324 {codeview::RegisterId::AMD64_YMM28, X86::YMM28},
325 {codeview::RegisterId::AMD64_YMM29, X86::YMM29},
326 {codeview::RegisterId::AMD64_YMM30, X86::YMM30},
327 {codeview::RegisterId::AMD64_YMM31, X86::YMM31},
328 {codeview::RegisterId::AMD64_ZMM0, X86::ZMM0},
329 {codeview::RegisterId::AMD64_ZMM1, X86::ZMM1},
330 {codeview::RegisterId::AMD64_ZMM2, X86::ZMM2},
331 {codeview::RegisterId::AMD64_ZMM3, X86::ZMM3},
332 {codeview::RegisterId::AMD64_ZMM4, X86::ZMM4},
333 {codeview::RegisterId::AMD64_ZMM5, X86::ZMM5},
334 {codeview::RegisterId::AMD64_ZMM6, X86::ZMM6},
335 {codeview::RegisterId::AMD64_ZMM7, X86::ZMM7},
336 {codeview::RegisterId::AMD64_ZMM8, X86::ZMM8},
337 {codeview::RegisterId::AMD64_ZMM9, X86::ZMM9},
338 {codeview::RegisterId::AMD64_ZMM10, X86::ZMM10},
339 {codeview::RegisterId::AMD64_ZMM11, X86::ZMM11},
340 {codeview::RegisterId::AMD64_ZMM12, X86::ZMM12},
341 {codeview::RegisterId::AMD64_ZMM13, X86::ZMM13},
342 {codeview::RegisterId::AMD64_ZMM14, X86::ZMM14},
343 {codeview::RegisterId::AMD64_ZMM15, X86::ZMM15},
344 {codeview::RegisterId::AMD64_ZMM16, X86::ZMM16},
345 {codeview::RegisterId::AMD64_ZMM17, X86::ZMM17},
346 {codeview::RegisterId::AMD64_ZMM18, X86::ZMM18},
347 {codeview::RegisterId::AMD64_ZMM19, X86::ZMM19},
348 {codeview::RegisterId::AMD64_ZMM20, X86::ZMM20},
349 {codeview::RegisterId::AMD64_ZMM21, X86::ZMM21},
350 {codeview::RegisterId::AMD64_ZMM22, X86::ZMM22},
351 {codeview::RegisterId::AMD64_ZMM23, X86::ZMM23},
352 {codeview::RegisterId::AMD64_ZMM24, X86::ZMM24},
353 {codeview::RegisterId::AMD64_ZMM25, X86::ZMM25},
354 {codeview::RegisterId::AMD64_ZMM26, X86::ZMM26},
355 {codeview::RegisterId::AMD64_ZMM27, X86::ZMM27},
356 {codeview::RegisterId::AMD64_ZMM28, X86::ZMM28},
357 {codeview::RegisterId::AMD64_ZMM29, X86::ZMM29},
358 {codeview::RegisterId::AMD64_ZMM30, X86::ZMM30},
359 {codeview::RegisterId::AMD64_ZMM31, X86::ZMM31},
360 {codeview::RegisterId::AMD64_K0, X86::K0},
361 {codeview::RegisterId::AMD64_K1, X86::K1},
362 {codeview::RegisterId::AMD64_K2, X86::K2},
363 {codeview::RegisterId::AMD64_K3, X86::K3},
364 {codeview::RegisterId::AMD64_K4, X86::K4},
365 {codeview::RegisterId::AMD64_K5, X86::K5},
366 {codeview::RegisterId::AMD64_K6, X86::K6},
367 {codeview::RegisterId::AMD64_K7, X86::K7},
368 {codeview::RegisterId::AMD64_XMM16, X86::XMM16},
369 {codeview::RegisterId::AMD64_XMM17, X86::XMM17},
370 {codeview::RegisterId::AMD64_XMM18, X86::XMM18},
371 {codeview::RegisterId::AMD64_XMM19, X86::XMM19},
372 {codeview::RegisterId::AMD64_XMM20, X86::XMM20},
373 {codeview::RegisterId::AMD64_XMM21, X86::XMM21},
374 {codeview::RegisterId::AMD64_XMM22, X86::XMM22},
375 {codeview::RegisterId::AMD64_XMM23, X86::XMM23},
376 {codeview::RegisterId::AMD64_XMM24, X86::XMM24},
377 {codeview::RegisterId::AMD64_XMM25, X86::XMM25},
378 {codeview::RegisterId::AMD64_XMM26, X86::XMM26},
379 {codeview::RegisterId::AMD64_XMM27, X86::XMM27},
380 {codeview::RegisterId::AMD64_XMM28, X86::XMM28},
381 {codeview::RegisterId::AMD64_XMM29, X86::XMM29},
382 {codeview::RegisterId::AMD64_XMM30, X86::XMM30},
383 {codeview::RegisterId::AMD64_XMM31, X86::XMM31},
384
385 };
386 for (const auto &I : RegMap)
387 MRI->mapLLVMRegToCVReg(I.Reg, static_cast<int>(I.CVReg));
388}
389
390MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT,
391 StringRef CPU, StringRef FS) {
392 std::string ArchFS = X86_MC::ParseX86Triple(TT);
393 assert(!ArchFS.empty() && "Failed to parse X86 triple");
394 if (!FS.empty())
395 ArchFS = (Twine(ArchFS) + "," + FS).str();
396
397 if (CPU.empty())
398 CPU = "generic";
399
400 return createX86MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, ArchFS);
401}
402
403static MCInstrInfo *createX86MCInstrInfo() {
404 MCInstrInfo *X = new MCInstrInfo();
405 InitX86MCInstrInfo(X);
406 return X;
407}
408
409static MCRegisterInfo *createX86MCRegisterInfo(const Triple &TT) {
410 unsigned RA = (TT.getArch() == Triple::x86_64)
411 ? X86::RIP // Should have dwarf #16.
412 : X86::EIP; // Should have dwarf #8.
413
414 MCRegisterInfo *X = new MCRegisterInfo();
415 InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false),
416 X86_MC::getDwarfRegFlavour(TT, true), RA);
417 X86_MC::initLLVMToSEHAndCVRegMapping(X);
418 return X;
419}
420
421static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI,
422 const Triple &TheTriple,
423 const MCTargetOptions &Options) {
424 bool is64Bit = TheTriple.getArch() == Triple::x86_64;
425
426 MCAsmInfo *MAI;
427 if (TheTriple.isOSBinFormatMachO()) {
428 if (is64Bit)
429 MAI = new X86_64MCAsmInfoDarwin(TheTriple);
430 else
431 MAI = new X86MCAsmInfoDarwin(TheTriple);
432 } else if (TheTriple.isOSBinFormatELF()) {
433 // Force the use of an ELF container.
434 MAI = new X86ELFMCAsmInfo(TheTriple);
435 } else if (TheTriple.isWindowsMSVCEnvironment() ||
436 TheTriple.isWindowsCoreCLREnvironment() || TheTriple.isUEFI()) {
437 if (Options.getAssemblyLanguage().equals_insensitive("masm"))
438 MAI = new X86MCAsmInfoMicrosoftMASM(TheTriple);
439 else
440 MAI = new X86MCAsmInfoMicrosoft(TheTriple);
441 } else if (TheTriple.isOSCygMing() ||
442 TheTriple.isWindowsItaniumEnvironment()) {
443 MAI = new X86MCAsmInfoGNUCOFF(TheTriple);
444 } else {
445 // The default is ELF.
446 MAI = new X86ELFMCAsmInfo(TheTriple);
447 }
448
449 // Initialize initial frame state.
450 // Calculate amount of bytes used for return address storing
451 int stackGrowth = is64Bit ? -8 : -4;
452
453 // Initial state of the frame pointer is esp+stackGrowth.
454 unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP;
455 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(
456 nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth);
457 MAI->addInitialFrameState(Inst);
458
459 // Add return address to move list
460 unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP;
461 MCCFIInstruction Inst2 = MCCFIInstruction::createOffset(
462 nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth);
463 MAI->addInitialFrameState(Inst2);
464
465 return MAI;
466}
467
468static MCInstPrinter *createX86MCInstPrinter(const Triple &T,
469 unsigned SyntaxVariant,
470 const MCAsmInfo &MAI,
471 const MCInstrInfo &MII,
472 const MCRegisterInfo &MRI) {
473 if (SyntaxVariant == 0)
474 return new X86ATTInstPrinter(MAI, MII, MRI);
475 if (SyntaxVariant == 1)
476 return new X86IntelInstPrinter(MAI, MII, MRI);
477 return nullptr;
478}
479
480static MCRelocationInfo *createX86MCRelocationInfo(const Triple &TheTriple,
481 MCContext &Ctx) {
482 // Default to the stock relocation info.
483 return llvm::createMCRelocationInfo(TheTriple, Ctx);
484}
485
486namespace llvm {
487namespace X86_MC {
488
489class X86MCInstrAnalysis : public MCInstrAnalysis {
490 X86MCInstrAnalysis(const X86MCInstrAnalysis &) = delete;
491 X86MCInstrAnalysis &operator=(const X86MCInstrAnalysis &) = delete;
492 virtual ~X86MCInstrAnalysis() = default;
493
494public:
495 X86MCInstrAnalysis(const MCInstrInfo *MCII) : MCInstrAnalysis(MCII) {}
496
497#define GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
498#include "X86GenSubtargetInfo.inc"
499
500 bool clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst,
501 APInt &Mask) const override;
502 std::vector<std::pair<uint64_t, uint64_t>>
503 findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
504 const MCSubtargetInfo &STI) const override;
505
506 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
507 uint64_t &Target) const override;
508 std::optional<uint64_t>
509 evaluateMemoryOperandAddress(const MCInst &Inst, const MCSubtargetInfo *STI,
510 uint64_t Addr, uint64_t Size) const override;
511 std::optional<uint64_t>
512 getMemoryOperandRelocationOffset(const MCInst &Inst,
513 uint64_t Size) const override;
514};
515
516#define GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
517#include "X86GenSubtargetInfo.inc"
518
519bool X86MCInstrAnalysis::clearsSuperRegisters(const MCRegisterInfo &MRI,
520 const MCInst &Inst,
521 APInt &Mask) const {
522 const MCInstrDesc &Desc = Info->get(Inst.getOpcode());
523 unsigned NumDefs = Desc.getNumDefs();
524 unsigned NumImplicitDefs = Desc.implicit_defs().size();
525 assert(Mask.getBitWidth() == NumDefs + NumImplicitDefs &&
526 "Unexpected number of bits in the mask!");
527
528 bool HasVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::VEX;
529 bool HasEVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX;
530 bool HasXOP = (Desc.TSFlags & X86II::EncodingMask) == X86II::XOP;
531
532 const MCRegisterClass &GR32RC = MRI.getRegClass(X86::GR32RegClassID);
533 const MCRegisterClass &VR128XRC = MRI.getRegClass(X86::VR128XRegClassID);
534 const MCRegisterClass &VR256XRC = MRI.getRegClass(X86::VR256XRegClassID);
535
536 auto ClearsSuperReg = [=](unsigned RegID) {
537 // On X86-64, a general purpose integer register is viewed as a 64-bit
538 // register internal to the processor.
539 // An update to the lower 32 bits of a 64 bit integer register is
540 // architecturally defined to zero extend the upper 32 bits.
541 if (GR32RC.contains(RegID))
542 return true;
543
544 // Early exit if this instruction has no vex/evex/xop prefix.
545 if (!HasEVEX && !HasVEX && !HasXOP)
546 return false;
547
548 // All VEX and EVEX encoded instructions are defined to zero the high bits
549 // of the destination register up to VLMAX (i.e. the maximum vector register
550 // width pertaining to the instruction).
551 // We assume the same behavior for XOP instructions too.
552 return VR128XRC.contains(RegID) || VR256XRC.contains(RegID);
553 };
554
555 Mask.clearAllBits();
556 for (unsigned I = 0, E = NumDefs; I < E; ++I) {
557 const MCOperand &Op = Inst.getOperand(I);
558 if (ClearsSuperReg(Op.getReg()))
559 Mask.setBit(I);
560 }
561
562 for (unsigned I = 0, E = NumImplicitDefs; I < E; ++I) {
563 const MCPhysReg Reg = Desc.implicit_defs()[I];
564 if (ClearsSuperReg(Reg))
565 Mask.setBit(NumDefs + I);
566 }
567
568 return Mask.getBoolValue();
569}
570
571static std::vector<std::pair<uint64_t, uint64_t>>
572findX86PltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents) {
573 // Do a lightweight parsing of PLT entries.
574 std::vector<std::pair<uint64_t, uint64_t>> Result;
575 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 6 < End; ) {
576 // Recognize a jmp.
577 if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0xa3) {
578 // The jmp instruction at the beginning of each PLT entry jumps to the
579 // address of the base of the .got.plt section plus the immediate.
580 // Set the 1 << 32 bit to let ELFObjectFileBase::getPltEntries convert the
581 // offset to an address. Imm may be a negative int32_t if the GOT entry is
582 // in .got.
583 uint32_t Imm = support::endian::read32le(PltContents.data() + Byte + 2);
584 Result.emplace_back(PltSectionVA + Byte, Imm | (uint64_t(1) << 32));
585 Byte += 6;
586 } else if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0x25) {
587 // The jmp instruction at the beginning of each PLT entry jumps to the
588 // immediate.
589 uint32_t Imm = support::endian::read32le(PltContents.data() + Byte + 2);
590 Result.push_back(std::make_pair(PltSectionVA + Byte, Imm));
591 Byte += 6;
592 } else
593 Byte++;
594 }
595 return Result;
596}
597
598static std::vector<std::pair<uint64_t, uint64_t>>
599findX86_64PltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents) {
600 // Do a lightweight parsing of PLT entries.
601 std::vector<std::pair<uint64_t, uint64_t>> Result;
602 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 6 < End; ) {
603 // Recognize a jmp.
604 if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0x25) {
605 // The jmp instruction at the beginning of each PLT entry jumps to the
606 // address of the next instruction plus the immediate.
607 uint32_t Imm = support::endian::read32le(PltContents.data() + Byte + 2);
608 Result.push_back(
609 std::make_pair(PltSectionVA + Byte, PltSectionVA + Byte + 6 + Imm));
610 Byte += 6;
611 } else
612 Byte++;
613 }
614 return Result;
615}
616
617std::vector<std::pair<uint64_t, uint64_t>>
618X86MCInstrAnalysis::findPltEntries(uint64_t PltSectionVA,
619 ArrayRef<uint8_t> PltContents,
620 const MCSubtargetInfo &STI) const {
621 const Triple &TargetTriple = STI.getTargetTriple();
622 switch (TargetTriple.getArch()) {
623 case Triple::x86:
624 return findX86PltEntries(PltSectionVA, PltContents);
625 case Triple::x86_64:
626 return findX86_64PltEntries(PltSectionVA, PltContents);
627 default:
628 return {};
629 }
630}
631
632bool X86MCInstrAnalysis::evaluateBranch(const MCInst &Inst, uint64_t Addr,
633 uint64_t Size, uint64_t &Target) const {
634 if (Inst.getNumOperands() == 0 ||
635 Info->get(Inst.getOpcode()).operands()[0].OperandType !=
636 MCOI::OPERAND_PCREL)
637 return false;
638 Target = Addr + Size + Inst.getOperand(0).getImm();
639 return true;
640}
641
642std::optional<uint64_t> X86MCInstrAnalysis::evaluateMemoryOperandAddress(
643 const MCInst &Inst, const MCSubtargetInfo *STI, uint64_t Addr,
644 uint64_t Size) const {
645 const MCInstrDesc &MCID = Info->get(Inst.getOpcode());
646 int MemOpStart = X86II::getMemoryOperandNo(MCID.TSFlags);
647 if (MemOpStart == -1)
648 return std::nullopt;
649 MemOpStart += X86II::getOperandBias(MCID);
650
651 const MCOperand &SegReg = Inst.getOperand(MemOpStart + X86::AddrSegmentReg);
652 const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg);
653 const MCOperand &IndexReg = Inst.getOperand(MemOpStart + X86::AddrIndexReg);
654 const MCOperand &ScaleAmt = Inst.getOperand(MemOpStart + X86::AddrScaleAmt);
655 const MCOperand &Disp = Inst.getOperand(MemOpStart + X86::AddrDisp);
656 if (SegReg.getReg() || IndexReg.getReg() || ScaleAmt.getImm() != 1 ||
657 !Disp.isImm())
658 return std::nullopt;
659
660 // RIP-relative addressing.
661 if (BaseReg.getReg() == X86::RIP)
662 return Addr + Size + Disp.getImm();
663
664 return std::nullopt;
665}
666
667std::optional<uint64_t>
668X86MCInstrAnalysis::getMemoryOperandRelocationOffset(const MCInst &Inst,
669 uint64_t Size) const {
670 if (Inst.getOpcode() != X86::LEA64r)
671 return std::nullopt;
672 const MCInstrDesc &MCID = Info->get(Inst.getOpcode());
673 int MemOpStart = X86II::getMemoryOperandNo(MCID.TSFlags);
674 if (MemOpStart == -1)
675 return std::nullopt;
676 MemOpStart += X86II::getOperandBias(MCID);
677 const MCOperand &SegReg = Inst.getOperand(MemOpStart + X86::AddrSegmentReg);
678 const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg);
679 const MCOperand &IndexReg = Inst.getOperand(MemOpStart + X86::AddrIndexReg);
680 const MCOperand &ScaleAmt = Inst.getOperand(MemOpStart + X86::AddrScaleAmt);
681 const MCOperand &Disp = Inst.getOperand(MemOpStart + X86::AddrDisp);
682 // Must be a simple rip-relative address.
683 if (BaseReg.getReg() != X86::RIP || SegReg.getReg() || IndexReg.getReg() ||
684 ScaleAmt.getImm() != 1 || !Disp.isImm())
685 return std::nullopt;
686 // rip-relative ModR/M immediate is 32 bits.
687 assert(Size > 4 && "invalid instruction size for rip-relative lea");
688 return Size - 4;
689}
690
691} // end of namespace X86_MC
692
693} // end of namespace llvm
694
698
699// Force static initialization.
700extern "C" LLVM_C_ABI void LLVMInitializeX86TargetMC() {
701 for (Target *T : {&getTheX86_32Target(), &getTheX86_64Target()}) {
702 // Register the MC asm info.
703 RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo);
704
705 // Register the MC instruction info.
706 TargetRegistry::RegisterMCInstrInfo(*T, createX86MCInstrInfo);
707
708 // Register the MC register info.
709 TargetRegistry::RegisterMCRegInfo(*T, createX86MCRegisterInfo);
710
711 // Register the MC subtarget info.
712 TargetRegistry::RegisterMCSubtargetInfo(*T,
713 X86_MC::createX86MCSubtargetInfo);
714
715 // Register the MC instruction analyzer.
716 TargetRegistry::RegisterMCInstrAnalysis(*T, createX86MCInstrAnalysis);
717
718 // Register the code emitter.
719 TargetRegistry::RegisterMCCodeEmitter(*T, createX86MCCodeEmitter);
720
721 // Register the obj target streamer.
722 TargetRegistry::RegisterObjectTargetStreamer(*T,
723 createX86ObjectTargetStreamer);
724
725 // Register the asm target streamer.
726 TargetRegistry::RegisterAsmTargetStreamer(*T, createX86AsmTargetStreamer);
727
728 // Register the null streamer.
729 TargetRegistry::RegisterNullTargetStreamer(*T, createX86NullTargetStreamer);
730
731 TargetRegistry::RegisterCOFFStreamer(*T, createX86WinCOFFStreamer);
732 TargetRegistry::RegisterELFStreamer(*T, createX86ELFStreamer);
733
734 // Register the MCInstPrinter.
735 TargetRegistry::RegisterMCInstPrinter(*T, createX86MCInstPrinter);
736
737 // Register the MC relocation info.
738 TargetRegistry::RegisterMCRelocationInfo(*T, createX86MCRelocationInfo);
739 }
740
741 // Register the asm backend.
742 TargetRegistry::RegisterMCAsmBackend(getTheX86_32Target(),
743 createX86_32AsmBackend);
744 TargetRegistry::RegisterMCAsmBackend(getTheX86_64Target(),
745 createX86_64AsmBackend);
746}
747
748MCRegister llvm::getX86SubSuperRegister(MCRegister Reg, unsigned Size,
749 bool High) {
750#define DEFAULT_NOREG \
751 default: \
752 return X86::NoRegister;
753#define SUB_SUPER(R1, R2, R3, R4, R) \
754 case X86::R1: \
755 case X86::R2: \
756 case X86::R3: \
757 case X86::R4: \
758 return X86::R;
759#define A_SUB_SUPER(R) \
760 case X86::AH: \
761 SUB_SUPER(AL, AX, EAX, RAX, R)
762#define D_SUB_SUPER(R) \
763 case X86::DH: \
764 SUB_SUPER(DL, DX, EDX, RDX, R)
765#define C_SUB_SUPER(R) \
766 case X86::CH: \
767 SUB_SUPER(CL, CX, ECX, RCX, R)
768#define B_SUB_SUPER(R) \
769 case X86::BH: \
770 SUB_SUPER(BL, BX, EBX, RBX, R)
771#define SI_SUB_SUPER(R) SUB_SUPER(SIL, SI, ESI, RSI, R)
772#define DI_SUB_SUPER(R) SUB_SUPER(DIL, DI, EDI, RDI, R)
773#define BP_SUB_SUPER(R) SUB_SUPER(BPL, BP, EBP, RBP, R)
774#define SP_SUB_SUPER(R) SUB_SUPER(SPL, SP, ESP, RSP, R)
775#define NO_SUB_SUPER(NO, REG) \
776 SUB_SUPER(R##NO##B, R##NO##W, R##NO##D, R##NO, REG)
777#define NO_SUB_SUPER_B(NO) NO_SUB_SUPER(NO, R##NO##B)
778#define NO_SUB_SUPER_W(NO) NO_SUB_SUPER(NO, R##NO##W)
779#define NO_SUB_SUPER_D(NO) NO_SUB_SUPER(NO, R##NO##D)
780#define NO_SUB_SUPER_Q(NO) NO_SUB_SUPER(NO, R##NO)
781 switch (Size) {
782 default:
783 llvm_unreachable("illegal register size");
784 case 8:
785 if (High) {
786 switch (Reg.id()) {
787 DEFAULT_NOREG
788 A_SUB_SUPER(AH)
789 D_SUB_SUPER(DH)
790 C_SUB_SUPER(CH)
791 B_SUB_SUPER(BH)
792 }
793 } else {
794 switch (Reg.id()) {
795 DEFAULT_NOREG
796 A_SUB_SUPER(AL)
797 D_SUB_SUPER(DL)
798 C_SUB_SUPER(CL)
799 B_SUB_SUPER(BL)
800 SI_SUB_SUPER(SIL)
801 DI_SUB_SUPER(DIL)
802 BP_SUB_SUPER(BPL)
803 SP_SUB_SUPER(SPL)
804 NO_SUB_SUPER_B(8)
805 NO_SUB_SUPER_B(9)
806 NO_SUB_SUPER_B(10)
807 NO_SUB_SUPER_B(11)
808 NO_SUB_SUPER_B(12)
809 NO_SUB_SUPER_B(13)
810 NO_SUB_SUPER_B(14)
811 NO_SUB_SUPER_B(15)
812 NO_SUB_SUPER_B(16)
813 NO_SUB_SUPER_B(17)
814 NO_SUB_SUPER_B(18)
815 NO_SUB_SUPER_B(19)
816 NO_SUB_SUPER_B(20)
817 NO_SUB_SUPER_B(21)
818 NO_SUB_SUPER_B(22)
819 NO_SUB_SUPER_B(23)
820 NO_SUB_SUPER_B(24)
821 NO_SUB_SUPER_B(25)
822 NO_SUB_SUPER_B(26)
823 NO_SUB_SUPER_B(27)
824 NO_SUB_SUPER_B(28)
825 NO_SUB_SUPER_B(29)
826 NO_SUB_SUPER_B(30)
827 NO_SUB_SUPER_B(31)
828 }
829 }
830 case 16:
831 switch (Reg.id()) {
832 DEFAULT_NOREG
833 A_SUB_SUPER(AX)
834 D_SUB_SUPER(DX)
835 C_SUB_SUPER(CX)
836 B_SUB_SUPER(BX)
837 SI_SUB_SUPER(SI)
838 DI_SUB_SUPER(DI)
839 BP_SUB_SUPER(BP)
840 SP_SUB_SUPER(SP)
841 NO_SUB_SUPER_W(8)
842 NO_SUB_SUPER_W(9)
843 NO_SUB_SUPER_W(10)
844 NO_SUB_SUPER_W(11)
845 NO_SUB_SUPER_W(12)
846 NO_SUB_SUPER_W(13)
847 NO_SUB_SUPER_W(14)
848 NO_SUB_SUPER_W(15)
849 NO_SUB_SUPER_W(16)
850 NO_SUB_SUPER_W(17)
851 NO_SUB_SUPER_W(18)
852 NO_SUB_SUPER_W(19)
853 NO_SUB_SUPER_W(20)
854 NO_SUB_SUPER_W(21)
855 NO_SUB_SUPER_W(22)
856 NO_SUB_SUPER_W(23)
857 NO_SUB_SUPER_W(24)
858 NO_SUB_SUPER_W(25)
859 NO_SUB_SUPER_W(26)
860 NO_SUB_SUPER_W(27)
861 NO_SUB_SUPER_W(28)
862 NO_SUB_SUPER_W(29)
863 NO_SUB_SUPER_W(30)
864 NO_SUB_SUPER_W(31)
865 }
866 case 32:
867 switch (Reg.id()) {
868 DEFAULT_NOREG
869 A_SUB_SUPER(EAX)
870 D_SUB_SUPER(EDX)
871 C_SUB_SUPER(ECX)
872 B_SUB_SUPER(EBX)
873 SI_SUB_SUPER(ESI)
874 DI_SUB_SUPER(EDI)
875 BP_SUB_SUPER(EBP)
876 SP_SUB_SUPER(ESP)
877 NO_SUB_SUPER_D(8)
878 NO_SUB_SUPER_D(9)
879 NO_SUB_SUPER_D(10)
880 NO_SUB_SUPER_D(11)
881 NO_SUB_SUPER_D(12)
882 NO_SUB_SUPER_D(13)
883 NO_SUB_SUPER_D(14)
884 NO_SUB_SUPER_D(15)
885 NO_SUB_SUPER_D(16)
886 NO_SUB_SUPER_D(17)
887 NO_SUB_SUPER_D(18)
888 NO_SUB_SUPER_D(19)
889 NO_SUB_SUPER_D(20)
890 NO_SUB_SUPER_D(21)
891 NO_SUB_SUPER_D(22)
892 NO_SUB_SUPER_D(23)
893 NO_SUB_SUPER_D(24)
894 NO_SUB_SUPER_D(25)
895 NO_SUB_SUPER_D(26)
896 NO_SUB_SUPER_D(27)
897 NO_SUB_SUPER_D(28)
898 NO_SUB_SUPER_D(29)
899 NO_SUB_SUPER_D(30)
900 NO_SUB_SUPER_D(31)
901 }
902 case 64:
903 switch (Reg.id()) {
904 DEFAULT_NOREG
905 A_SUB_SUPER(RAX)
906 D_SUB_SUPER(RDX)
907 C_SUB_SUPER(RCX)
908 B_SUB_SUPER(RBX)
909 SI_SUB_SUPER(RSI)
910 DI_SUB_SUPER(RDI)
911 BP_SUB_SUPER(RBP)
912 SP_SUB_SUPER(RSP)
913 NO_SUB_SUPER_Q(8)
914 NO_SUB_SUPER_Q(9)
915 NO_SUB_SUPER_Q(10)
916 NO_SUB_SUPER_Q(11)
917 NO_SUB_SUPER_Q(12)
918 NO_SUB_SUPER_Q(13)
919 NO_SUB_SUPER_Q(14)
920 NO_SUB_SUPER_Q(15)
921 NO_SUB_SUPER_Q(16)
922 NO_SUB_SUPER_Q(17)
923 NO_SUB_SUPER_Q(18)
924 NO_SUB_SUPER_Q(19)
925 NO_SUB_SUPER_Q(20)
926 NO_SUB_SUPER_Q(21)
927 NO_SUB_SUPER_Q(22)
928 NO_SUB_SUPER_Q(23)
929 NO_SUB_SUPER_Q(24)
930 NO_SUB_SUPER_Q(25)
931 NO_SUB_SUPER_Q(26)
932 NO_SUB_SUPER_Q(27)
933 NO_SUB_SUPER_Q(28)
934 NO_SUB_SUPER_Q(29)
935 NO_SUB_SUPER_Q(30)
936 NO_SUB_SUPER_Q(31)
937 }
938 }
939}
MRI
unsigned const MachineRegisterInfo * MRI
Definition AArch64AdvSIMDScalarPass.cpp:103
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
APInt.h
This file implements a class to represent arbitrary precision integral constant values and operations...
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition ARMSLSHardening.cpp:73
Info
Analysis containing CSE Info
Definition CSEInfo.cpp:27
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:110
Options
static LVOptions Options
Definition LVOptions.cpp:25
I
#define I(x, y, z)
Definition MD5.cpp:58
T
#define T
Definition Mips16ISelLowering.cpp:353
High
uint64_t High
Definition NVVMIntrRange.cpp:46
CH
#define CH(x, y, z)
Definition SHA256.cpp:34
RA
SI optimize exec mask operations pre RA
Definition SIOptimizeExecMaskingPreRA.cpp:79
X
static TableGen::Emitter::OptClass< SkeletonEmitter > X("gen-skeleton-class", "Generate example skeleton class")
LLVM_C_ABI
#define LLVM_C_ABI
LLVM_C_ABI is the export/visibility macro used to mark symbols declared in llvm-c as exported when bu...
Definition Visibility.h:40
is64Bit
static bool is64Bit(const char *name)
Definition X86Disassembler.cpp:1086
NO_SUB_SUPER_W
#define NO_SUB_SUPER_W(NO)
NO_SUB_SUPER_Q
#define NO_SUB_SUPER_Q(NO)
createX86MCRelocationInfo
static MCRelocationInfo * createX86MCRelocationInfo(const Triple &TheTriple, MCContext &Ctx)
Definition X86MCTargetDesc.cpp:480
createX86MCInstrInfo
static MCInstrInfo * createX86MCInstrInfo()
Definition X86MCTargetDesc.cpp:403
C_SUB_SUPER
#define C_SUB_SUPER(R)
NO_SUB_SUPER_D
#define NO_SUB_SUPER_D(NO)
DEFAULT_NOREG
#define DEFAULT_NOREG
createX86MCRegisterInfo
static MCRegisterInfo * createX86MCRegisterInfo(const Triple &TT)
Definition X86MCTargetDesc.cpp:409
SP_SUB_SUPER
#define SP_SUB_SUPER(R)
createX86MCInstPrinter
static MCInstPrinter * createX86MCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
Definition X86MCTargetDesc.cpp:468
createX86MCInstrAnalysis
static MCInstrAnalysis * createX86MCInstrAnalysis(const MCInstrInfo *Info)
Definition X86MCTargetDesc.cpp:695
SI_SUB_SUPER
#define SI_SUB_SUPER(R)
BP_SUB_SUPER
#define BP_SUB_SUPER(R)
B_SUB_SUPER
#define B_SUB_SUPER(R)
LLVMInitializeX86TargetMC
LLVM_C_ABI void LLVMInitializeX86TargetMC()
Definition X86MCTargetDesc.cpp:700
DI_SUB_SUPER
#define DI_SUB_SUPER(R)
NO_SUB_SUPER_B
#define NO_SUB_SUPER_B(NO)
A_SUB_SUPER
#define A_SUB_SUPER(R)
D_SUB_SUPER
#define D_SUB_SUPER(R)
createX86MCAsmInfo
static MCAsmInfo * createX86MCAsmInfo(const MCRegisterInfo &MRI, const Triple &TheTriple, const MCTargetOptions &Options)
Definition X86MCTargetDesc.cpp:421
isMemOperand
static bool isMemOperand(const MCInst &MI, unsigned Op, unsigned RegClassID)
Definition X86MCTargetDesc.cpp:77
llvm::APInt
Class for arbitrary precision integers.
Definition APInt.h:78
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:41
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition ArrayRef.h:147
llvm::ArrayRef::data
const T * data() const
Definition ArrayRef.h:144
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition MCAsmInfo.h:64
llvm::MCAsmInfo::addInitialFrameState
void addInitialFrameState(const MCCFIInstruction &Inst)
Definition MCAsmInfo.cpp:74
llvm::MCCFIInstruction::cfiDefCfa
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Definition MCDwarf.h:585
llvm::MCCFIInstruction::createOffset
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition MCDwarf.h:627
llvm::MCContext
Context object for machine code objects.
Definition MCContext.h:83
llvm::MCInstPrinter
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition MCInstPrinter.h:46
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition MCInst.h:188
llvm::MCInst::getNumOperands
unsigned getNumOperands() const
Definition MCInst.h:212
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition MCInst.h:202
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition MCInst.h:210
llvm::MCInstrAnalysis::Info
const MCInstrInfo * Info
Definition MCInstrAnalysis.h:35
llvm::MCInstrAnalysis::MCInstrAnalysis
MCInstrAnalysis(const MCInstrInfo *Info)
Definition MCInstrAnalysis.h:38
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition MCInstrDesc.h:199
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition MCInstrInfo.h:27
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition MCInst.h:40
llvm::MCOperand::getImm
int64_t getImm() const
Definition MCInst.h:84
llvm::MCOperand::isImm
bool isImm() const
Definition MCInst.h:66
llvm::MCOperand::getReg
MCRegister getReg() const
Returns the register number.
Definition MCInst.h:73
llvm::MCRegisterClass
MCRegisterClass - Base class of TargetRegisterClass.
Definition MCRegisterInfo.h:36
llvm::MCRegisterClass::contains
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
Definition MCRegisterInfo.h:74
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition MCRegisterInfo.h:150
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition MCRegister.h:33
llvm::MCRelocationInfo
Create MCExprs from relocations found in an object file.
Definition MCRelocationInfo.h:26
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition MCSubtargetInfo.h:77
llvm::MCSubtargetInfo::hasFeature
bool hasFeature(unsigned Feature) const
Definition MCSubtargetInfo.h:122
llvm::MCSubtargetInfo::getTargetTriple
const Triple & getTargetTriple() const
Definition MCSubtargetInfo.h:111
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition StringRef.h:55
llvm::Target
Target - Wrapper for Target specific information.
Definition TargetRegistry.h:146
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition Triple.h:47
llvm::Triple::isOSCygMing
bool isOSCygMing() const
Tests for either Cygwin or MinGW OS.
Definition Triple.h:717
llvm::Triple::isOSBinFormatMachO
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition Triple.h:782
llvm::Triple::isWindowsCoreCLREnvironment
bool isWindowsCoreCLREnvironment() const
Definition Triple.h:700
llvm::Triple::getArch
ArchType getArch() const
Get the parsed architecture type of this triple.
Definition Triple.h:411
llvm::Triple::isUEFI
bool isUEFI() const
Tests whether the OS is UEFI.
Definition Triple.h:674
llvm::Triple::isOSBinFormatELF
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition Triple.h:769
llvm::Triple::isWindowsMSVCEnvironment
bool isWindowsMSVCEnvironment() const
Checks if the environment could be MSVC.
Definition Triple.h:689
llvm::Triple::isWindowsItaniumEnvironment
bool isWindowsItaniumEnvironment() const
Definition Triple.h:704
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition Twine.h:82
llvm::X86_MC::X86MCInstrAnalysis
Definition X86MCTargetDesc.cpp:489
llvm::X86_MC::X86MCInstrAnalysis::evaluateBranch
bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, uint64_t &Target) const override
Given a branch instruction try to get the address the branch targets.
Definition X86MCTargetDesc.cpp:632
llvm::X86_MC::X86MCInstrAnalysis::X86MCInstrAnalysis
X86MCInstrAnalysis(const MCInstrInfo *MCII)
Definition X86MCTargetDesc.cpp:495
llvm::X86_MC::X86MCInstrAnalysis::evaluateMemoryOperandAddress
std::optional< uint64_t > evaluateMemoryOperandAddress(const MCInst &Inst, const MCSubtargetInfo *STI, uint64_t Addr, uint64_t Size) const override
Given an instruction tries to get the address of a memory operand.
Definition X86MCTargetDesc.cpp:642
llvm::X86_MC::X86MCInstrAnalysis::getMemoryOperandRelocationOffset
std::optional< uint64_t > getMemoryOperandRelocationOffset(const MCInst &Inst, uint64_t Size) const override
Given an instruction with a memory operand that could require relocation, returns the offset within t...
Definition X86MCTargetDesc.cpp:668
llvm::X86_MC::X86MCInstrAnalysis::findPltEntries
std::vector< std::pair< uint64_t, uint64_t > > findPltEntries(uint64_t PltSectionVA, ArrayRef< uint8_t > PltContents, const MCSubtargetInfo &STI) const override
Returns (PLT virtual address, GOT virtual address) pairs for PLT entries.
Definition X86MCTargetDesc.cpp:618
llvm::X86_MC::X86MCInstrAnalysis::clearsSuperRegisters
bool clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst, APInt &Mask) const override
Returns true if at least one of the register writes performed by.
Definition X86MCTargetDesc.cpp:519
uint32_t
uint64_t
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition ErrorHandling.h:164
llvm::X86II::RawFrmDstSrc
@ RawFrmDstSrc
RawFrmDstSrc - This form is for instructions that use the source index register SI/ESI/RSI with a pos...
Definition X86BaseInfo.h:518
llvm::X86II::EVEX
@ EVEX
EVEX - Specifies that this instruction use EVEX form which provides syntax support up to 32 512-bit r...
Definition X86BaseInfo.h:825
llvm::X86II::RawFrmDst
@ RawFrmDst
RawFrmDst - This form is for instructions that use the destination index register DI/EDI/RDI.
Definition X86BaseInfo.h:514
llvm::X86II::VEX
@ VEX
VEX - encoding using 0xC4/0xC5.
Definition X86BaseInfo.h:818
llvm::X86II::XOP
@ XOP
XOP - Opcode prefix used by XOP instructions.
Definition X86BaseInfo.h:820
llvm::X86II::RawFrmSrc
@ RawFrmSrc
RawFrmSrc - This form is for instructions that use the source index register SI/ESI/RSI with a possib...
Definition X86BaseInfo.h:511
llvm::X86II::getMemoryOperandNo
int getMemoryOperandNo(uint64_t TSFlags)
Definition X86BaseInfo.h:1011
llvm::X86II::getOperandBias
unsigned getOperandBias(const MCInstrDesc &Desc)
Compute whether all of the def operands are repeated in the uses and therefore should be skipped.
Definition X86BaseInfo.h:968
llvm::X86_MC
Definition X86MCTargetDesc.cpp:487
llvm::X86_MC::is32BitMemOperand
bool is32BitMemOperand(const MCInst &MI, unsigned Op)
Definition X86MCTargetDesc.cpp:97
llvm::X86_MC::is16BitMemOperand
bool is16BitMemOperand(const MCInst &MI, unsigned Op, const MCSubtargetInfo &STI)
Definition X86MCTargetDesc.cpp:86
llvm::X86_MC::hasLockPrefix
bool hasLockPrefix(const MCInst &MI)
Returns true if this instruction has a LOCK prefix.
Definition X86MCTargetDesc.cpp:73
llvm::X86_MC::initLLVMToSEHAndCVRegMapping
void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI)
Definition X86MCTargetDesc.cpp:168
llvm::X86_MC::findX86_64PltEntries
static std::vector< std::pair< uint64_t, uint64_t > > findX86_64PltEntries(uint64_t PltSectionVA, ArrayRef< uint8_t > PltContents)
Definition X86MCTargetDesc.cpp:599
llvm::X86_MC::findX86PltEntries
static std::vector< std::pair< uint64_t, uint64_t > > findX86PltEntries(uint64_t PltSectionVA, ArrayRef< uint8_t > PltContents)
Definition X86MCTargetDesc.cpp:572
llvm::X86_MC::needsAddressSizeOverride
bool needsAddressSizeOverride(const MCInst &MI, const MCSubtargetInfo &STI, int MemoryOperand, uint64_t TSFlags)
Returns true if this instruction needs an Address-Size override prefix.
Definition X86MCTargetDesc.cpp:115
llvm::X86_MC::ParseX86Triple
std::string ParseX86Triple(const Triple &TT)
Definition X86MCTargetDesc.cpp:47
llvm::X86_MC::createX86MCSubtargetInfo
MCSubtargetInfo * createX86MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a X86 MCSubtargetInfo instance.
Definition X86MCTargetDesc.cpp:390
llvm::X86_MC::is64BitMemOperand
bool is64BitMemOperand(const MCInst &MI, unsigned Op)
Definition X86MCTargetDesc.cpp:110
llvm::X86_MC::getDwarfRegFlavour
unsigned getDwarfRegFlavour(const Triple &TT, bool isEH)
Definition X86MCTargetDesc.cpp:61
llvm::support::endian::read32le
uint32_t read32le(const void *P)
Definition Endian.h:429
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition AddressRanges.h:18
llvm::createX86ObjectTargetStreamer
MCTargetStreamer * createX86ObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
Implements X86-only directives for object files.
Definition X86WinCOFFTargetStreamer.cpp:463
llvm::getX86SubSuperRegister
MCRegister getX86SubSuperRegister(MCRegister Reg, unsigned Size, bool High=false)
Definition X86MCTargetDesc.cpp:748
llvm::createX86_64AsmBackend
MCAsmBackend * createX86_64AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition X86AsmBackend.cpp:1487
llvm::createX86AsmTargetStreamer
MCTargetStreamer * createX86AsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrinter)
Implements X86-only directives for assembly emission.
Definition X86WinCOFFTargetStreamer.cpp:454
llvm::createX86MCCodeEmitter
MCCodeEmitter * createX86MCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition X86MCCodeEmitter.cpp:2027
llvm::getTheX86_32Target
Target & getTheX86_32Target()
Definition X86TargetInfo.cpp:14
llvm::Desc
Op::Description Desc
Definition DWARFExpressionPrinter.cpp:23
llvm::createMCRelocationInfo
LLVM_ABI MCRelocationInfo * createMCRelocationInfo(const Triple &TT, MCContext &Ctx)
Definition MCRelocationInfo.cpp:27
llvm::createX86ELFStreamer
MCStreamer * createX86ELFStreamer(const Triple &T, MCContext &Context, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&MOW, std::unique_ptr< MCCodeEmitter > &&MCE)
Definition X86AsmBackend.cpp:1529
llvm::createX86WinCOFFStreamer
MCStreamer * createX86WinCOFFStreamer(MCContext &C, std::unique_ptr< MCAsmBackend > &&AB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&CE)
Construct an X86 Windows COFF machine code streamer which will generate PE/COFF format object files.
Definition X86WinCOFFStreamer.cpp:76
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition MCRegister.h:21
llvm::Op
DWARFExpression::Operation Op
Definition DWARFExpressionPrinter.cpp:22
llvm::createX86_32AsmBackend
MCAsmBackend * createX86_32AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition X86AsmBackend.cpp:1468
llvm::getTheX86_64Target
Target & getTheX86_64Target()
Definition X86TargetInfo.cpp:18
llvm::createX86NullTargetStreamer
MCTargetStreamer * createX86NullTargetStreamer(MCStreamer &S)
Implements X86-only null emission.
Definition X86TargetStreamer.h:43
llvm::RegisterMCAsmInfoFn
RegisterMCAsmInfoFn - Helper template for registering a target assembly info implementation.
Definition TargetRegistry.h:1130
llvm::TargetRegistry::RegisterMCRegInfo
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
Definition TargetRegistry.h:855
llvm::TargetRegistry::RegisterMCAsmBackend
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
Definition TargetRegistry.h:895
llvm::TargetRegistry::RegisterMCCodeEmitter
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
Definition TargetRegistry.h:961
llvm::TargetRegistry::RegisterMCSubtargetInfo
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target.
Definition TargetRegistry.h:868
llvm::TargetRegistry::RegisterObjectTargetStreamer
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
Definition TargetRegistry.h:996
llvm::TargetRegistry::RegisterMCInstrAnalysis
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target.
Definition TargetRegistry.h:841
llvm::TargetRegistry::RegisterELFStreamer
static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)
Definition TargetRegistry.h:973
llvm::TargetRegistry::RegisterNullTargetStreamer
static void RegisterNullTargetStreamer(Target &T, Target::NullTargetStreamerCtorTy Fn)
Definition TargetRegistry.h:981
llvm::TargetRegistry::RegisterMCInstPrinter
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
Definition TargetRegistry.h:948
llvm::TargetRegistry::RegisterCOFFStreamer
static void RegisterCOFFStreamer(Target &T, Target::COFFStreamerCtorTy Fn)
Definition TargetRegistry.h:965
llvm::TargetRegistry::RegisterMCInstrInfo
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target.
Definition TargetRegistry.h:835
llvm::TargetRegistry::RegisterAsmTargetStreamer
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)
Definition TargetRegistry.h:990
llvm::TargetRegistry::RegisterMCRelocationInfo
static void RegisterMCRelocationInfo(Target &T, Target::MCRelocationInfoCtorTy Fn)
RegisterMCRelocationInfo - Register an MCRelocationInfo implementation for the given target.
Definition TargetRegistry.h:1010
llvm::X86_64MCAsmInfoDarwin
Definition X86MCAsmInfo.h:32
Generated on for LLVM by doxygen 1.14.0