LLVM 22.0.0git
Public Member Functions | Static Public Member Functions | List of all members
llvm::AMDGPUDisassembler Class Reference

#include "Target/AMDGPU/Disassembler/AMDGPUDisassembler.h"

Inheritance diagram for llvm::AMDGPUDisassembler:
[legend]

Public Member Functions

 AMDGPUDisassembler (const MCSubtargetInfo &STI, MCContext &Ctx, MCInstrInfo const *MCII)
 
 ~AMDGPUDisassembler () override=default
 
void setABIVersion (unsigned Version) override
 ELF-specific, set the ABI version from the object header.
 
DecodeStatus getInstruction (MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CS) const override
 Returns the disassembly of a single instruction.
 
const char * getRegClassName (unsigned RegClassID) const
 
MCOperand createRegOperand (unsigned int RegId) const
 
MCOperand createRegOperand (unsigned RegClassID, unsigned Val) const
 
MCOperand createSRegOperand (unsigned SRegClassID, unsigned Val) const
 
MCOperand createVGPR16Operand (unsigned RegIdx, bool IsHi) const
 
MCOperand errOperand (unsigned V, const Twine &ErrMsg) const
 
template<typename InsnType >
DecodeStatus tryDecodeInst (const uint8_t *Table, MCInst &MI, InsnType Inst, uint64_t Address, raw_ostream &Comments) const
 
template<typename InsnType >
DecodeStatus tryDecodeInst (const uint8_t *Table1, const uint8_t *Table2, MCInst &MI, InsnType Inst, uint64_t Address, raw_ostream &Comments) const
 
Expected< bool > onSymbolStart (SymbolInfoTy &Symbol, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address) const override
 Used to perform separate target specific disassembly for a particular symbol.
 
Expected< bool > decodeKernelDescriptor (StringRef KdName, ArrayRef< uint8_t > Bytes, uint64_t KdAddress) const
 
Expected< bool > decodeKernelDescriptorDirective (DataExtractor::Cursor &Cursor, ArrayRef< uint8_t > Bytes, raw_string_ostream &KdStream) const
 
Expected< bool > decodeCOMPUTE_PGM_RSRC1 (uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
 Decode as directives that handle COMPUTE_PGM_RSRC1.
 
Expected< bool > decodeCOMPUTE_PGM_RSRC2 (uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
 Decode as directives that handle COMPUTE_PGM_RSRC2.
 
Expected< bool > decodeCOMPUTE_PGM_RSRC3 (uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
 Decode as directives that handle COMPUTE_PGM_RSRC3.
 
void convertEXPInst (MCInst &MI) const
 
void convertVINTERPInst (MCInst &MI) const
 
void convertFMAanyK (MCInst &MI) const
 
void convertSDWAInst (MCInst &MI) const
 
void convertMAIInst (MCInst &MI) const
 f8f6f4 instructions have different pseudos depending on the used formats.
 
void convertWMMAInst (MCInst &MI) const
 
void convertDPP8Inst (MCInst &MI) const
 
void convertMIMGInst (MCInst &MI) const
 
void convertVOP3DPPInst (MCInst &MI) const
 
void convertVOP3PDPPInst (MCInst &MI) const
 
void convertVOPCDPPInst (MCInst &MI) const
 
void convertVOPC64DPPInst (MCInst &MI) const
 
void convertMacDPPInst (MCInst &MI) const
 
void convertTrue16OpSel (MCInst &MI) const
 
unsigned getVgprClassId (unsigned Width) const
 
unsigned getAgprClassId (unsigned Width) const
 
unsigned getSgprClassId (unsigned Width) const
 
unsigned getTtmpClassId (unsigned Width) const
 
MCOperand decodeMandatoryLiteralConstant (unsigned Imm) const
 
MCOperand decodeMandatoryLiteral64Constant (uint64_t Imm) const
 
MCOperand decodeLiteralConstant (bool ExtendFP64) const
 
MCOperand decodeLiteral64Constant () const
 
MCOperand decodeSrcOp (unsigned Width, unsigned Val) const
 
MCOperand decodeNonVGPRSrcOp (unsigned Width, unsigned Val) const
 
MCOperand decodeVOPDDstYOp (MCInst &Inst, unsigned Val) const
 
MCOperand decodeSpecialReg32 (unsigned Val) const
 
MCOperand decodeSpecialReg64 (unsigned Val) const
 
MCOperand decodeSpecialReg96Plus (unsigned Val) const
 
MCOperand decodeSDWASrc (unsigned Width, unsigned Val) const
 
MCOperand decodeSDWASrc16 (unsigned Val) const
 
MCOperand decodeSDWASrc32 (unsigned Val) const
 
MCOperand decodeSDWAVopcDst (unsigned Val) const
 
MCOperand decodeBoolReg (unsigned Val) const
 
MCOperand decodeSplitBarrier (unsigned Val) const
 
MCOperand decodeDpp8FI (unsigned Val) const
 
MCOperand decodeVersionImm (unsigned Imm) const
 
int getTTmpIdx (unsigned Val) const
 
const MCInstrInfo * getMCII () const
 
bool isVI () const
 
bool isGFX9 () const
 
bool isGFX90A () const
 
bool isGFX9Plus () const
 
bool isGFX10 () const
 
bool isGFX10Plus () const
 
bool isGFX11 () const
 
bool isGFX11Plus () const
 
bool isGFX12 () const
 
bool isGFX12Plus () const
 
bool isGFX1250 () const
 
bool hasArchitectedFlatScratch () const
 
bool hasKernargPreload () const
 
bool isMacDPP (MCInst &MI) const
 
- Public Member Functions inherited from llvm::MCDisassembler
 MCDisassembler (const MCSubtargetInfo &STI, MCContext &Ctx)
 
virtual ~MCDisassembler ()
 
virtual DecodeStatus getInstruction (MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
 Returns the disassembly of a single instruction.
 
virtual DecodeStatus getInstructionBundle (MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const
 Returns the disassembly of an instruction bundle for VLIW architectures like Hexagon.
 
virtual Expected< bool > onSymbolStart (SymbolInfoTy &Symbol, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address) const
 Used to perform separate target specific disassembly for a particular symbol.
 
virtual uint64_t suggestBytesToSkip (ArrayRef< uint8_t > Bytes, uint64_t Address) const
 Suggest a distance to skip in a buffer of data to find the next place to look for the start of an instruction.
 
bool tryAddingSymbolicOperand (MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const
 
void tryAddingPcLoadReferenceComment (int64_t Value, uint64_t Address) const
 
void setSymbolizer (std::unique_ptr< MCSymbolizer > Symzer)
 Set Symzer as the current symbolizer.
 
MCContext & getContext () const
 
const MCSubtargetInfo & getSubtargetInfo () const
 
virtual void setABIVersion (unsigned Version)
 ELF-specific, set the ABI version from the object header.
 

Static Public Member Functions

static MCOperand decodeIntImmed (unsigned Imm)
 

Additional Inherited Members

- Public Types inherited from llvm::MCDisassembler
enum  DecodeStatus { Fail = 0 , SoftFail = 1 , Success = 3 }
 Ternary decode status. More...
 
- Public Attributes inherited from llvm::MCDisassembler
raw_ostream * CommentStream = nullptr
 
- Protected Attributes inherited from llvm::MCDisassembler
const MCSubtargetInfo & STI
 
std::unique_ptr< MCSymbolizer > Symbolizer
 

Detailed Description

Definition at line 39 of file AMDGPUDisassembler.h.

Constructor & Destructor Documentation

◆ AMDGPUDisassembler()

AMDGPUDisassembler::AMDGPUDisassembler ( const MCSubtargetInfo &  STI,
MCContext &  Ctx,
MCInstrInfo const *  MCII 
)

Definition at line 56 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::UCVersion::getGFXVersions(), llvm::MCSubtargetInfo::hasFeature(), isGFX10Plus(), llvm::reportFatalUsageError(), and llvm::MCDisassembler::STI.

◆ ~AMDGPUDisassembler()

llvm::AMDGPUDisassembler::~AMDGPUDisassembler ( )
overridedefault

Member Function Documentation

◆ convertDPP8Inst()

void AMDGPUDisassembler::convertDPP8Inst ( MCInst &  MI) const

Definition at line 1179 of file AMDGPUDisassembler.cpp.

References collectVOPModifiers(), convertTrue16OpSel(), llvm::MCOperand::createImm(), llvm::MCInstrInfo::get(), llvm::MCInstrDesc::getNumOperands(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), MI, and Opc.

Referenced by getInstruction().

◆ convertEXPInst()

void AMDGPUDisassembler::convertEXPInst ( MCInst &  MI) const

Definition at line 932 of file AMDGPUDisassembler.cpp.

References llvm::MCOperand::createImm(), llvm::MCSubtargetInfo::hasFeature(), insertNamedMCOperand(), MI, and llvm::MCDisassembler::STI.

Referenced by getInstruction().

◆ convertFMAanyK()

void AMDGPUDisassembler::convertFMAanyK ( MCInst &  MI) const

Definition at line 1440 of file AMDGPUDisassembler.cpp.

References assert(), llvm::MCOperand::createImm(), insertNamedMCOperand(), and MI.

Referenced by getInstruction().

◆ convertMacDPPInst()

void AMDGPUDisassembler::convertMacDPPInst ( MCInst &  MI) const

Definition at line 1172 of file AMDGPUDisassembler.cpp.

References assert(), llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), llvm::MCInstrInfo::get(), llvm::MCInstrDesc::getNumOperands(), insertNamedMCOperand(), and MI.

Referenced by getInstruction().

◆ convertMAIInst()

void AMDGPUDisassembler::convertMAIInst ( MCInst &  MI) const

f8f6f4 instructions have different pseudos depending on the used formats.

In the disassembler table, we only have the variants with the largest register classes which assume using an fp8/bf8 format for both operands. The actual register class depends on the format in blgp and cbsz operands. Adjust the register classes depending on the used format.

Definition at line 1020 of file AMDGPUDisassembler.cpp.

References adjustMFMA_F8F6F4OpRegClass(), llvm::AMDGPU::getMFMA_F8F6F4_WithFormatArgs(), MI, llvm::AMDGPU::MFMA_F8F6F4_Info::NumRegsSrcA, llvm::AMDGPU::MFMA_F8F6F4_Info::NumRegsSrcB, and llvm::AMDGPU::MFMA_F8F6F4_Info::Opcode.

Referenced by getInstruction().

◆ convertMIMGInst()

void AMDGPUDisassembler::convertMIMGInst ( MCInst &  MI) const

Definition at line 1229 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::MIMGBaseOpcodeInfo::A16, addOperand(), assert(), llvm::AMDGPU::MIMGBaseOpcodeInfo::BVH, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), llvm::SIInstrFlags::Gather4, llvm::MCInstrInfo::get(), llvm::AMDGPU::getAddrSizeMIMGOp(), llvm::MCRegisterInfo::getMatchingSuperReg(), llvm::AMDGPU::getMIMGBaseOpcodeInfo(), llvm::AMDGPU::getMIMGDimInfoByEncoding(), llvm::AMDGPU::getMIMGInfo(), llvm::AMDGPU::getMIMGOpcode(), llvm::MCRegisterInfo::getRegClass(), llvm::MCRegisterInfo::getSubReg(), llvm::MCSubtargetInfo::hasFeature(), llvm::AMDGPU::hasG16(), llvm::AMDGPU::hasPackedD16(), Info, isGFX10Plus(), MI, llvm::SIInstrFlags::MIMG, llvm::MCInstrDesc::operands(), llvm::popcount(), llvm::MCDisassembler::STI, llvm::MCInstrDesc::TSFlags, and llvm::SIInstrFlags::VSAMPLE.

Referenced by getInstruction().

◆ convertSDWAInst()

void AMDGPUDisassembler::convertSDWAInst ( MCInst &  MI) const

Definition at line 965 of file AMDGPUDisassembler.cpp.

References llvm::MCOperand::createImm(), createRegOperand(), llvm::MCSubtargetInfo::hasFeature(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), MI, and llvm::MCDisassembler::STI.

Referenced by getInstruction().

◆ convertTrue16OpSel()

void AMDGPUDisassembler::convertTrue16OpSel ( MCInst &  MI) const

Definition at line 1117 of file AMDGPUDisassembler.cpp.

References llvm::MCRegisterClass::contains(), llvm::SISrcMods::DST_OP_SEL, llvm::MCRegisterInfo::getEncodingValue(), llvm::MCOperand::getImm(), llvm::MCRegisterInfo::getRegClass(), llvm::MCRegisterClass::getRegister(), MI, llvm::SISrcMods::OP_SEL_0, Opc, OpIdx, and llvm::AMDGPU::HWEncoding::REG_IDX_MASK.

Referenced by convertDPP8Inst(), convertVINTERPInst(), convertVOP3DPPInst(), convertVOPC64DPPInst(), and getInstruction().

◆ convertVINTERPInst()

void AMDGPUDisassembler::convertVINTERPInst ( MCInst &  MI) const

Definition at line 941 of file AMDGPUDisassembler.cpp.

References convertTrue16OpSel(), llvm::MCOperand::createImm(), insertNamedMCOperand(), and MI.

Referenced by getInstruction().

◆ convertVOP3DPPInst()

void AMDGPUDisassembler::convertVOP3DPPInst ( MCInst &  MI) const

Definition at line 1208 of file AMDGPUDisassembler.cpp.

References collectVOPModifiers(), convertTrue16OpSel(), llvm::MCOperand::createImm(), llvm::MCInstrInfo::get(), llvm::MCInstrDesc::getNumOperands(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), MI, and Opc.

Referenced by getInstruction().

◆ convertVOP3PDPPInst()

void AMDGPUDisassembler::convertVOP3PDPPInst ( MCInst &  MI) const

Definition at line 1379 of file AMDGPUDisassembler.cpp.

References collectVOPModifiers(), llvm::MCOperand::createImm(), llvm::MCInstrInfo::get(), llvm::MCInstrDesc::getNumOperands(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), MI, and Opc.

Referenced by getInstruction().

◆ convertVOPC64DPPInst()

void AMDGPUDisassembler::convertVOPC64DPPInst ( MCInst &  MI) const

Definition at line 1426 of file AMDGPUDisassembler.cpp.

References collectVOPModifiers(), convertTrue16OpSel(), llvm::MCOperand::createImm(), llvm::MCInstrInfo::get(), llvm::MCInstrDesc::getNumOperands(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), MI, Opc, and VOPModifiers::OpSel.

Referenced by getInstruction().

◆ convertVOPCDPPInst()

void AMDGPUDisassembler::convertVOPCDPPInst ( MCInst &  MI) const

Definition at line 1407 of file AMDGPUDisassembler.cpp.

References llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), llvm::MCInstrInfo::get(), llvm::MCInstrDesc::getNumOperands(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), MI, and Opc.

Referenced by getInstruction().

◆ convertWMMAInst()

void AMDGPUDisassembler::convertWMMAInst ( MCInst &  MI) const

Definition at line 1049 of file AMDGPUDisassembler.cpp.

References adjustMFMA_F8F6F4OpRegClass(), llvm::AMDGPU::getWMMA_F8F6F4_WithFormatArgs(), MI, llvm::AMDGPU::MFMA_F8F6F4_Info::NumRegsSrcA, llvm::AMDGPU::MFMA_F8F6F4_Info::NumRegsSrcB, and llvm::AMDGPU::MFMA_F8F6F4_Info::Opcode.

Referenced by getInstruction().

◆ createRegOperand() [1/2]

MCOperand AMDGPUDisassembler::createRegOperand ( unsigned int  RegId) const
inline

Definition at line 1461 of file AMDGPUDisassembler.cpp.

References llvm::MCOperand::createReg(), llvm::AMDGPU::getMCReg(), and llvm::MCDisassembler::STI.

Referenced by convertSDWAInst(), createRegOperand(), createSRegOperand(), createVGPR16Operand(), decodeSDWASrc(), decodeSDWAVopcDst(), decodeSpecialReg32(), decodeSpecialReg64(), decodeSpecialReg96Plus(), decodeSrcOp(), decodeVOPDDstYOp(), and getInstruction().

◆ createRegOperand() [2/2]

MCOperand AMDGPUDisassembler::createRegOperand ( unsigned  RegClassID,
unsigned  Val 
) const
inline

Definition at line 1466 of file AMDGPUDisassembler.cpp.

References createRegOperand(), errOperand(), and getRegClassName().

◆ createSRegOperand()

MCOperand AMDGPUDisassembler::createSRegOperand ( unsigned  SRegClassID,
unsigned  Val 
) const
inline

Definition at line 1476 of file AMDGPUDisassembler.cpp.

References llvm::MCDisassembler::CommentStream, createRegOperand(), getRegClassName(), and llvm_unreachable.

Referenced by decodeNonVGPRSrcOp(), decodeSDWASrc(), and decodeSDWAVopcDst().

◆ createVGPR16Operand()

MCOperand AMDGPUDisassembler::createVGPR16Operand ( unsigned  RegIdx,
bool  IsHi 
) const

Definition at line 1525 of file AMDGPUDisassembler.cpp.

References createRegOperand().

◆ decodeBoolReg()

MCOperand AMDGPUDisassembler::decodeBoolReg ( unsigned  Val) const

Definition at line 2064 of file AMDGPUDisassembler.cpp.

References decodeSrcOp(), llvm::MCSubtargetInfo::hasFeature(), and llvm::MCDisassembler::STI.

◆ decodeCOMPUTE_PGM_RSRC1()

Expected< bool > AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1 ( uint32_t  FourByteBuffer,
raw_string_ostream &  KdStream 
) const

Decode as directives that handle COMPUTE_PGM_RSRC1.

Parameters
FourByteBuffer- Bytes holding contents of COMPUTE_PGM_RSRC1.
KdStream- Stream to write the disassembled directives to.

Definition at line 2214 of file AMDGPUDisassembler.cpp.

References CHECK_RESERVED_BITS, CHECK_RESERVED_BITS_DESC, CHECK_RESERVED_BITS_DESC_MSG, CHECK_RESERVED_BITS_MSG, GET_FIELD, llvm::AMDGPU::IsaInfo::getSGPREncodingGranule(), llvm::AMDGPU::IsaInfo::getVGPREncodingGranule(), hasArchitectedFlatScratch(), isGFX10Plus(), isGFX1250(), isGFX12Plus(), isGFX9Plus(), PRINT_DIRECTIVE, PRINT_PSEUDO_DIRECTIVE_COMMENT, and llvm::MCDisassembler::STI.

Referenced by decodeKernelDescriptorDirective().

◆ decodeCOMPUTE_PGM_RSRC2()

Expected< bool > AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2 ( uint32_t  FourByteBuffer,
raw_string_ostream &  KdStream 
) const

Decode as directives that handle COMPUTE_PGM_RSRC2.

Parameters
FourByteBuffer- Bytes holding contents of COMPUTE_PGM_RSRC2.
KdStream- Stream to write the disassembled directives to.

Definition at line 2336 of file AMDGPUDisassembler.cpp.

References CHECK_RESERVED_BITS, CHECK_RESERVED_BITS_DESC, hasArchitectedFlatScratch(), and PRINT_DIRECTIVE.

Referenced by decodeKernelDescriptorDirective().

◆ decodeCOMPUTE_PGM_RSRC3()

Expected< bool > AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC3 ( uint32_t  FourByteBuffer,
raw_string_ostream &  KdStream 
) const

Decode as directives that handle COMPUTE_PGM_RSRC3.

Parameters
FourByteBuffer- Bytes holding contents of COMPUTE_PGM_RSRC3.
KdStream- Stream to write the disassembled directives to.

Definition at line 2384 of file AMDGPUDisassembler.cpp.

References CHECK_RESERVED_BITS_DESC_MSG, llvm::createStringError(), GET_FIELD, isGFX10Plus(), isGFX11(), isGFX11Plus(), isGFX1250(), isGFX12Plus(), isGFX90A(), PRINT_DIRECTIVE, and PRINT_PSEUDO_DIRECTIVE_COMMENT.

Referenced by decodeKernelDescriptorDirective().

◆ decodeDpp8FI()

MCOperand AMDGPUDisassembler::decodeDpp8FI ( unsigned  Val) const

Definition at line 2073 of file AMDGPUDisassembler.cpp.

References llvm::MCOperand::createImm(), llvm::AMDGPU::DPP::DPP8_FI_0, and llvm::AMDGPU::DPP::DPP8_FI_1.

◆ decodeIntImmed()

MCOperand AMDGPUDisassembler::decodeIntImmed ( unsigned  Imm)
static

Definition at line 1588 of file AMDGPUDisassembler.cpp.

References assert(), and llvm::MCOperand::createImm().

◆ decodeKernelDescriptor()

Expected< bool > AMDGPUDisassembler::decodeKernelDescriptor ( StringRef  KdName,
ArrayRef< uint8_t >  Bytes,
uint64_t  KdAddress 
) const

Definition at line 2669 of file AMDGPUDisassembler.cpp.

References AMDHSA_BITS_GET, llvm::CallingConv::C, llvm::cantFail(), llvm::createStringError(), decodeKernelDescriptorDirective(), isGFX10Plus(), llvm::amdhsa::KERNEL_CODE_PROPERTIES_OFFSET, llvm::little, llvm::outs(), llvm::support::endian::read16(), llvm::ArrayRef< T >::size(), and llvm::raw_string_ostream::str().

Referenced by onSymbolStart().

◆ decodeKernelDescriptorDirective()

Expected< bool > AMDGPUDisassembler::decodeKernelDescriptorDirective ( DataExtractor::Cursor &  Cursor,
ArrayRef< uint8_t >  Bytes,
raw_string_ostream &  KdStream 
) const

Definition at line 2514 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::AMDHSA_COV5, assert(), llvm::amdhsa::COMPUTE_PGM_RSRC1_OFFSET, llvm::amdhsa::COMPUTE_PGM_RSRC2_OFFSET, llvm::amdhsa::COMPUTE_PGM_RSRC3_OFFSET, createReservedKDBitsError(), createReservedKDBytesError(), decodeCOMPUTE_PGM_RSRC1(), decodeCOMPUTE_PGM_RSRC2(), decodeCOMPUTE_PGM_RSRC3(), llvm::DataExtractor::getBytes(), llvm::DataExtractor::getU16(), llvm::DataExtractor::getU32(), llvm::amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET, hasArchitectedFlatScratch(), I, isGFX10Plus(), isGFX1250(), isGFX9(), llvm::amdhsa::KERNARG_PRELOAD_OFFSET, llvm::amdhsa::KERNARG_SIZE_OFFSET, llvm::amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET, llvm::amdhsa::KERNEL_CODE_PROPERTIES_OFFSET, llvm_unreachable, PRINT_DIRECTIVE, llvm::amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET, llvm::amdhsa::RESERVED0_OFFSET, llvm::amdhsa::RESERVED1_OFFSET, llvm::amdhsa::RESERVED3_OFFSET, llvm::ArrayRef< T >::size(), llvm::DataExtractor::skip(), and llvm::DataExtractor::Cursor::tell().

Referenced by decodeKernelDescriptor().

◆ decodeLiteral64Constant()

MCOperand AMDGPUDisassembler::decodeLiteral64Constant ( ) const

Definition at line 1574 of file AMDGPUDisassembler.cpp.

References assert(), llvm::MCOperand::createImm(), errOperand(), llvm::MCSubtargetInfo::hasFeature(), llvm::ArrayRef< T >::size(), and llvm::MCDisassembler::STI.

Referenced by decodeNonVGPRSrcOp().

◆ decodeLiteralConstant()

MCOperand AMDGPUDisassembler::decodeLiteralConstant ( bool  ExtendFP64) const

Definition at line 1557 of file AMDGPUDisassembler.cpp.

References llvm::MCOperand::createImm(), errOperand(), and llvm::ArrayRef< T >::size().

◆ decodeMandatoryLiteral64Constant()

MCOperand AMDGPUDisassembler::decodeMandatoryLiteral64Constant ( uint64_t  Imm) const

Definition at line 1547 of file AMDGPUDisassembler.cpp.

References llvm::MCOperand::createImm(), and errOperand().

◆ decodeMandatoryLiteralConstant()

MCOperand AMDGPUDisassembler::decodeMandatoryLiteralConstant ( unsigned  Imm) const

Definition at line 1533 of file AMDGPUDisassembler.cpp.

References assert(), llvm::MCOperand::createImm(), errOperand(), llvm::AMDGPU::hasVOPD(), and llvm::MCDisassembler::STI.

◆ decodeNonVGPRSrcOp()

MCOperand AMDGPUDisassembler::decodeNonVGPRSrcOp ( unsigned  Width,
unsigned  Val 
) const

Definition at line 1848 of file AMDGPUDisassembler.cpp.

References assert(), llvm::MCOperand::createImm(), createSRegOperand(), decodeLiteral64Constant(), decodeSpecialReg32(), decodeSpecialReg64(), decodeSpecialReg96Plus(), getSgprClassId(), getTtmpClassId(), getTTmpIdx(), llvm::MCSubtargetInfo::hasFeature(), llvm_unreachable, SGPR_MAX, and llvm::MCDisassembler::STI.

Referenced by decodeSrcOp().

◆ decodeSDWASrc()

MCOperand AMDGPUDisassembler::decodeSDWASrc ( unsigned  Width,
unsigned  Val 
) const

Definition at line 1992 of file AMDGPUDisassembler.cpp.

References llvm::MCOperand::createImm(), createRegOperand(), createSRegOperand(), decodeSpecialReg32(), getSgprClassId(), getTtmpClassId(), getVgprClassId(), llvm::MCSubtargetInfo::hasFeature(), isGFX10Plus(), llvm_unreachable, and llvm::MCDisassembler::STI.

Referenced by decodeSDWASrc16(), and decodeSDWASrc32().

◆ decodeSDWASrc16()

MCOperand AMDGPUDisassembler::decodeSDWASrc16 ( unsigned  Val) const

Definition at line 2031 of file AMDGPUDisassembler.cpp.

References decodeSDWASrc().

◆ decodeSDWASrc32()

MCOperand AMDGPUDisassembler::decodeSDWASrc32 ( unsigned  Val) const

Definition at line 2035 of file AMDGPUDisassembler.cpp.

References decodeSDWASrc().

◆ decodeSDWAVopcDst()

MCOperand AMDGPUDisassembler::decodeSDWAVopcDst ( unsigned  Val) const

Definition at line 2039 of file AMDGPUDisassembler.cpp.

References assert(), createRegOperand(), createSRegOperand(), decodeSpecialReg32(), decodeSpecialReg64(), getSgprClassId(), getTtmpClassId(), getTTmpIdx(), llvm::MCSubtargetInfo::hasFeature(), SGPR_MAX, and llvm::MCDisassembler::STI.

◆ decodeSpecialReg32()

MCOperand AMDGPUDisassembler::decodeSpecialReg32 ( unsigned  Val) const

Definition at line 1904 of file AMDGPUDisassembler.cpp.

References createRegOperand(), errOperand(), isGFX11Plus(), and llvm::M0().

Referenced by decodeNonVGPRSrcOp(), decodeSDWASrc(), and decodeSDWAVopcDst().

◆ decodeSpecialReg64()

MCOperand AMDGPUDisassembler::decodeSpecialReg64 ( unsigned  Val) const

Definition at line 1942 of file AMDGPUDisassembler.cpp.

References createRegOperand(), errOperand(), and isGFX11Plus().

Referenced by decodeNonVGPRSrcOp(), and decodeSDWAVopcDst().

◆ decodeSpecialReg96Plus()

MCOperand AMDGPUDisassembler::decodeSpecialReg96Plus ( unsigned  Val) const

Definition at line 1974 of file AMDGPUDisassembler.cpp.

References createRegOperand(), errOperand(), and isGFX11Plus().

Referenced by decodeNonVGPRSrcOp().

◆ decodeSplitBarrier()

MCOperand AMDGPUDisassembler::decodeSplitBarrier ( unsigned  Val) const

Definition at line 2069 of file AMDGPUDisassembler.cpp.

References decodeSrcOp().

◆ decodeSrcOp()

MCOperand AMDGPUDisassembler::decodeSrcOp ( unsigned  Width,
unsigned  Val 
) const

Definition at line 1833 of file AMDGPUDisassembler.cpp.

References assert(), createRegOperand(), decodeNonVGPRSrcOp(), getAgprClassId(), and getVgprClassId().

Referenced by decodeBoolReg(), and decodeSplitBarrier().

◆ decodeVersionImm()

MCOperand AMDGPUDisassembler::decodeVersionImm ( unsigned  Imm) const

Definition at line 2079 of file AMDGPUDisassembler.cpp.

References llvm::MCSymbolRefExpr::create(), llvm::MCConstantExpr::create(), llvm::MCOperand::createExpr(), llvm::MCOperand::createImm(), llvm::MCBinaryExpr::createOr(), llvm::find_if(), llvm::MCDisassembler::getContext(), llvm::AMDGPU::UCVersion::getGFXVersions(), I, and llvm::Version.

◆ decodeVOPDDstYOp()

MCOperand AMDGPUDisassembler::decodeVOPDDstYOp ( MCInst &  Inst,
unsigned  Val 
) const

Definition at line 1893 of file AMDGPUDisassembler.cpp.

References assert(), createRegOperand(), llvm::MCRegisterInfo::getEncodingValue(), llvm::MCInst::getOpcode(), llvm::MCInst::getOperand(), llvm::MCOperand::getReg(), getVgprClassId(), and llvm::MCOperand::isReg().

◆ errOperand()

MCOperand AMDGPUDisassembler::errOperand ( unsigned  V,
const Twine &  ErrMsg 
) const
inline

Definition at line 1451 of file AMDGPUDisassembler.cpp.

References llvm::MCDisassembler::CommentStream.

Referenced by createRegOperand(), decodeLiteral64Constant(), decodeLiteralConstant(), decodeMandatoryLiteral64Constant(), decodeMandatoryLiteralConstant(), decodeSpecialReg32(), decodeSpecialReg64(), and decodeSpecialReg96Plus().

◆ getAgprClassId()

unsigned AMDGPUDisassembler::getAgprClassId ( unsigned  Width) const

Definition at line 1733 of file AMDGPUDisassembler.cpp.

References llvm_unreachable.

Referenced by decodeSrcOp().

◆ getInstruction()

DecodeStatus AMDGPUDisassembler::getInstruction ( MCInst &  Instr,
uint64_t &  Size,
ArrayRef< uint8_t >  Bytes,
uint64_t  Address,
raw_ostream &  CStream 
) const
overridevirtual

Returns the disassembly of a single instruction.

Parameters
Instr- An MCInst to populate with the contents of the instruction.
Size- A value to populate with the size of the instruction, or the number of bytes consumed while attempting to decode an invalid instruction.
Address- The address, in the memory space of region, of the first byte of the instruction.
Bytes- A reference to the actual bytes of the instruction.
CStream- The stream to print comments and annotations on.
Returns
- MCDisassembler::Success if the instruction is valid, MCDisassembler::SoftFail if the instruction was disassemblable but invalid, MCDisassembler::Fail if the instruction was invalid.

Implements llvm::MCDisassembler.

Definition at line 592 of file AMDGPUDisassembler.cpp.

References llvm::Address, convertDPP8Inst(), convertEXPInst(), convertFMAanyK(), convertMacDPPInst(), convertMAIInst(), convertMIMGInst(), convertSDWAInst(), convertTrue16OpSel(), convertVINTERPInst(), convertVOP3DPPInst(), convertVOP3PDPPInst(), convertVOPC64DPPInst(), convertVOPCDPPInst(), convertWMMAInst(), llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), createRegOperand(), llvm::SIInstrFlags::DPP, llvm::SIInstrFlags::DS, eat12Bytes(), eat16Bytes(), llvm::SIInstrFlags::EXP, llvm::MCDisassembler::Fail, llvm::SIInstrFlags::FLAT, llvm::MCInstrInfo::get(), llvm::MCRegisterInfo::getEncodingValue(), llvm::MCInstrDesc::getOperandConstraint(), llvm::AMDGPU::CPol::GLC, llvm::MCSubtargetInfo::hasFeature(), llvm::AMDGPU::hasGDS(), llvm::MCInstrDesc::hasImplicitDefOfPhysReg(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), llvm::SIInstrFlags::IsAtomicRet, isGFX10(), isGFX11(), isGFX11Plus(), isGFX12(), isGFX1250(), isGFX9(), llvm::AMDGPU::isMAC(), isMacDPP(), llvm::SIInstrFlags::IsMAI, isVI(), llvm::AMDGPU::isVOPC64DPP(), llvm::SIInstrFlags::IsWMMA, MI, llvm::SIInstrFlags::MIMG, llvm::SIInstrFlags::MTBUF, llvm::SIInstrFlags::MUBUF, llvm::SIInstrFlags::SDWA, llvm::ArrayRef< T >::size(), Size, llvm::ArrayRef< T >::slice(), llvm::SIInstrFlags::SMRD, llvm::MCDisassembler::SoftFail, llvm::SIInstrFlags::SOPK, llvm::MCDisassembler::STI, llvm::MCDisassembler::Success, llvm::MCOI::TIED_TO, tryDecodeInst(), llvm::MCInstrDesc::TSFlags, llvm::SIInstrFlags::VIMAGE, llvm::SIInstrFlags::VINTERP, llvm::SIInstrFlags::VOP3, llvm::SIInstrFlags::VOP3P, llvm::SIInstrFlags::VOPC, and llvm::SIInstrFlags::VSAMPLE.

◆ getMCII()

const MCInstrInfo * llvm::AMDGPUDisassembler::getMCII ( ) const
inline

Definition at line 170 of file AMDGPUDisassembler.h.

References llvm::MCInstrInfo::get().

◆ getRegClassName()

const char * AMDGPUDisassembler::getRegClassName ( unsigned  RegClassID) const

Definition at line 1445 of file AMDGPUDisassembler.cpp.

References llvm::MCDisassembler::getContext(), getRegClassName(), and llvm::MCContext::getRegisterInfo().

Referenced by createRegOperand(), createSRegOperand(), and getRegClassName().

◆ getSgprClassId()

unsigned AMDGPUDisassembler::getSgprClassId ( unsigned  Width) const

Definition at line 1766 of file AMDGPUDisassembler.cpp.

References llvm_unreachable.

Referenced by decodeNonVGPRSrcOp(), decodeSDWASrc(), and decodeSDWAVopcDst().

◆ getTtmpClassId()

unsigned AMDGPUDisassembler::getTtmpClassId ( unsigned  Width) const

Definition at line 1797 of file AMDGPUDisassembler.cpp.

References llvm_unreachable.

Referenced by decodeNonVGPRSrcOp(), decodeSDWASrc(), and decodeSDWAVopcDst().

◆ getTTmpIdx()

int AMDGPUDisassembler::getTTmpIdx ( unsigned  Val) const

Definition at line 1824 of file AMDGPUDisassembler.cpp.

References isGFX9Plus().

Referenced by decodeNonVGPRSrcOp(), and decodeSDWAVopcDst().

◆ getVgprClassId()

unsigned AMDGPUDisassembler::getVgprClassId ( unsigned  Width) const

Definition at line 1698 of file AMDGPUDisassembler.cpp.

References llvm_unreachable.

Referenced by decodeSDWASrc(), decodeSrcOp(), and decodeVOPDDstYOp().

◆ hasArchitectedFlatScratch()

bool AMDGPUDisassembler::hasArchitectedFlatScratch ( ) const

Definition at line 2150 of file AMDGPUDisassembler.cpp.

References llvm::MCSubtargetInfo::hasFeature(), and llvm::MCDisassembler::STI.

Referenced by decodeCOMPUTE_PGM_RSRC1(), decodeCOMPUTE_PGM_RSRC2(), and decodeKernelDescriptorDirective().

◆ hasKernargPreload()

bool AMDGPUDisassembler::hasKernargPreload ( ) const

Definition at line 2154 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::hasKernargPreload(), and llvm::MCDisassembler::STI.

◆ isGFX10()

bool AMDGPUDisassembler::isGFX10 ( ) const

Definition at line 2126 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::isGFX10(), and llvm::MCDisassembler::STI.

Referenced by getInstruction().

◆ isGFX10Plus()

bool AMDGPUDisassembler::isGFX10Plus ( ) const

Definition at line 2128 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::isGFX10Plus(), and llvm::MCDisassembler::STI.

Referenced by AMDGPUDisassembler(), convertMIMGInst(), decodeCOMPUTE_PGM_RSRC1(), decodeCOMPUTE_PGM_RSRC3(), decodeKernelDescriptor(), decodeKernelDescriptorDirective(), and decodeSDWASrc().

◆ isGFX11()

bool AMDGPUDisassembler::isGFX11 ( ) const

Definition at line 2132 of file AMDGPUDisassembler.cpp.

References llvm::MCSubtargetInfo::hasFeature(), and llvm::MCDisassembler::STI.

Referenced by decodeCOMPUTE_PGM_RSRC3(), and getInstruction().

◆ isGFX11Plus()

bool AMDGPUDisassembler::isGFX11Plus ( ) const

Definition at line 2136 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::isGFX11Plus(), and llvm::MCDisassembler::STI.

Referenced by decodeCOMPUTE_PGM_RSRC3(), decodeSpecialReg32(), decodeSpecialReg64(), decodeSpecialReg96Plus(), and getInstruction().

◆ isGFX12()

bool AMDGPUDisassembler::isGFX12 ( ) const

Definition at line 2140 of file AMDGPUDisassembler.cpp.

References llvm::MCSubtargetInfo::hasFeature(), and llvm::MCDisassembler::STI.

Referenced by getInstruction().

◆ isGFX1250()

bool AMDGPUDisassembler::isGFX1250 ( ) const

Definition at line 2148 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::isGFX1250(), and llvm::MCDisassembler::STI.

Referenced by decodeCOMPUTE_PGM_RSRC1(), decodeCOMPUTE_PGM_RSRC3(), decodeKernelDescriptorDirective(), and getInstruction().

◆ isGFX12Plus()

bool AMDGPUDisassembler::isGFX12Plus ( ) const

Definition at line 2144 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::isGFX12Plus(), and llvm::MCDisassembler::STI.

Referenced by decodeCOMPUTE_PGM_RSRC1(), and decodeCOMPUTE_PGM_RSRC3().

◆ isGFX9()

bool AMDGPUDisassembler::isGFX9 ( ) const

Definition at line 2118 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::isGFX9(), and llvm::MCDisassembler::STI.

Referenced by decodeKernelDescriptorDirective(), and getInstruction().

◆ isGFX90A()

bool AMDGPUDisassembler::isGFX90A ( ) const

Definition at line 2120 of file AMDGPUDisassembler.cpp.

References llvm::MCSubtargetInfo::hasFeature(), and llvm::MCDisassembler::STI.

Referenced by decodeCOMPUTE_PGM_RSRC3().

◆ isGFX9Plus()

bool AMDGPUDisassembler::isGFX9Plus ( ) const

Definition at line 2124 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::isGFX9Plus(), and llvm::MCDisassembler::STI.

Referenced by decodeCOMPUTE_PGM_RSRC1(), and getTTmpIdx().

◆ isMacDPP()

bool AMDGPUDisassembler::isMacDPP ( MCInst &  MI) const

Definition at line 1152 of file AMDGPUDisassembler.cpp.

References assert(), llvm::MCInstrInfo::get(), llvm::AMDGPU::hasNamedOperand(), MI, and llvm::MCOI::TIED_TO.

Referenced by getInstruction().

◆ isVI()

bool AMDGPUDisassembler::isVI ( ) const

Definition at line 2114 of file AMDGPUDisassembler.cpp.

References llvm::MCSubtargetInfo::hasFeature(), and llvm::MCDisassembler::STI.

Referenced by getInstruction().

◆ onSymbolStart()

Expected< bool > AMDGPUDisassembler::onSymbolStart ( SymbolInfoTy &  Symbol,
uint64_t &  Size,
ArrayRef< uint8_t >  Bytes,
uint64_t  Address 
) const
overridevirtual

Used to perform separate target specific disassembly for a particular symbol.

May parse any prelude that precedes instructions after the start of a symbol, or the entire symbol. This is used for example by WebAssembly to decode preludes.

Base implementation returns false. So all targets by default decline to treat symbols separately.

Parameters
Symbol- The symbol.
Size- The number of bytes consumed.
Address- The address, in the memory space of region, of the first byte of the symbol.
Bytes- A reference to the actual bytes at the symbol location.
Returns
- True if this symbol triggered some target specific disassembly for this symbol. Size must be set with the number of bytes consumed.
  • Error if this symbol triggered some target specific disassembly for this symbol, but an error was found with it. Size must be set with the number of bytes consumed.
  • False if the target doesn't want to handle the symbol separately. The value of Size is ignored in this case, and Err must not be set.

Reimplemented from llvm::MCDisassembler.

Definition at line 2709 of file AMDGPUDisassembler.cpp.

References llvm::Address, llvm::createStringError(), decodeKernelDescriptor(), Name, Size, llvm::ELF::STT_AMDGPU_HSA_KERNEL, and llvm::ELF::STT_OBJECT.

◆ setABIVersion()

void AMDGPUDisassembler::setABIVersion ( unsigned  Version)
overridevirtual

ELF-specific, set the ABI version from the object header.

Reimplemented from llvm::MCDisassembler.

Definition at line 73 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::getAMDHSACodeObjectVersion(), and llvm::Version.

◆ tryDecodeInst() [1/2]

template<typename InsnType >
DecodeStatus AMDGPUDisassembler::tryDecodeInst ( const uint8_t *  Table,
MCInst &  MI,
InsnType  Inst,
uint64_t  Address,
raw_ostream &  Comments 
) const

Definition at line 463 of file AMDGPUDisassembler.cpp.

References llvm::Address, assert(), llvm::MCDisassembler::CommentStream, llvm::MCDisassembler::Fail, MI, llvm::MCDisassembler::STI, and llvm::MCDisassembler::Success.

Referenced by getInstruction(), and tryDecodeInst().

◆ tryDecodeInst() [2/2]

template<typename InsnType >
DecodeStatus AMDGPUDisassembler::tryDecodeInst ( const uint8_t *  Table1,
const uint8_t *  Table2,
MCInst &  MI,
InsnType  Inst,
uint64_t  Address,
raw_ostream &  Comments 
) const

Definition at line 492 of file AMDGPUDisassembler.cpp.

References llvm::Address, llvm::MCDisassembler::Fail, MI, and tryDecodeInst().

The documentation for this class was generated from the following files:
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