|
LLVM 22.0.0git
|
#include "llvm/CodeGen/RegisterClassInfo.h"
Public Member Functions | |
| LLVM_ABI | RegisterClassInfo () |
| LLVM_ABI void | runOnMachineFunction (const MachineFunction &MF, bool Rev=false) |
| runOnFunction - Prepare to answer questions about MF. | |
| unsigned | getNumAllocatableRegs (const TargetRegisterClass *RC) const |
| getNumAllocatableRegs - Returns the number of actually allocatable registers in RC in the current function. | |
| ArrayRef< MCPhysReg > | getOrder (const TargetRegisterClass *RC) const |
| getOrder - Returns the preferred allocation order for RC. | |
| bool | isProperSubClass (const TargetRegisterClass *RC) const |
| isProperSubClass - Returns true if RC has a legal super-class with more allocatable registers. | |
| MCRegister | getLastCalleeSavedAlias (MCRegister PhysReg) const |
| getLastCalleeSavedAlias - Returns the last callee saved register that overlaps PhysReg, or NoRegister if PhysReg doesn't overlap a CalleeSavedAliases. | |
| uint8_t | getMinCost (const TargetRegisterClass *RC) const |
| Get the minimum register cost in RC's allocation order. | |
| unsigned | getLastCostChange (const TargetRegisterClass *RC) const |
| Get the position of the last cost change in getOrder(RC). | |
| unsigned | getRegPressureSetLimit (unsigned Idx) const |
| Get the register unit limit for the given pressure set index. | |
Protected Member Functions | |
| LLVM_ABI unsigned | computePSetLimit (unsigned Idx) const |
| This is not accurate because two overlapping register sets may have some nonoverlapping reserved registers. | |
Definition at line 30 of file RegisterClassInfo.h.
|
default |
This is not accurate because two overlapping register sets may have some nonoverlapping reserved registers.
However, computing the allocation order for all register classes would be too expensive.
Definition at line 210 of file RegisterClassInfo.cpp.
References assert(), llvm::CallingConv::C, getNumAllocatableRegs(), llvm::TargetRegisterClass::getNumRegs(), llvm::TargetRegisterInfo::getRegClassPressureSets(), llvm::TargetRegisterInfo::getRegClassWeight(), llvm::TargetRegisterInfo::getRegPressureSetLimit(), Idx, llvm::TargetRegisterInfo::regclasses(), llvm::RegClassWeight::RegWeight, and llvm::RegClassWeight::WeightLimit.
Referenced by getRegPressureSetLimit().
|
inline |
getLastCalleeSavedAlias - Returns the last callee saved register that overlaps PhysReg, or NoRegister if PhysReg doesn't overlap a CalleeSavedAliases.
Definition at line 123 of file RegisterClassInfo.h.
References TRI.
Referenced by llvm::RegAllocEvictionAdvisor::canAllocatePhysReg(), and llvm::RegAllocEvictionAdvisor::isUnusedCalleeSavedReg().
|
inline |
Get the position of the last cost change in getOrder(RC).
All registers in getOrder(RC).slice(getLastCostChange(RC)) will have the same cost according to RegCosts[Reg].
Definition at line 144 of file RegisterClassInfo.h.
Referenced by llvm::RegAllocEvictionAdvisor::getOrderLimit().
|
inline |
Get the minimum register cost in RC's allocation order.
This is the smallest value in RegCosts[Reg] for all the registers in getOrder(RC).
Definition at line 136 of file RegisterClassInfo.h.
Referenced by llvm::RegAllocEvictionAdvisor::getOrderLimit().
|
inline |
getNumAllocatableRegs - Returns the number of actually allocatable registers in RC in the current function.
Definition at line 99 of file RegisterClassInfo.h.
Referenced by computePSetLimit(), getNumAllocatableRegsForConstraints(), llvm::GCNSchedStrategy::initialize(), and llvm::GenericScheduler::initPolicy().
|
inline |
getOrder - Returns the preferred allocation order for RC.
The order contains no reserved registers, and registers that alias callee saved registers come last.
Definition at line 106 of file RegisterClassInfo.h.
Referenced by llvm::AllocationOrder::create(), and llvm::RegAllocBase::getErrorAssignment().
Get the register unit limit for the given pressure set index.
RegisterClassInfo adjusts this limit for reserved registers.
Definition at line 151 of file RegisterClassInfo.h.
References computePSetLimit(), and Idx.
Referenced by computeExcessPressureDelta(), llvm::RegPressureTracker::getUpwardPressureDelta(), llvm::ConvergingVLIWScheduler::initialize(), llvm::ScheduleDAGMILive::initRegPressure(), llvm::PPCInstrInfo::shouldReduceRegisterPressure(), and llvm::ScheduleDAGMILive::updateScheduledPressure().
|
inline |
isProperSubClass - Returns true if RC has a legal super-class with more allocatable registers.
Register classes like GR32_NOSP are not proper sub-classes because esp is not allocatable. Similarly, tGPR is not a proper sub-class in Thumb mode because the GPR super-class is not legal.
Definition at line 116 of file RegisterClassInfo.h.
| void RegisterClassInfo::runOnMachineFunction | ( | const MachineFunction & | MF, |
| bool | Rev = false |
||
| ) |
runOnFunction - Prepare to answer questions about MF.
Rev indicates to use reversed raw order when compute register order. This must be called before any other methods are used.
Definition at line 42 of file RegisterClassInfo.cpp.
References llvm::TargetRegisterInfo::getNumRegClasses(), llvm::TargetRegisterInfo::getNumRegPressureSets(), llvm::MCRegisterInfo::getNumRegs(), llvm::MCRegisterInfo::getNumRegUnits(), llvm::MachineFunction::getRegInfo(), llvm::TargetRegisterInfo::getRegisterCosts(), llvm::MachineRegisterInfo::getReservedRegs(), llvm::MachineFunction::getSubtarget(), I, llvm::MCRegAliasIterator::isValid(), MRI, and llvm::MCRegisterInfo::regunits().
Referenced by llvm::RegAllocBase::init(), llvm::AMDGPURewriteAGPRCopyMFMAPass::run(), llvm::MachinePipeliner::runOnMachineFunction(), and llvm::BreakFalseDeps::runOnMachineFunction().
1.9.6