LLVM 22.0.0git
ARMDisassembler.cpp
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1//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "ARMBaseInstrInfo.h"
10#include "MCTargetDesc/ARMAddressingModes.h"
11#include "MCTargetDesc/ARMBaseInfo.h"
12#include "MCTargetDesc/ARMMCTargetDesc.h"
13#include "TargetInfo/ARMTargetInfo.h"
14#include "Utils/ARMBaseInfo.h"
15#include "llvm/MC/MCContext.h"
16#include "llvm/MC/MCDecoder.h"
17#include "llvm/MC/MCDecoderOps.h"
18#include "llvm/MC/MCDisassembler/MCDisassembler.h"
19#include "llvm/MC/MCInst.h"
20#include "llvm/MC/MCInstrDesc.h"
21#include "llvm/MC/MCInstrInfo.h"
22#include "llvm/MC/MCSubtargetInfo.h"
23#include "llvm/MC/TargetRegistry.h"
24#include "llvm/Support/Compiler.h"
25#include "llvm/Support/ErrorHandling.h"
26#include "llvm/Support/MathExtras.h"
27#include "llvm/Support/raw_ostream.h"
28#include "llvm/TargetParser/SubtargetFeature.h"
29#include <algorithm>
30#include <cassert>
31#include <cstdint>
32#include <vector>
33
34using namespace llvm;
35using namespace llvm::MCD;
36
37#define DEBUG_TYPE "arm-disassembler"
38
39using DecodeStatus = MCDisassembler::DecodeStatus;
40
41namespace {
42
43// Handles the condition code status of instructions in IT blocks
44class ITStatus {
45public:
46 // Returns the condition code for instruction in IT block
47 unsigned getITCC() {
48 unsigned CC = ARMCC::AL;
49 if (instrInITBlock())
50 CC = ITStates.back();
51 return CC;
52 }
53
54 // Advances the IT block state to the next T or E
55 void advanceITState() { ITStates.pop_back(); }
56
57 // Returns true if the current instruction is in an IT block
58 bool instrInITBlock() { return !ITStates.empty(); }
59
60 // Returns true if current instruction is the last instruction in an IT block
61 bool instrLastInITBlock() { return ITStates.size() == 1; }
62
63 // Called when decoding an IT instruction. Sets the IT state for
64 // the following instructions that for the IT block. Firstcond
65 // corresponds to the field in the IT instruction encoding; Mask
66 // is in the MCOperand format in which 1 means 'else' and 0 'then'.
67 void setITState(char Firstcond, char Mask) {
68 // (3 - the number of trailing zeros) is the number of then / else.
69 unsigned NumTZ = llvm::countr_zero<uint8_t>(Mask);
70 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
71 assert(NumTZ <= 3 && "Invalid IT mask!");
72 // push condition codes onto the stack the correct order for the pops
73 for (unsigned Pos = NumTZ + 1; Pos <= 3; ++Pos) {
74 unsigned Else = (Mask >> Pos) & 1;
75 ITStates.push_back(CCBits ^ Else);
76 }
77 ITStates.push_back(CCBits);
78 }
79
80private:
81 std::vector<unsigned char> ITStates;
82};
83
84class VPTStatus {
85public:
86 unsigned getVPTPred() {
87 unsigned Pred = ARMVCC::None;
88 if (instrInVPTBlock())
89 Pred = VPTStates.back();
90 return Pred;
91 }
92
93 void advanceVPTState() { VPTStates.pop_back(); }
94
95 bool instrInVPTBlock() { return !VPTStates.empty(); }
96
97 bool instrLastInVPTBlock() { return VPTStates.size() == 1; }
98
99 void setVPTState(char Mask) {
100 // (3 - the number of trailing zeros) is the number of then / else.
101 unsigned NumTZ = llvm::countr_zero<uint8_t>(Mask);
102 assert(NumTZ <= 3 && "Invalid VPT mask!");
103 // push predicates onto the stack the correct order for the pops
104 for (unsigned Pos = NumTZ + 1; Pos <= 3; ++Pos) {
105 bool T = ((Mask >> Pos) & 1) == 0;
106 if (T)
107 VPTStates.push_back(ARMVCC::Then);
108 else
109 VPTStates.push_back(ARMVCC::Else);
110 }
111 VPTStates.push_back(ARMVCC::Then);
112 }
113
114private:
115 SmallVector<unsigned char, 4> VPTStates;
116};
117
118/// ARM disassembler for all ARM platforms.
119class ARMDisassembler : public MCDisassembler {
120public:
121 std::unique_ptr<const MCInstrInfo> MCII;
122
123 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
124 const MCInstrInfo *MCII)
125 : MCDisassembler(STI, Ctx), MCII(MCII) {
126 InstructionEndianness = STI.hasFeature(ARM::ModeBigEndianInstructions)
127 ? llvm::endianness::big
128 : llvm::endianness::little;
129 }
130
131 ~ARMDisassembler() override = default;
132
133 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
134 ArrayRef<uint8_t> Bytes, uint64_t Address,
135 raw_ostream &CStream) const override;
136
137 uint64_t suggestBytesToSkip(ArrayRef<uint8_t> Bytes,
138 uint64_t Address) const override;
139
140private:
141 DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size,
142 ArrayRef<uint8_t> Bytes, uint64_t Address,
143 raw_ostream &CStream) const;
144
145 DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size,
146 ArrayRef<uint8_t> Bytes, uint64_t Address,
147 raw_ostream &CStream) const;
148
149 mutable ITStatus ITBlock;
150 mutable VPTStatus VPTBlock;
151
152 void AddThumb1SBit(MCInst &MI, bool InITBlock) const;
153 bool isVectorPredicable(const MCInst &MI) const;
154 DecodeStatus AddThumbPredicate(MCInst&) const;
155 void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const;
156
157 llvm::endianness InstructionEndianness;
158};
159
160} // end anonymous namespace
161
162// Forward declare these because the autogenerated code will reference them.
163// Definitions are further down.
164static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
165 uint64_t Address,
166 const MCDisassembler *Decoder);
167static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
168 uint64_t Address,
169 const MCDisassembler *Decoder);
170static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo,
171 uint64_t Address,
172 const MCDisassembler *Decoder);
173static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo,
174 uint64_t Address,
175 const MCDisassembler *Decoder);
176static DecodeStatus
177DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo,
178 uint64_t Address,
179 const MCDisassembler *Decoder);
180static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
181 uint64_t Address,
182 const MCDisassembler *Decoder);
183static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo,
184 uint64_t Address,
185 const MCDisassembler *Decoder);
186static DecodeStatus
187DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
188 const MCDisassembler *Decoder);
189static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo,
190 uint64_t Address,
191 const MCDisassembler *Decoder);
192static DecodeStatus
193DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
194 const MCDisassembler *Decoder);
195static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
196 uint64_t Address,
197 const MCDisassembler *Decoder);
198static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
199 uint64_t Address,
200 const MCDisassembler *Decoder);
201static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
202 uint64_t Address,
203 const MCDisassembler *Decoder);
204static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
205 uint64_t Address,
206 const MCDisassembler *Decoder);
207static DecodeStatus
208DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
209 const MCDisassembler *Decoder);
210static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo,
211 uint64_t Address,
212 const MCDisassembler *Decoder);
213static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
214 uint64_t Address,
215 const MCDisassembler *Decoder);
216static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
217 uint64_t Address,
218 const MCDisassembler *Decoder);
219static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
220 uint64_t Address,
221 const MCDisassembler *Decoder);
222static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
223 uint64_t Address,
224 const MCDisassembler *Decoder);
225static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
226 uint64_t Address,
227 const MCDisassembler *Decoder);
228static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
229 uint64_t Address,
230 const MCDisassembler *Decoder);
231static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
232 uint64_t Address,
233 const MCDisassembler *Decoder);
234static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo,
235 uint64_t Address,
236 const MCDisassembler *Decoder);
237static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
238 uint64_t Address,
239 const MCDisassembler *Decoder);
240static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
241 uint64_t Address,
242 const MCDisassembler *Decoder);
243static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
244 uint64_t Address,
245 const MCDisassembler *Decoder);
246static DecodeStatus
247DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
248 const MCDisassembler *Decoder);
249
250static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
251 uint64_t Address,
252 const MCDisassembler *Decoder);
253static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
254 uint64_t Address,
255 const MCDisassembler *Decoder);
256static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
257 uint64_t Address,
258 const MCDisassembler *Decoder);
259static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
260 uint64_t Address,
261 const MCDisassembler *Decoder);
262static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
263 uint64_t Address,
264 const MCDisassembler *Decoder);
265
266static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
267 uint64_t Address,
268 const MCDisassembler *Decoder);
269static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
270 uint64_t Address,
271 const MCDisassembler *Decoder);
272static DecodeStatus
273DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
274 const MCDisassembler *Decoder);
275static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
276 uint64_t Address,
277 const MCDisassembler *Decoder);
278static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
279 uint64_t Address,
280 const MCDisassembler *Decoder);
281static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn,
282 uint64_t Address,
283 const MCDisassembler *Decoder);
284static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
285 uint64_t Address,
286 const MCDisassembler *Decoder);
287static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
288 uint64_t Address,
289 const MCDisassembler *Decoder);
290
291static DecodeStatus
292DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn,
293 uint64_t Adddress,
294 const MCDisassembler *Decoder);
295static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
296 uint64_t Address,
297 const MCDisassembler *Decoder);
298static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
299 uint64_t Address,
300 const MCDisassembler *Decoder);
301static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
302 uint64_t Address,
303 const MCDisassembler *Decoder);
304static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
305 uint64_t Address,
306 const MCDisassembler *Decoder);
307static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
308 uint64_t Address,
309 const MCDisassembler *Decoder);
310static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
311 uint64_t Address,
312 const MCDisassembler *Decoder);
313static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
314 uint64_t Address,
315 const MCDisassembler *Decoder);
316static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
317 uint64_t Address,
318 const MCDisassembler *Decoder);
319static DecodeStatus DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn,
320 uint64_t Address,
321 const MCDisassembler *Decoder);
322static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
323 uint64_t Address,
324 const MCDisassembler *Decoder);
325static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
326 uint64_t Address,
327 const MCDisassembler *Decoder);
328static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
329 uint64_t Address,
330 const MCDisassembler *Decoder);
331static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
332 uint64_t Address,
333 const MCDisassembler *Decoder);
334static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
335 uint64_t Address,
336 const MCDisassembler *Decoder);
337static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
338 uint64_t Address,
339 const MCDisassembler *Decoder);
340static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
341 uint64_t Address,
342 const MCDisassembler *Decoder);
343static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
344 uint64_t Address,
345 const MCDisassembler *Decoder);
346static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
347 uint64_t Address,
348 const MCDisassembler *Decoder);
349static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
350 uint64_t Address,
351 const MCDisassembler *Decoder);
352static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
353 uint64_t Address,
354 const MCDisassembler *Decoder);
355static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
356 uint64_t Address,
357 const MCDisassembler *Decoder);
358static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
359 uint64_t Address,
360 const MCDisassembler *Decoder);
361static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
362 uint64_t Address,
363 const MCDisassembler *Decoder);
364static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
365 uint64_t Address,
366 const MCDisassembler *Decoder);
367static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
368 uint64_t Address,
369 const MCDisassembler *Decoder);
370static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
371 uint64_t Address,
372 const MCDisassembler *Decoder);
373static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Val,
374 uint64_t Address,
375 const MCDisassembler *Decoder);
376static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst, unsigned Val,
377 uint64_t Address,
378 const MCDisassembler *Decoder);
379static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn,
380 uint64_t Address,
381 const MCDisassembler *Decoder);
382static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
383 uint64_t Address,
384 const MCDisassembler *Decoder);
385static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
386 uint64_t Address,
387 const MCDisassembler *Decoder);
388static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
389 uint64_t Address,
390 const MCDisassembler *Decoder);
391static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
392 uint64_t Address,
393 const MCDisassembler *Decoder);
394static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
395 uint64_t Address,
396 const MCDisassembler *Decoder);
397static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
398 uint64_t Address,
399 const MCDisassembler *Decoder);
400static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
401 uint64_t Address,
402 const MCDisassembler *Decoder);
403static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn,
404 uint64_t Address,
405 const MCDisassembler *Decoder);
406template <int shift>
407static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn,
408 uint64_t Address,
409 const MCDisassembler *Decoder);
410static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
411 uint64_t Address,
412 const MCDisassembler *Decoder);
413static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
414 uint64_t Address,
415 const MCDisassembler *Decoder);
416static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
417 uint64_t Address,
418 const MCDisassembler *Decoder);
419static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, uint64_t Address,
420 const MCDisassembler *Decoder);
421static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
422 uint64_t Address,
423 const MCDisassembler *Decoder);
424static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
425 uint64_t Address,
426 const MCDisassembler *Decoder);
427static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
428 uint64_t Address,
429 const MCDisassembler *Decoder);
430static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
431 uint64_t Address,
432 const MCDisassembler *Decoder);
433static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
434 uint64_t Address,
435 const MCDisassembler *Decoder);
436static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
437 uint64_t Address,
438 const MCDisassembler *Decoder);
439static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
440 uint64_t Address,
441 const MCDisassembler *Decoder);
442static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address,
443 const MCDisassembler *Decoder);
444static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address,
445 const MCDisassembler *Decoder);
446static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address,
447 const MCDisassembler *Decoder);
448static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address,
449 const MCDisassembler *Decoder);
450static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address,
451 const MCDisassembler *Decoder);
452static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address,
453 const MCDisassembler *Decoder);
454static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address,
455 const MCDisassembler *Decoder);
456static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address,
457 const MCDisassembler *Decoder);
458static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address,
459 const MCDisassembler *Decoder);
460static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address,
461 const MCDisassembler *Decoder);
462static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address,
463 const MCDisassembler *Decoder);
464static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address,
465 const MCDisassembler *Decoder);
466static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address,
467 const MCDisassembler *Decoder);
468static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn,
469 uint64_t Address,
470 const MCDisassembler *Decoder);
471static DecodeStatus
472DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Val, uint64_t Address,
473 const MCDisassembler *Decoder);
474
475static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
476 uint64_t Address,
477 const MCDisassembler *Decoder);
478static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
479 uint64_t Address,
480 const MCDisassembler *Decoder);
481static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
482 uint64_t Address,
483 const MCDisassembler *Decoder);
484static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
485 uint64_t Address,
486 const MCDisassembler *Decoder);
487static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
488 uint64_t Address,
489 const MCDisassembler *Decoder);
490static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
491 uint64_t Address,
492 const MCDisassembler *Decoder);
493static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
494 uint64_t Address,
495 const MCDisassembler *Decoder);
496static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
497 uint64_t Address,
498 const MCDisassembler *Decoder);
499static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
500 uint64_t Address,
501 const MCDisassembler *Decoder);
502static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
503 uint64_t Address,
504 const MCDisassembler *Decoder);
505static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
506 uint64_t Address,
507 const MCDisassembler *Decoder);
508static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
509 uint64_t Address,
510 const MCDisassembler *Decoder);
511static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address,
512 const MCDisassembler *Decoder);
513static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
514 uint64_t Address,
515 const MCDisassembler *Decoder);
516static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address,
517 const MCDisassembler *Decoder);
518static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address,
519 const MCDisassembler *Decoder);
520static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
521 uint64_t Address,
522 const MCDisassembler *Decoder);
523static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val,
524 uint64_t Address,
525 const MCDisassembler *Decoder);
526static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst, unsigned Val,
527 uint64_t Address,
528 const MCDisassembler *Decoder);
529static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address,
530 const MCDisassembler *Decoder);
531template <int shift>
532static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address,
533 const MCDisassembler *Decoder);
534static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
535 uint64_t Address,
536 const MCDisassembler *Decoder);
537template <int shift>
538static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val,
539 uint64_t Address,
540 const MCDisassembler *Decoder);
541template <int shift, int WriteBack>
542static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val,
543 uint64_t Address,
544 const MCDisassembler *Decoder);
545static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
546 uint64_t Address,
547 const MCDisassembler *Decoder);
548static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
549 uint64_t Address,
550 const MCDisassembler *Decoder);
551static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
552 uint64_t Address,
553 const MCDisassembler *Decoder);
554static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
555 uint64_t Address,
556 const MCDisassembler *Decoder);
557static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
558 uint64_t Address,
559 const MCDisassembler *Decoder);
560static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
561 uint64_t Address,
562 const MCDisassembler *Decoder);
563static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
564 uint64_t Address,
565 const MCDisassembler *Decoder);
566static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
567 uint64_t Address,
568 const MCDisassembler *Decoder);
569static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address,
570 const MCDisassembler *Decoder);
571static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
572 uint64_t Address,
573 const MCDisassembler *Decoder);
574static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
575 uint64_t Address,
576 const MCDisassembler *Decoder);
577static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, uint64_t Address,
578 const MCDisassembler *Decoder);
579static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
580 uint64_t Address,
581 const MCDisassembler *Decoder);
582static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
583 uint64_t Address,
584 const MCDisassembler *Decoder);
585static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, uint64_t Address,
586 const MCDisassembler *Decoder);
587static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
588 uint64_t Address,
589 const MCDisassembler *Decoder);
590static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
591 uint64_t Address,
592 const MCDisassembler *Decoder);
593
594static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address,
595 const MCDisassembler *Decoder);
596static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
597 uint64_t Address,
598 const MCDisassembler *Decoder);
599static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
600 uint64_t Address,
601 const MCDisassembler *Decoder);
602
603template <bool isSigned, bool isNeg, bool zeroPermitted, int size>
604static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val,
605 uint64_t Address,
606 const MCDisassembler *Decoder);
607static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val,
608 uint64_t Address,
609 const MCDisassembler *Decoder);
610static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val,
611 uint64_t Address,
612 const MCDisassembler *Decoder);
613static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address,
614 const MCDisassembler *Decoder);
615static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val,
616 uint64_t Address,
617 const MCDisassembler *Decoder);
618static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address,
619 const MCDisassembler *Decoder);
620static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val,
621 uint64_t Address,
622 const MCDisassembler *Decoder);
623static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val,
624 uint64_t Address,
625 const MCDisassembler *Decoder);
626static DecodeStatus DecodeVpredNOperand(MCInst &Inst, unsigned Val,
627 uint64_t Address,
628 const MCDisassembler *Decoder);
629static DecodeStatus
630DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
631 const MCDisassembler *Decoder);
632static DecodeStatus
633DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
634 const MCDisassembler *Decoder);
635static DecodeStatus
636DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
637 const MCDisassembler *Decoder);
638static DecodeStatus
639DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
640 const MCDisassembler *Decoder);
641template <bool Writeback>
642static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn,
643 uint64_t Address,
644 const MCDisassembler *Decoder);
645template <int shift>
646static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val,
647 uint64_t Address,
648 const MCDisassembler *Decoder);
649template <int shift>
650static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val,
651 uint64_t Address,
652 const MCDisassembler *Decoder);
653template <int shift>
654static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val,
655 uint64_t Address,
656 const MCDisassembler *Decoder);
657template <unsigned MinLog, unsigned MaxLog>
658static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,
659 uint64_t Address,
660 const MCDisassembler *Decoder);
661template <unsigned start>
662static DecodeStatus
663DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address,
664 const MCDisassembler *Decoder);
665static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn,
666 uint64_t Address,
667 const MCDisassembler *Decoder);
668static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn,
669 uint64_t Address,
670 const MCDisassembler *Decoder);
671static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn,
672 uint64_t Address,
673 const MCDisassembler *Decoder);
674typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val,
675 uint64_t Address,
676 const MCDisassembler *Decoder);
677template <bool scalar, OperandDecoder predicate_decoder>
678static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address,
679 const MCDisassembler *Decoder);
680static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address,
681 const MCDisassembler *Decoder);
682static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn,
683 uint64_t Address,
684 const MCDisassembler *Decoder);
685static DecodeStatus
686DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address,
687 const MCDisassembler *Decoder);
688static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn,
689 uint64_t Address,
690 const MCDisassembler *Decoder);
691static DecodeStatus DecodeLazyLoadStoreMul(MCInst &Inst, unsigned Insn,
692 uint64_t Address,
693 const MCDisassembler *Decoder);
694
695/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
696/// immediate Value in the MCInst. The immediate Value has had any PC
697/// adjustment made by the caller. If the instruction is a branch instruction
698/// then isBranch is true, else false. If the getOpInfo() function was set as
699/// part of the setupForSymbolicDisassembly() call then that function is called
700/// to get any symbolic information at the Address for this instruction. If
701/// that returns non-zero then the symbolic information it returns is used to
702/// create an MCExpr and that is added as an operand to the MCInst. If
703/// getOpInfo() returns zero and isBranch is true then a symbol look up for
704/// Value is done and if a symbol is found an MCExpr is created with that, else
705/// an MCExpr with Value is created. This function returns true if it adds an
706/// operand to the MCInst and false otherwise.
707static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
708 bool isBranch, uint64_t InstSize,
709 MCInst &MI,
710 const MCDisassembler *Decoder) {
711 // FIXME: Does it make sense for value to be negative?
712 return Decoder->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address,
713 isBranch, /*Offset=*/0, /*OpSize=*/0,
714 InstSize);
715}
716
717/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
718/// referenced by a load instruction with the base register that is the Pc.
719/// These can often be values in a literal pool near the Address of the
720/// instruction. The Address of the instruction and its immediate Value are
721/// used as a possible literal pool entry. The SymbolLookUp call back will
722/// return the name of a symbol referenced by the literal pool's entry if
723/// the referenced address is that of a symbol. Or it will return a pointer to
724/// a literal 'C' string if the referenced address of the literal pool's entry
725/// is an address into a section with 'C' string literals.
726static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
727 const MCDisassembler *Decoder) {
728 Decoder->tryAddingPcLoadReferenceComment(Value, Address);
729}
730
731#include "ARMGenDisassemblerTables.inc"
732
733static MCDisassembler *createARMDisassembler(const Target &T,
734 const MCSubtargetInfo &STI,
735 MCContext &Ctx) {
736 return new ARMDisassembler(STI, Ctx, T.createMCInstrInfo());
737}
738
739// Post-decoding checks
740static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size,
741 uint64_t Address, raw_ostream &CS,
742 uint32_t Insn,
743 DecodeStatus Result) {
744 switch (MI.getOpcode()) {
745 case ARM::HVC: {
746 // HVC is undefined if condition = 0xf otherwise upredictable
747 // if condition != 0xe
748 uint32_t Cond = (Insn >> 28) & 0xF;
749 if (Cond == 0xF)
750 return MCDisassembler::Fail;
751 if (Cond != 0xE)
752 return MCDisassembler::SoftFail;
753 return Result;
754 }
755 case ARM::t2ADDri:
756 case ARM::t2ADDri12:
757 case ARM::t2ADDrr:
758 case ARM::t2ADDrs:
759 case ARM::t2SUBri:
760 case ARM::t2SUBri12:
761 case ARM::t2SUBrr:
762 case ARM::t2SUBrs:
763 if (MI.getOperand(0).getReg() == ARM::SP &&
764 MI.getOperand(1).getReg() != ARM::SP)
765 return MCDisassembler::SoftFail;
766 return Result;
767 default: return Result;
768 }
769}
770
771uint64_t ARMDisassembler::suggestBytesToSkip(ArrayRef<uint8_t> Bytes,
772 uint64_t Address) const {
773 // In Arm state, instructions are always 4 bytes wide, so there's no
774 // point in skipping any smaller number of bytes if an instruction
775 // can't be decoded.
776 if (!STI.hasFeature(ARM::ModeThumb))
777 return 4;
778
779 // In a Thumb instruction stream, a halfword is a standalone 2-byte
780 // instruction if and only if its value is less than 0xE800.
781 // Otherwise, it's the first halfword of a 4-byte instruction.
782 //
783 // So, if we can see the upcoming halfword, we can judge on that
784 // basis, and maybe skip a whole 4-byte instruction that we don't
785 // know how to decode, without accidentally trying to interpret its
786 // second half as something else.
787 //
788 // If we don't have the instruction data available, we just have to
789 // recommend skipping the minimum sensible distance, which is 2
790 // bytes.
791 if (Bytes.size() < 2)
792 return 2;
793
794 uint16_t Insn16 = llvm::support::endian::read<uint16_t>(
795 Bytes.data(), InstructionEndianness);
796 return Insn16 < 0xE800 ? 2 : 4;
797}
798
799DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
800 ArrayRef<uint8_t> Bytes,
801 uint64_t Address,
802 raw_ostream &CS) const {
803 if (STI.hasFeature(ARM::ModeThumb))
804 return getThumbInstruction(MI, Size, Bytes, Address, CS);
805 return getARMInstruction(MI, Size, Bytes, Address, CS);
806}
807
808DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size,
809 ArrayRef<uint8_t> Bytes,
810 uint64_t Address,
811 raw_ostream &CS) const {
812 CommentStream = &CS;
813
814 assert(!STI.hasFeature(ARM::ModeThumb) &&
815 "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
816 "mode!");
817
818 // We want to read exactly 4 bytes of data.
819 if (Bytes.size() < 4) {
820 Size = 0;
821 return MCDisassembler::Fail;
822 }
823
824 // Encoded as a 32-bit word in the stream.
825 uint32_t Insn = llvm::support::endian::read<uint32_t>(Bytes.data(),
826 InstructionEndianness);
827
828 // Calling the auto-generated decoder function.
829 DecodeStatus Result =
830 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
831 if (Result != MCDisassembler::Fail) {
832 Size = 4;
833 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result);
834 }
835
836 struct DecodeTable {
837 const uint8_t *P;
838 bool DecodePred;
839 };
840
841 const DecodeTable Tables[] = {
842 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false},
843 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true},
844 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false},
845 {DecoderTablev8Crypto32, false},
846 };
847
848 for (auto Table : Tables) {
849 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI);
850 if (Result != MCDisassembler::Fail) {
851 Size = 4;
852 // Add a fake predicate operand, because we share these instruction
853 // definitions with Thumb2 where these instructions are predicable.
854 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this))
855 return MCDisassembler::Fail;
856 return Result;
857 }
858 }
859
860 Result =
861 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI);
862 if (Result != MCDisassembler::Fail) {
863 Size = 4;
864 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result);
865 }
866
867 Size = 4;
868 return MCDisassembler::Fail;
869}
870
871// Thumb1 instructions don't have explicit S bits. Rather, they
872// implicitly set CPSR. Since it's not represented in the encoding, the
873// auto-generated decoder won't inject the CPSR operand. We need to fix
874// that as a post-pass.
875void ARMDisassembler::AddThumb1SBit(MCInst &MI, bool InITBlock) const {
876 const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
877 MCInst::iterator I = MI.begin();
878 for (unsigned i = 0; i < MCID.NumOperands; ++i, ++I) {
879 if (I == MI.end()) break;
880 if (MCID.operands()[i].isOptionalDef() &&
881 MCID.operands()[i].RegClass == ARM::CCRRegClassID) {
882 if (i > 0 && MCID.operands()[i - 1].isPredicate())
883 continue;
884 MI.insert(I,
885 MCOperand::createReg(InITBlock ? ARM::NoRegister : ARM::CPSR));
886 return;
887 }
888 }
889
890 MI.insert(I, MCOperand::createReg(InITBlock ? ARM::NoRegister : ARM::CPSR));
891}
892
893bool ARMDisassembler::isVectorPredicable(const MCInst &MI) const {
894 const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
895 for (unsigned i = 0; i < MCID.NumOperands; ++i) {
896 if (ARM::isVpred(MCID.operands()[i].OperandType))
897 return true;
898 }
899 return false;
900}
901
902// Most Thumb instructions don't have explicit predicates in the
903// encoding, but rather get their predicates from IT context. We need
904// to fix up the predicate operands using this context information as a
905// post-pass.
906MCDisassembler::DecodeStatus
907ARMDisassembler::AddThumbPredicate(MCInst &MI) const {
908 MCDisassembler::DecodeStatus S = Success;
909
910 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
911
912 // A few instructions actually have predicates encoded in them. Don't
913 // try to overwrite it if we're seeing one of those.
914 switch (MI.getOpcode()) {
915 case ARM::tBcc:
916 case ARM::t2Bcc:
917 case ARM::tCBZ:
918 case ARM::tCBNZ:
919 case ARM::tCPS:
920 case ARM::t2CPS3p:
921 case ARM::t2CPS2p:
922 case ARM::t2CPS1p:
923 case ARM::t2CSEL:
924 case ARM::t2CSINC:
925 case ARM::t2CSINV:
926 case ARM::t2CSNEG:
927 case ARM::tMOVSr:
928 case ARM::tSETEND:
929 // Some instructions (mostly conditional branches) are not
930 // allowed in IT blocks.
931 if (ITBlock.instrInITBlock())
932 S = SoftFail;
933 else
934 return Success;
935 break;
936 case ARM::t2HINT:
937 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
938 S = SoftFail;
939 break;
940 case ARM::tB:
941 case ARM::t2B:
942 case ARM::t2TBB:
943 case ARM::t2TBH:
944 // Some instructions (mostly unconditional branches) can
945 // only appears at the end of, or outside of, an IT.
946 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
947 S = SoftFail;
948 break;
949 default:
950 break;
951 }
952
953 // Warn on non-VPT predicable instruction in a VPT block and a VPT
954 // predicable instruction in an IT block
955 if ((!isVectorPredicable(MI) && VPTBlock.instrInVPTBlock()) ||
956 (isVectorPredicable(MI) && ITBlock.instrInITBlock()))
957 S = SoftFail;
958
959 // If we're in an IT/VPT block, base the predicate on that. Otherwise,
960 // assume a predicate of AL.
961 unsigned CC = ARMCC::AL;
962 unsigned VCC = ARMVCC::None;
963 if (ITBlock.instrInITBlock()) {
964 CC = ITBlock.getITCC();
965 ITBlock.advanceITState();
966 } else if (VPTBlock.instrInVPTBlock()) {
967 VCC = VPTBlock.getVPTPred();
968 VPTBlock.advanceVPTState();
969 }
970
971 const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
972
973 MCInst::iterator CCI = MI.begin();
974 for (unsigned i = 0; i < MCID.NumOperands; ++i, ++CCI) {
975 if (MCID.operands()[i].isPredicate() || CCI == MI.end())
976 break;
977 }
978
979 if (MCID.isPredicable()) {
980 CCI = MI.insert(CCI, MCOperand::createImm(CC));
981 ++CCI;
982 if (CC == ARMCC::AL)
983 MI.insert(CCI, MCOperand::createReg(ARM::NoRegister));
984 else
985 MI.insert(CCI, MCOperand::createReg(ARM::CPSR));
986 } else if (CC != ARMCC::AL) {
987 Check(S, SoftFail);
988 }
989
990 MCInst::iterator VCCI = MI.begin();
991 unsigned VCCPos;
992 for (VCCPos = 0; VCCPos < MCID.NumOperands; ++VCCPos, ++VCCI) {
993 if (ARM::isVpred(MCID.operands()[VCCPos].OperandType) || VCCI == MI.end())
994 break;
995 }
996
997 if (isVectorPredicable(MI)) {
998 VCCI = MI.insert(VCCI, MCOperand::createImm(VCC));
999 ++VCCI;
1000 if (VCC == ARMVCC::None)
1001 VCCI = MI.insert(VCCI, MCOperand::createReg(0));
1002 else
1003 VCCI = MI.insert(VCCI, MCOperand::createReg(ARM::P0));
1004 ++VCCI;
1005 VCCI = MI.insert(VCCI, MCOperand::createReg(0));
1006 ++VCCI;
1007 if (MCID.operands()[VCCPos].OperandType == ARM::OPERAND_VPRED_R) {
1008 int TiedOp = MCID.getOperandConstraint(VCCPos + 3, MCOI::TIED_TO);
1009 assert(TiedOp >= 0 &&
1010 "Inactive register in vpred_r is not tied to an output!");
1011 // Copy the operand to ensure it's not invalidated when MI grows.
1012 MI.insert(VCCI, MCOperand(MI.getOperand(TiedOp)));
1013 }
1014 } else if (VCC != ARMVCC::None) {
1015 Check(S, SoftFail);
1016 }
1017
1018 return S;
1019}
1020
1021static const uint16_t GPRDecoderTable[] = {
1022 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1023 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1024 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1025 ARM::R12, ARM::SP, ARM::LR, ARM::PC
1026};
1027
1028static const uint16_t CLRMGPRDecoderTable[] = {
1029 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1030 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1031 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1032 ARM::R12, 0, ARM::LR, ARM::APSR
1033};
1034
1035static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1036 uint64_t Address,
1037 const MCDisassembler *Decoder) {
1038 if (RegNo > 15)
1039 return MCDisassembler::Fail;
1040
1041 unsigned Register = GPRDecoderTable[RegNo];
1042 Inst.addOperand(MCOperand::createReg(Register));
1043 return MCDisassembler::Success;
1044}
1045
1046static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1047 uint64_t Address,
1048 const MCDisassembler *Decoder) {
1049 if (RegNo > 15)
1050 return MCDisassembler::Fail;
1051
1052 unsigned Register = CLRMGPRDecoderTable[RegNo];
1053 if (Register == 0)
1054 return MCDisassembler::Fail;
1055
1056 Inst.addOperand(MCOperand::createReg(Register));
1057 return MCDisassembler::Success;
1058}
1059
1060static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
1061 uint64_t Address,
1062 const MCDisassembler *Decoder) {
1063 DecodeStatus S = MCDisassembler::Success;
1064
1065 if (RegNo == 15)
1066 S = MCDisassembler::SoftFail;
1067
1068 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1069
1070 return S;
1071}
1072
1073static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo,
1074 uint64_t Address,
1075 const MCDisassembler *Decoder) {
1076 DecodeStatus S = MCDisassembler::Success;
1077
1078 if (RegNo == 13)
1079 S = MCDisassembler::SoftFail;
1080
1081 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1082
1083 return S;
1084}
1085
1086static DecodeStatus
1087DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1088 const MCDisassembler *Decoder) {
1089 DecodeStatus S = MCDisassembler::Success;
1090
1091 if (RegNo == 15)
1092 {
1093 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
1094 return MCDisassembler::Success;
1095 }
1096
1097 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1098 return S;
1099}
1100
1101static DecodeStatus
1102DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1103 const MCDisassembler *Decoder) {
1104 DecodeStatus S = MCDisassembler::Success;
1105
1106 if (RegNo == 15)
1107 {
1108 Inst.addOperand(MCOperand::createReg(ARM::ZR));
1109 return MCDisassembler::Success;
1110 }
1111
1112 if (RegNo == 13)
1113 Check(S, MCDisassembler::SoftFail);
1114
1115 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1116 return S;
1117}
1118
1119static DecodeStatus
1120DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1121 const MCDisassembler *Decoder) {
1122 DecodeStatus S = MCDisassembler::Success;
1123 if (RegNo == 13)
1124 return MCDisassembler::Fail;
1125 Check(S, DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder));
1126 return S;
1127}
1128
1129static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1130 uint64_t Address,
1131 const MCDisassembler *Decoder) {
1132 if (RegNo > 7)
1133 return MCDisassembler::Fail;
1134 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
1135}
1136
1137static const uint16_t GPRPairDecoderTable[] = {
1138 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
1139 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
1140};
1141
1142static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
1143 uint64_t Address,
1144 const MCDisassembler *Decoder) {
1145 DecodeStatus S = MCDisassembler::Success;
1146
1147 // According to the Arm ARM RegNo = 14 is undefined, but we return fail
1148 // rather than SoftFail as there is no GPRPair table entry for index 7.
1149 if (RegNo > 13)
1150 return MCDisassembler::Fail;
1151
1152 if (RegNo & 1)
1153 S = MCDisassembler::SoftFail;
1154
1155 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
1156 Inst.addOperand(MCOperand::createReg(RegisterPair));
1157 return S;
1158}
1159
1160static DecodeStatus
1161DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1162 const MCDisassembler *Decoder) {
1163 if (RegNo > 13)
1164 return MCDisassembler::Fail;
1165
1166 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
1167 Inst.addOperand(MCOperand::createReg(RegisterPair));
1168
1169 if ((RegNo & 1) || RegNo > 10)
1170 return MCDisassembler::SoftFail;
1171 return MCDisassembler::Success;
1172}
1173
1174static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo,
1175 uint64_t Address,
1176 const MCDisassembler *Decoder) {
1177 if (RegNo != 13)
1178 return MCDisassembler::Fail;
1179
1180 unsigned Register = GPRDecoderTable[RegNo];
1181 Inst.addOperand(MCOperand::createReg(Register));
1182 return MCDisassembler::Success;
1183}
1184
1185static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1186 uint64_t Address,
1187 const MCDisassembler *Decoder) {
1188 unsigned Register = 0;
1189 switch (RegNo) {
1190 case 0:
1191 Register = ARM::R0;
1192 break;
1193 case 1:
1194 Register = ARM::R1;
1195 break;
1196 case 2:
1197 Register = ARM::R2;
1198 break;
1199 case 3:
1200 Register = ARM::R3;
1201 break;
1202 case 9:
1203 Register = ARM::R9;
1204 break;
1205 case 12:
1206 Register = ARM::R12;
1207 break;
1208 default:
1209 return MCDisassembler::Fail;
1210 }
1211
1212 Inst.addOperand(MCOperand::createReg(Register));
1213 return MCDisassembler::Success;
1214}
1215
1216static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1217 uint64_t Address,
1218 const MCDisassembler *Decoder) {
1219 DecodeStatus S = MCDisassembler::Success;
1220
1221 const FeatureBitset &featureBits =
1222 Decoder->getSubtargetInfo().getFeatureBits();
1223
1224 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
1225 S = MCDisassembler::SoftFail;
1226
1227 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1228 return S;
1229}
1230
1231static const MCPhysReg SPRDecoderTable[] = {
1232 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
1233 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
1234 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
1235 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
1236 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
1237 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
1238 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
1239 ARM::S28, ARM::S29, ARM::S30, ARM::S31
1240};
1241
1242static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
1243 uint64_t Address,
1244 const MCDisassembler *Decoder) {
1245 if (RegNo > 31)
1246 return MCDisassembler::Fail;
1247
1248 unsigned Register = SPRDecoderTable[RegNo];
1249 Inst.addOperand(MCOperand::createReg(Register));
1250 return MCDisassembler::Success;
1251}
1252
1253static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
1254 uint64_t Address,
1255 const MCDisassembler *Decoder) {
1256 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
1257}
1258
1259static const MCPhysReg DPRDecoderTable[] = {
1260 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1261 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1262 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1263 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1264 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1265 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1266 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1267 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1268};
1269
1270// Does this instruction/subtarget permit use of registers d16-d31?
1271static bool PermitsD32(const MCInst &Inst, const MCDisassembler *Decoder) {
1272 if (Inst.getOpcode() == ARM::VSCCLRMD || Inst.getOpcode() == ARM::VSCCLRMS)
1273 return true;
1274 const FeatureBitset &featureBits =
1275 Decoder->getSubtargetInfo().getFeatureBits();
1276 return featureBits[ARM::FeatureD32];
1277}
1278
1279static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
1280 uint64_t Address,
1281 const MCDisassembler *Decoder) {
1282 if (RegNo > (PermitsD32(Inst, Decoder) ? 31u : 15u))
1283 return MCDisassembler::Fail;
1284
1285 unsigned Register = DPRDecoderTable[RegNo];
1286 Inst.addOperand(MCOperand::createReg(Register));
1287 return MCDisassembler::Success;
1288}
1289
1290static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1291 uint64_t Address,
1292 const MCDisassembler *Decoder) {
1293 if (RegNo > 7)
1294 return MCDisassembler::Fail;
1295 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1296}
1297
1298static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1299 uint64_t Address,
1300 const MCDisassembler *Decoder) {
1301 if (RegNo > 15)
1302 return MCDisassembler::Fail;
1303 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
1304}
1305
1306static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
1307 uint64_t Address,
1308 const MCDisassembler *Decoder) {
1309 if (RegNo > 15)
1310 return MCDisassembler::Fail;
1311 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1312}
1313
1314static const MCPhysReg QPRDecoderTable[] = {
1315 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1316 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1317 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1318 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1319};
1320
1321static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
1322 uint64_t Address,
1323 const MCDisassembler *Decoder) {
1324 if (RegNo > 31 || (RegNo & 1) != 0)
1325 return MCDisassembler::Fail;
1326 RegNo >>= 1;
1327
1328 unsigned Register = QPRDecoderTable[RegNo];
1329 Inst.addOperand(MCOperand::createReg(Register));
1330 return MCDisassembler::Success;
1331}
1332
1333static const MCPhysReg DPairDecoderTable[] = {
1334 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1335 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1336 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1337 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1338 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1339 ARM::Q15
1340};
1341
1342static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1343 uint64_t Address,
1344 const MCDisassembler *Decoder) {
1345 if (RegNo > 30)
1346 return MCDisassembler::Fail;
1347
1348 unsigned Register = DPairDecoderTable[RegNo];
1349 Inst.addOperand(MCOperand::createReg(Register));
1350 return MCDisassembler::Success;
1351}
1352
1353static const MCPhysReg DPairSpacedDecoderTable[] = {
1354 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1355 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1356 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1357 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1358 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1359 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1360 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1361 ARM::D28_D30, ARM::D29_D31
1362};
1363
1364static DecodeStatus
1365DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1366 const MCDisassembler *Decoder) {
1367 if (RegNo > 29)
1368 return MCDisassembler::Fail;
1369
1370 unsigned Register = DPairSpacedDecoderTable[RegNo];
1371 Inst.addOperand(MCOperand::createReg(Register));
1372 return MCDisassembler::Success;
1373}
1374
1375static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1376 uint64_t Address,
1377 const MCDisassembler *Decoder) {
1378 DecodeStatus S = MCDisassembler::Success;
1379 if (Val == 0xF) return MCDisassembler::Fail;
1380 // AL predicate is not allowed on Thumb1 branches.
1381 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1382 return MCDisassembler::Fail;
1383 const MCInstrInfo *MCII =
1384 static_cast<const ARMDisassembler *>(Decoder)->MCII.get();
1385 if (Val != ARMCC::AL && !MCII->get(Inst.getOpcode()).isPredicable())
1386 Check(S, MCDisassembler::SoftFail);
1387 Inst.addOperand(MCOperand::createImm(Val));
1388 if (Val == ARMCC::AL) {
1389 Inst.addOperand(MCOperand::createReg(ARM::NoRegister));
1390 } else
1391 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1392 return S;
1393}
1394
1395static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1396 uint64_t Address,
1397 const MCDisassembler *Decoder) {
1398 if (Val)
1399 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1400 else
1401 Inst.addOperand(MCOperand::createReg(ARM::NoRegister));
1402 return MCDisassembler::Success;
1403}
1404
1405static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1406 uint64_t Address,
1407 const MCDisassembler *Decoder) {
1408 DecodeStatus S = MCDisassembler::Success;
1409
1410 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1411 unsigned type = fieldFromInstruction(Val, 5, 2);
1412 unsigned imm = fieldFromInstruction(Val, 7, 5);
1413
1414 // Register-immediate
1415 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
1416 return MCDisassembler::Fail;
1417
1418 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1419 switch (type) {
1420 case 0:
1421 Shift = ARM_AM::lsl;
1422 break;
1423 case 1:
1424 Shift = ARM_AM::lsr;
1425 break;
1426 case 2:
1427 Shift = ARM_AM::asr;
1428 break;
1429 case 3:
1430 Shift = ARM_AM::ror;
1431 break;
1432 }
1433
1434 if (Shift == ARM_AM::ror && imm == 0)
1435 Shift = ARM_AM::rrx;
1436
1437 unsigned Op = Shift | (imm << 3);
1438 Inst.addOperand(MCOperand::createImm(Op));
1439
1440 return S;
1441}
1442
1443static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1444 uint64_t Address,
1445 const MCDisassembler *Decoder) {
1446 DecodeStatus S = MCDisassembler::Success;
1447
1448 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1449 unsigned type = fieldFromInstruction(Val, 5, 2);
1450 unsigned Rs = fieldFromInstruction(Val, 8, 4);
1451
1452 // Register-register
1453 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1454 return MCDisassembler::Fail;
1455 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1456 return MCDisassembler::Fail;
1457
1458 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1459 switch (type) {
1460 case 0:
1461 Shift = ARM_AM::lsl;
1462 break;
1463 case 1:
1464 Shift = ARM_AM::lsr;
1465 break;
1466 case 2:
1467 Shift = ARM_AM::asr;
1468 break;
1469 case 3:
1470 Shift = ARM_AM::ror;
1471 break;
1472 }
1473
1474 Inst.addOperand(MCOperand::createImm(Shift));
1475
1476 return S;
1477}
1478
1479static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1480 uint64_t Address,
1481 const MCDisassembler *Decoder) {
1482 DecodeStatus S = MCDisassembler::Success;
1483
1484 bool NeedDisjointWriteback = false;
1485 MCRegister WritebackReg;
1486 bool CLRM = false;
1487 switch (Inst.getOpcode()) {
1488 default:
1489 break;
1490 case ARM::LDMIA_UPD:
1491 case ARM::LDMDB_UPD:
1492 case ARM::LDMIB_UPD:
1493 case ARM::LDMDA_UPD:
1494 case ARM::t2LDMIA_UPD:
1495 case ARM::t2LDMDB_UPD:
1496 case ARM::t2STMIA_UPD:
1497 case ARM::t2STMDB_UPD:
1498 NeedDisjointWriteback = true;
1499 WritebackReg = Inst.getOperand(0).getReg();
1500 break;
1501 case ARM::t2CLRM:
1502 CLRM = true;
1503 break;
1504 }
1505
1506 // Empty register lists are not allowed.
1507 if (Val == 0) return MCDisassembler::Fail;
1508 for (unsigned i = 0; i < 16; ++i) {
1509 if (Val & (1 << i)) {
1510 if (CLRM) {
1511 if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) {
1512 return MCDisassembler::Fail;
1513 }
1514 } else {
1515 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1516 return MCDisassembler::Fail;
1517 // Writeback not allowed if Rn is in the target list.
1518 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
1519 Check(S, MCDisassembler::SoftFail);
1520 }
1521 }
1522 }
1523
1524 return S;
1525}
1526
1527static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1528 uint64_t Address,
1529 const MCDisassembler *Decoder) {
1530 DecodeStatus S = MCDisassembler::Success;
1531
1532 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1533 unsigned regs = fieldFromInstruction(Val, 0, 8);
1534
1535 // In case of unpredictable encoding, tweak the operands.
1536 if (regs == 0 || (Vd + regs) > 32) {
1537 regs = Vd + regs > 32 ? 32 - Vd : regs;
1538 regs = std::max( 1u, regs);
1539 S = MCDisassembler::SoftFail;
1540 }
1541
1542 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1543 return MCDisassembler::Fail;
1544 for (unsigned i = 0; i < (regs - 1); ++i) {
1545 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1546 return MCDisassembler::Fail;
1547 }
1548
1549 return S;
1550}
1551
1552static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1553 uint64_t Address,
1554 const MCDisassembler *Decoder) {
1555 DecodeStatus S = MCDisassembler::Success;
1556
1557 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1558 unsigned regs = fieldFromInstruction(Val, 1, 7);
1559
1560 // In case of unpredictable encoding, tweak the operands.
1561 unsigned MaxReg = PermitsD32(Inst, Decoder) ? 32 : 16;
1562 if (regs == 0 || (Vd + regs) > MaxReg) {
1563 regs = Vd + regs > MaxReg ? MaxReg - Vd : regs;
1564 regs = std::max( 1u, regs);
1565 regs = std::min(MaxReg, regs);
1566 S = MCDisassembler::SoftFail;
1567 }
1568
1569 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1570 return MCDisassembler::Fail;
1571 for (unsigned i = 0; i < (regs - 1); ++i) {
1572 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1573 return MCDisassembler::Fail;
1574 }
1575
1576 return S;
1577}
1578
1579static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1580 uint64_t Address,
1581 const MCDisassembler *Decoder) {
1582 // This operand encodes a mask of contiguous zeros between a specified MSB
1583 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1584 // the mask of all bits LSB-and-lower, and then xor them to create
1585 // the mask of that's all ones on [msb, lsb]. Finally we not it to
1586 // create the final mask.
1587 unsigned msb = fieldFromInstruction(Val, 5, 5);
1588 unsigned lsb = fieldFromInstruction(Val, 0, 5);
1589
1590 DecodeStatus S = MCDisassembler::Success;
1591 if (lsb > msb) {
1592 Check(S, MCDisassembler::SoftFail);
1593 // The check above will cause the warning for the "potentially undefined
1594 // instruction encoding" but we can't build a bad MCOperand value here
1595 // with a lsb > msb or else printing the MCInst will cause a crash.
1596 lsb = msb;
1597 }
1598
1599 uint32_t msb_mask = 0xFFFFFFFF;
1600 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1601 uint32_t lsb_mask = (1U << lsb) - 1;
1602
1603 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask)));
1604 return S;
1605}
1606
1607static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
1608 uint64_t Address,
1609 const MCDisassembler *Decoder) {
1610 DecodeStatus S = MCDisassembler::Success;
1611
1612 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1613 unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1614 unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1615 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1616 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1617 unsigned U = fieldFromInstruction(Insn, 23, 1);
1618 const FeatureBitset &featureBits =
1619 Decoder->getSubtargetInfo().getFeatureBits();
1620
1621 switch (Inst.getOpcode()) {
1622 case ARM::LDC_OFFSET:
1623 case ARM::LDC_PRE:
1624 case ARM::LDC_POST:
1625 case ARM::LDC_OPTION:
1626 case ARM::LDCL_OFFSET:
1627 case ARM::LDCL_PRE:
1628 case ARM::LDCL_POST:
1629 case ARM::LDCL_OPTION:
1630 case ARM::STC_OFFSET:
1631 case ARM::STC_PRE:
1632 case ARM::STC_POST:
1633 case ARM::STC_OPTION:
1634 case ARM::STCL_OFFSET:
1635 case ARM::STCL_PRE:
1636 case ARM::STCL_POST:
1637 case ARM::STCL_OPTION:
1638 case ARM::t2LDC_OFFSET:
1639 case ARM::t2LDC_PRE:
1640 case ARM::t2LDC_POST:
1641 case ARM::t2LDC_OPTION:
1642 case ARM::t2LDCL_OFFSET:
1643 case ARM::t2LDCL_PRE:
1644 case ARM::t2LDCL_POST:
1645 case ARM::t2LDCL_OPTION:
1646 case ARM::t2STC_OFFSET:
1647 case ARM::t2STC_PRE:
1648 case ARM::t2STC_POST:
1649 case ARM::t2STC_OPTION:
1650 case ARM::t2STCL_OFFSET:
1651 case ARM::t2STCL_PRE:
1652 case ARM::t2STCL_POST:
1653 case ARM::t2STCL_OPTION:
1654 case ARM::t2LDC2_OFFSET:
1655 case ARM::t2LDC2L_OFFSET:
1656 case ARM::t2LDC2_PRE:
1657 case ARM::t2LDC2L_PRE:
1658 case ARM::t2STC2_OFFSET:
1659 case ARM::t2STC2L_OFFSET:
1660 case ARM::t2STC2_PRE:
1661 case ARM::t2STC2L_PRE:
1662 case ARM::LDC2_OFFSET:
1663 case ARM::LDC2L_OFFSET:
1664 case ARM::LDC2_PRE:
1665 case ARM::LDC2L_PRE:
1666 case ARM::STC2_OFFSET:
1667 case ARM::STC2L_OFFSET:
1668 case ARM::STC2_PRE:
1669 case ARM::STC2L_PRE:
1670 case ARM::t2LDC2_OPTION:
1671 case ARM::t2STC2_OPTION:
1672 case ARM::t2LDC2_POST:
1673 case ARM::t2LDC2L_POST:
1674 case ARM::t2STC2_POST:
1675 case ARM::t2STC2L_POST:
1676 case ARM::LDC2_POST:
1677 case ARM::LDC2L_POST:
1678 case ARM::STC2_POST:
1679 case ARM::STC2L_POST:
1680 if (coproc == 0xA || coproc == 0xB ||
1681 (featureBits[ARM::HasV8_1MMainlineOps] &&
1682 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB ||
1683 coproc == 0xE || coproc == 0xF)))
1684 return MCDisassembler::Fail;
1685 break;
1686 default:
1687 break;
1688 }
1689
1690 if (featureBits[ARM::HasV8Ops] && (coproc != 14))
1691 return MCDisassembler::Fail;
1692
1693 Inst.addOperand(MCOperand::createImm(coproc));
1694 Inst.addOperand(MCOperand::createImm(CRd));
1695 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1696 return MCDisassembler::Fail;
1697
1698 switch (Inst.getOpcode()) {
1699 case ARM::t2LDC2_OFFSET:
1700 case ARM::t2LDC2L_OFFSET:
1701 case ARM::t2LDC2_PRE:
1702 case ARM::t2LDC2L_PRE:
1703 case ARM::t2STC2_OFFSET:
1704 case ARM::t2STC2L_OFFSET:
1705 case ARM::t2STC2_PRE:
1706 case ARM::t2STC2L_PRE:
1707 case ARM::LDC2_OFFSET:
1708 case ARM::LDC2L_OFFSET:
1709 case ARM::LDC2_PRE:
1710 case ARM::LDC2L_PRE:
1711 case ARM::STC2_OFFSET:
1712 case ARM::STC2L_OFFSET:
1713 case ARM::STC2_PRE:
1714 case ARM::STC2L_PRE:
1715 case ARM::t2LDC_OFFSET:
1716 case ARM::t2LDCL_OFFSET:
1717 case ARM::t2LDC_PRE:
1718 case ARM::t2LDCL_PRE:
1719 case ARM::t2STC_OFFSET:
1720 case ARM::t2STCL_OFFSET:
1721 case ARM::t2STC_PRE:
1722 case ARM::t2STCL_PRE:
1723 case ARM::LDC_OFFSET:
1724 case ARM::LDCL_OFFSET:
1725 case ARM::LDC_PRE:
1726 case ARM::LDCL_PRE:
1727 case ARM::STC_OFFSET:
1728 case ARM::STCL_OFFSET:
1729 case ARM::STC_PRE:
1730 case ARM::STCL_PRE:
1731 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1732 Inst.addOperand(MCOperand::createImm(imm));
1733 break;
1734 case ARM::t2LDC2_POST:
1735 case ARM::t2LDC2L_POST:
1736 case ARM::t2STC2_POST:
1737 case ARM::t2STC2L_POST:
1738 case ARM::LDC2_POST:
1739 case ARM::LDC2L_POST:
1740 case ARM::STC2_POST:
1741 case ARM::STC2L_POST:
1742 case ARM::t2LDC_POST:
1743 case ARM::t2LDCL_POST:
1744 case ARM::t2STC_POST:
1745 case ARM::t2STCL_POST:
1746 case ARM::LDC_POST:
1747 case ARM::LDCL_POST:
1748 case ARM::STC_POST:
1749 case ARM::STCL_POST:
1750 imm |= U << 8;
1751 [[fallthrough]];
1752 default:
1753 // The 'option' variant doesn't encode 'U' in the immediate since
1754 // the immediate is unsigned [0,255].
1755 Inst.addOperand(MCOperand::createImm(imm));
1756 break;
1757 }
1758
1759 switch (Inst.getOpcode()) {
1760 case ARM::LDC_OFFSET:
1761 case ARM::LDC_PRE:
1762 case ARM::LDC_POST:
1763 case ARM::LDC_OPTION:
1764 case ARM::LDCL_OFFSET:
1765 case ARM::LDCL_PRE:
1766 case ARM::LDCL_POST:
1767 case ARM::LDCL_OPTION:
1768 case ARM::STC_OFFSET:
1769 case ARM::STC_PRE:
1770 case ARM::STC_POST:
1771 case ARM::STC_OPTION:
1772 case ARM::STCL_OFFSET:
1773 case ARM::STCL_PRE:
1774 case ARM::STCL_POST:
1775 case ARM::STCL_OPTION:
1776 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1777 return MCDisassembler::Fail;
1778 break;
1779 default:
1780 break;
1781 }
1782
1783 return S;
1784}
1785
1786static DecodeStatus
1787DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
1788 const MCDisassembler *Decoder) {
1789 DecodeStatus S = MCDisassembler::Success;
1790
1791 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1792 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1793 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1794 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1795 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1796 unsigned reg = fieldFromInstruction(Insn, 25, 1);
1797 unsigned P = fieldFromInstruction(Insn, 24, 1);
1798 unsigned W = fieldFromInstruction(Insn, 21, 1);
1799
1800 // On stores, the writeback operand precedes Rt.
1801 switch (Inst.getOpcode()) {
1802 case ARM::STR_POST_IMM:
1803 case ARM::STR_POST_REG:
1804 case ARM::STRB_POST_IMM:
1805 case ARM::STRB_POST_REG:
1806 case ARM::STRT_POST_REG:
1807 case ARM::STRT_POST_IMM:
1808 case ARM::STRBT_POST_REG:
1809 case ARM::STRBT_POST_IMM:
1810 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1811 return MCDisassembler::Fail;
1812 break;
1813 default:
1814 break;
1815 }
1816
1817 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1818 return MCDisassembler::Fail;
1819
1820 // On loads, the writeback operand comes after Rt.
1821 switch (Inst.getOpcode()) {
1822 case ARM::LDR_POST_IMM:
1823 case ARM::LDR_POST_REG:
1824 case ARM::LDRB_POST_IMM:
1825 case ARM::LDRB_POST_REG:
1826 case ARM::LDRBT_POST_REG:
1827 case ARM::LDRBT_POST_IMM:
1828 case ARM::LDRT_POST_REG:
1829 case ARM::LDRT_POST_IMM:
1830 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1831 return MCDisassembler::Fail;
1832 break;
1833 default:
1834 break;
1835 }
1836
1837 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1838 return MCDisassembler::Fail;
1839
1840 ARM_AM::AddrOpc Op = ARM_AM::add;
1841 if (!fieldFromInstruction(Insn, 23, 1))
1842 Op = ARM_AM::sub;
1843
1844 bool writeback = (P == 0) || (W == 1);
1845 unsigned idx_mode = 0;
1846 if (P && writeback)
1847 idx_mode = ARMII::IndexModePre;
1848 else if (!P && writeback)
1849 idx_mode = ARMII::IndexModePost;
1850
1851 if (writeback && (Rn == 15 || Rn == Rt))
1852 S = MCDisassembler::SoftFail; // UNPREDICTABLE
1853
1854 if (reg) {
1855 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1856 return MCDisassembler::Fail;
1857 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1858 switch( fieldFromInstruction(Insn, 5, 2)) {
1859 case 0:
1860 Opc = ARM_AM::lsl;
1861 break;
1862 case 1:
1863 Opc = ARM_AM::lsr;
1864 break;
1865 case 2:
1866 Opc = ARM_AM::asr;
1867 break;
1868 case 3:
1869 Opc = ARM_AM::ror;
1870 break;
1871 default:
1872 return MCDisassembler::Fail;
1873 }
1874 unsigned amt = fieldFromInstruction(Insn, 7, 5);
1875 if (Opc == ARM_AM::ror && amt == 0)
1876 Opc = ARM_AM::rrx;
1877 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1878
1879 Inst.addOperand(MCOperand::createImm(imm));
1880 } else {
1881 Inst.addOperand(MCOperand::createReg(0));
1882 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1883 Inst.addOperand(MCOperand::createImm(tmp));
1884 }
1885
1886 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1887 return MCDisassembler::Fail;
1888
1889 return S;
1890}
1891
1892static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
1893 uint64_t Address,
1894 const MCDisassembler *Decoder) {
1895 DecodeStatus S = MCDisassembler::Success;
1896
1897 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1898 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1899 unsigned type = fieldFromInstruction(Val, 5, 2);
1900 unsigned imm = fieldFromInstruction(Val, 7, 5);
1901 unsigned U = fieldFromInstruction(Val, 12, 1);
1902
1903 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1904 switch (type) {
1905 case 0:
1906 ShOp = ARM_AM::lsl;
1907 break;
1908 case 1:
1909 ShOp = ARM_AM::lsr;
1910 break;
1911 case 2:
1912 ShOp = ARM_AM::asr;
1913 break;
1914 case 3:
1915 ShOp = ARM_AM::ror;
1916 break;
1917 }
1918
1919 if (ShOp == ARM_AM::ror && imm == 0)
1920 ShOp = ARM_AM::rrx;
1921
1922 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1923 return MCDisassembler::Fail;
1924 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1925 return MCDisassembler::Fail;
1926 unsigned shift;
1927 if (U)
1928 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1929 else
1930 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1931 Inst.addOperand(MCOperand::createImm(shift));
1932
1933 return S;
1934}
1935
1936static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn,
1937 uint64_t Address,
1938 const MCDisassembler *Decoder) {
1939 if (Inst.getOpcode() != ARM::TSB && Inst.getOpcode() != ARM::t2TSB)
1940 return MCDisassembler::Fail;
1941
1942 // The "csync" operand is not encoded into the "tsb" instruction (as this is
1943 // the only available operand), but LLVM expects the instruction to have one
1944 // operand, so we need to add the csync when decoding.
1945 Inst.addOperand(MCOperand::createImm(ARM_TSB::CSYNC));
1946 return MCDisassembler::Success;
1947}
1948
1949static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
1950 uint64_t Address,
1951 const MCDisassembler *Decoder) {
1952 DecodeStatus S = MCDisassembler::Success;
1953
1954 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1955 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1956 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1957 unsigned type = fieldFromInstruction(Insn, 22, 1);
1958 unsigned imm = fieldFromInstruction(Insn, 8, 4);
1959 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1960 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1961 unsigned W = fieldFromInstruction(Insn, 21, 1);
1962 unsigned P = fieldFromInstruction(Insn, 24, 1);
1963 unsigned Rt2 = Rt + 1;
1964
1965 bool writeback = (W == 1) | (P == 0);
1966
1967 // For {LD,ST}RD, Rt must be even, else undefined.
1968 switch (Inst.getOpcode()) {
1969 case ARM::STRD:
1970 case ARM::STRD_PRE:
1971 case ARM::STRD_POST:
1972 case ARM::LDRD:
1973 case ARM::LDRD_PRE:
1974 case ARM::LDRD_POST:
1975 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1976 break;
1977 default:
1978 break;
1979 }
1980 switch (Inst.getOpcode()) {
1981 case ARM::STRD:
1982 case ARM::STRD_PRE:
1983 case ARM::STRD_POST:
1984 if (P == 0 && W == 1)
1985 S = MCDisassembler::SoftFail;
1986
1987 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1988 S = MCDisassembler::SoftFail;
1989 if (type && Rm == 15)
1990 S = MCDisassembler::SoftFail;
1991 if (Rt2 == 15)
1992 S = MCDisassembler::SoftFail;
1993 if (!type && fieldFromInstruction(Insn, 8, 4))
1994 S = MCDisassembler::SoftFail;
1995 break;
1996 case ARM::STRH:
1997 case ARM::STRH_PRE:
1998 case ARM::STRH_POST:
1999 if (Rt == 15)
2000 S = MCDisassembler::SoftFail;
2001 if (writeback && (Rn == 15 || Rn == Rt))
2002 S = MCDisassembler::SoftFail;
2003 if (!type && Rm == 15)
2004 S = MCDisassembler::SoftFail;
2005 break;
2006 case ARM::LDRD:
2007 case ARM::LDRD_PRE:
2008 case ARM::LDRD_POST:
2009 if (type && Rn == 15) {
2010 if (Rt2 == 15)
2011 S = MCDisassembler::SoftFail;
2012 break;
2013 }
2014 if (P == 0 && W == 1)
2015 S = MCDisassembler::SoftFail;
2016 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
2017 S = MCDisassembler::SoftFail;
2018 if (!type && writeback && Rn == 15)
2019 S = MCDisassembler::SoftFail;
2020 if (writeback && (Rn == Rt || Rn == Rt2))
2021 S = MCDisassembler::SoftFail;
2022 break;
2023 case ARM::LDRH:
2024 case ARM::LDRH_PRE:
2025 case ARM::LDRH_POST:
2026 if (type && Rn == 15) {
2027 if (Rt == 15)
2028 S = MCDisassembler::SoftFail;
2029 break;
2030 }
2031 if (Rt == 15)
2032 S = MCDisassembler::SoftFail;
2033 if (!type && Rm == 15)
2034 S = MCDisassembler::SoftFail;
2035 if (!type && writeback && (Rn == 15 || Rn == Rt))
2036 S = MCDisassembler::SoftFail;
2037 break;
2038 case ARM::LDRSH:
2039 case ARM::LDRSH_PRE:
2040 case ARM::LDRSH_POST:
2041 case ARM::LDRSB:
2042 case ARM::LDRSB_PRE:
2043 case ARM::LDRSB_POST:
2044 if (type && Rn == 15) {
2045 if (Rt == 15)
2046 S = MCDisassembler::SoftFail;
2047 break;
2048 }
2049 if (type && (Rt == 15 || (writeback && Rn == Rt)))
2050 S = MCDisassembler::SoftFail;
2051 if (!type && (Rt == 15 || Rm == 15))
2052 S = MCDisassembler::SoftFail;
2053 if (!type && writeback && (Rn == 15 || Rn == Rt))
2054 S = MCDisassembler::SoftFail;
2055 break;
2056 default:
2057 break;
2058 }
2059
2060 if (writeback) { // Writeback
2061 if (P)
2062 U |= ARMII::IndexModePre << 9;
2063 else
2064 U |= ARMII::IndexModePost << 9;
2065
2066 // On stores, the writeback operand precedes Rt.
2067 switch (Inst.getOpcode()) {
2068 case ARM::STRD:
2069 case ARM::STRD_PRE:
2070 case ARM::STRD_POST:
2071 case ARM::STRH:
2072 case ARM::STRH_PRE:
2073 case ARM::STRH_POST:
2074 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2075 return MCDisassembler::Fail;
2076 break;
2077 default:
2078 break;
2079 }
2080 }
2081
2082 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2083 return MCDisassembler::Fail;
2084 switch (Inst.getOpcode()) {
2085 case ARM::STRD:
2086 case ARM::STRD_PRE:
2087 case ARM::STRD_POST:
2088 case ARM::LDRD:
2089 case ARM::LDRD_PRE:
2090 case ARM::LDRD_POST:
2091 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
2092 return MCDisassembler::Fail;
2093 break;
2094 default:
2095 break;
2096 }
2097
2098 if (writeback) {
2099 // On loads, the writeback operand comes after Rt.
2100 switch (Inst.getOpcode()) {
2101 case ARM::LDRD:
2102 case ARM::LDRD_PRE:
2103 case ARM::LDRD_POST:
2104 case ARM::LDRH:
2105 case ARM::LDRH_PRE:
2106 case ARM::LDRH_POST:
2107 case ARM::LDRSH:
2108 case ARM::LDRSH_PRE:
2109 case ARM::LDRSH_POST:
2110 case ARM::LDRSB:
2111 case ARM::LDRSB_PRE:
2112 case ARM::LDRSB_POST:
2113 case ARM::LDRHTr:
2114 case ARM::LDRSBTr:
2115 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2116 return MCDisassembler::Fail;
2117 break;
2118 default:
2119 break;
2120 }
2121 }
2122
2123 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2124 return MCDisassembler::Fail;
2125
2126 if (type) {
2127 Inst.addOperand(MCOperand::createReg(0));
2128 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
2129 } else {
2130 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2131 return MCDisassembler::Fail;
2132 Inst.addOperand(MCOperand::createImm(U));
2133 }
2134
2135 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2136 return MCDisassembler::Fail;
2137
2138 return S;
2139}
2140
2141static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
2142 uint64_t Address,
2143 const MCDisassembler *Decoder) {
2144 DecodeStatus S = MCDisassembler::Success;
2145
2146 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2147 unsigned mode = fieldFromInstruction(Insn, 23, 2);
2148
2149 switch (mode) {
2150 case 0:
2151 mode = ARM_AM::da;
2152 break;
2153 case 1:
2154 mode = ARM_AM::ia;
2155 break;
2156 case 2:
2157 mode = ARM_AM::db;
2158 break;
2159 case 3:
2160 mode = ARM_AM::ib;
2161 break;
2162 }
2163
2164 Inst.addOperand(MCOperand::createImm(mode));
2165 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2166 return MCDisassembler::Fail;
2167
2168 return S;
2169}
2170
2171static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
2172 uint64_t Address,
2173 const MCDisassembler *Decoder) {
2174 DecodeStatus S = MCDisassembler::Success;
2175
2176 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2177 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2178 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2179 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2180
2181 if (pred == 0xF)
2182 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2183
2184 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2185 return MCDisassembler::Fail;
2186 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2187 return MCDisassembler::Fail;
2188 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2189 return MCDisassembler::Fail;
2190 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2191 return MCDisassembler::Fail;
2192 return S;
2193}
2194
2195static DecodeStatus
2196DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn,
2197 uint64_t Address,
2198 const MCDisassembler *Decoder) {
2199 DecodeStatus S = MCDisassembler::Success;
2200
2201 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2202 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2203 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
2204
2205 if (pred == 0xF) {
2206 // Ambiguous with RFE and SRS
2207 switch (Inst.getOpcode()) {
2208 case ARM::LDMDA:
2209 Inst.setOpcode(ARM::RFEDA);
2210 break;
2211 case ARM::LDMDA_UPD:
2212 Inst.setOpcode(ARM::RFEDA_UPD);
2213 break;
2214 case ARM::LDMDB:
2215 Inst.setOpcode(ARM::RFEDB);
2216 break;
2217 case ARM::LDMDB_UPD:
2218 Inst.setOpcode(ARM::RFEDB_UPD);
2219 break;
2220 case ARM::LDMIA:
2221 Inst.setOpcode(ARM::RFEIA);
2222 break;
2223 case ARM::LDMIA_UPD:
2224 Inst.setOpcode(ARM::RFEIA_UPD);
2225 break;
2226 case ARM::LDMIB:
2227 Inst.setOpcode(ARM::RFEIB);
2228 break;
2229 case ARM::LDMIB_UPD:
2230 Inst.setOpcode(ARM::RFEIB_UPD);
2231 break;
2232 case ARM::STMDA:
2233 Inst.setOpcode(ARM::SRSDA);
2234 break;
2235 case ARM::STMDA_UPD:
2236 Inst.setOpcode(ARM::SRSDA_UPD);
2237 break;
2238 case ARM::STMDB:
2239 Inst.setOpcode(ARM::SRSDB);
2240 break;
2241 case ARM::STMDB_UPD:
2242 Inst.setOpcode(ARM::SRSDB_UPD);
2243 break;
2244 case ARM::STMIA:
2245 Inst.setOpcode(ARM::SRSIA);
2246 break;
2247 case ARM::STMIA_UPD:
2248 Inst.setOpcode(ARM::SRSIA_UPD);
2249 break;
2250 case ARM::STMIB:
2251 Inst.setOpcode(ARM::SRSIB);
2252 break;
2253 case ARM::STMIB_UPD:
2254 Inst.setOpcode(ARM::SRSIB_UPD);
2255 break;
2256 default:
2257 return MCDisassembler::Fail;
2258 }
2259
2260 // For stores (which become SRS's, the only operand is the mode.
2261 if (fieldFromInstruction(Insn, 20, 1) == 0) {
2262 // Check SRS encoding constraints
2263 if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
2264 fieldFromInstruction(Insn, 20, 1) == 0))
2265 return MCDisassembler::Fail;
2266
2267 Inst.addOperand(
2268 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4)));
2269 return S;
2270 }
2271
2272 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
2273 }
2274
2275 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2276 return MCDisassembler::Fail;
2277 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2278 return MCDisassembler::Fail; // Tied
2279 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2280 return MCDisassembler::Fail;
2281 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
2282 return MCDisassembler::Fail;
2283
2284 return S;
2285}
2286
2287// Check for UNPREDICTABLE predicated ESB instruction
2288static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
2289 uint64_t Address,
2290 const MCDisassembler *Decoder) {
2291 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2292 unsigned imm8 = fieldFromInstruction(Insn, 0, 8);
2293 const FeatureBitset &FeatureBits =
2294 Decoder->getSubtargetInfo().getFeatureBits();
2295
2296 DecodeStatus S = MCDisassembler::Success;
2297
2298 Inst.addOperand(MCOperand::createImm(imm8));
2299
2300 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2301 return MCDisassembler::Fail;
2302
2303 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP,
2304 // so all predicates should be allowed.
2305 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
2306 S = MCDisassembler::SoftFail;
2307
2308 return S;
2309}
2310
2311static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
2312 uint64_t Address,
2313 const MCDisassembler *Decoder) {
2314 unsigned imod = fieldFromInstruction(Insn, 18, 2);
2315 unsigned M = fieldFromInstruction(Insn, 17, 1);
2316 unsigned iflags = fieldFromInstruction(Insn, 6, 3);
2317 unsigned mode = fieldFromInstruction(Insn, 0, 5);
2318
2319 DecodeStatus S = MCDisassembler::Success;
2320
2321 // This decoder is called from multiple location that do not check
2322 // the full encoding is valid before they do.
2323 if (fieldFromInstruction(Insn, 5, 1) != 0 ||
2324 fieldFromInstruction(Insn, 16, 1) != 0 ||
2325 fieldFromInstruction(Insn, 20, 8) != 0x10)
2326 return MCDisassembler::Fail;
2327
2328 // imod == '01' --> UNPREDICTABLE
2329 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2330 // return failure here. The '01' imod value is unprintable, so there's
2331 // nothing useful we could do even if we returned UNPREDICTABLE.
2332
2333 if (imod == 1) return MCDisassembler::Fail;
2334
2335 if (imod && M) {
2336 Inst.setOpcode(ARM::CPS3p);
2337 Inst.addOperand(MCOperand::createImm(imod));
2338 Inst.addOperand(MCOperand::createImm(iflags));
2339 Inst.addOperand(MCOperand::createImm(mode));
2340 } else if (imod && !M) {
2341 Inst.setOpcode(ARM::CPS2p);
2342 Inst.addOperand(MCOperand::createImm(imod));
2343 Inst.addOperand(MCOperand::createImm(iflags));
2344 if (mode) S = MCDisassembler::SoftFail;
2345 } else if (!imod && M) {
2346 Inst.setOpcode(ARM::CPS1p);
2347 Inst.addOperand(MCOperand::createImm(mode));
2348 if (iflags) S = MCDisassembler::SoftFail;
2349 } else {
2350 // imod == '00' && M == '0' --> UNPREDICTABLE
2351 Inst.setOpcode(ARM::CPS1p);
2352 Inst.addOperand(MCOperand::createImm(mode));
2353 S = MCDisassembler::SoftFail;
2354 }
2355
2356 return S;
2357}
2358
2359static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
2360 uint64_t Address,
2361 const MCDisassembler *Decoder) {
2362 unsigned imod = fieldFromInstruction(Insn, 9, 2);
2363 unsigned M = fieldFromInstruction(Insn, 8, 1);
2364 unsigned iflags = fieldFromInstruction(Insn, 5, 3);
2365 unsigned mode = fieldFromInstruction(Insn, 0, 5);
2366
2367 DecodeStatus S = MCDisassembler::Success;
2368
2369 // imod == '01' --> UNPREDICTABLE
2370 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2371 // return failure here. The '01' imod value is unprintable, so there's
2372 // nothing useful we could do even if we returned UNPREDICTABLE.
2373
2374 if (imod == 1) return MCDisassembler::Fail;
2375
2376 if (imod && M) {
2377 Inst.setOpcode(ARM::t2CPS3p);
2378 Inst.addOperand(MCOperand::createImm(imod));
2379 Inst.addOperand(MCOperand::createImm(iflags));
2380 Inst.addOperand(MCOperand::createImm(mode));
2381 } else if (imod && !M) {
2382 Inst.setOpcode(ARM::t2CPS2p);
2383 Inst.addOperand(MCOperand::createImm(imod));
2384 Inst.addOperand(MCOperand::createImm(iflags));
2385 if (mode) S = MCDisassembler::SoftFail;
2386 } else if (!imod && M) {
2387 Inst.setOpcode(ARM::t2CPS1p);
2388 Inst.addOperand(MCOperand::createImm(mode));
2389 if (iflags) S = MCDisassembler::SoftFail;
2390 } else {
2391 // imod == '00' && M == '0' --> this is a HINT instruction
2392 int imm = fieldFromInstruction(Insn, 0, 8);
2393 // HINT are defined only for immediate in [0..4]
2394 if(imm > 4) return MCDisassembler::Fail;
2395 Inst.setOpcode(ARM::t2HINT);
2396 Inst.addOperand(MCOperand::createImm(imm));
2397 }
2398
2399 return S;
2400}
2401
2402static DecodeStatus
2403DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
2404 const MCDisassembler *Decoder) {
2405 unsigned imm = fieldFromInstruction(Insn, 0, 8);
2406
2407 unsigned Opcode = ARM::t2HINT;
2408
2409 if (imm == 0x0D) {
2410 Opcode = ARM::t2PACBTI;
2411 } else if (imm == 0x1D) {
2412 Opcode = ARM::t2PAC;
2413 } else if (imm == 0x2D) {
2414 Opcode = ARM::t2AUT;
2415 } else if (imm == 0x0F) {
2416 Opcode = ARM::t2BTI;
2417 }
2418
2419 Inst.setOpcode(Opcode);
2420 if (Opcode == ARM::t2HINT) {
2421 Inst.addOperand(MCOperand::createImm(imm));
2422 }
2423
2424 return MCDisassembler::Success;
2425}
2426
2427static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
2428 uint64_t Address,
2429 const MCDisassembler *Decoder) {
2430 DecodeStatus S = MCDisassembler::Success;
2431
2432 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
2433 unsigned imm = 0;
2434
2435 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2436 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2437 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2438 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2439
2440 if (Inst.getOpcode() == ARM::t2MOVTi16)
2441 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2442 return MCDisassembler::Fail;
2443 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2444 return MCDisassembler::Fail;
2445
2446 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2447 Inst.addOperand(MCOperand::createImm(imm));
2448
2449 return S;
2450}
2451
2452static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
2453 uint64_t Address,
2454 const MCDisassembler *Decoder) {
2455 DecodeStatus S = MCDisassembler::Success;
2456
2457 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2458 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2459 unsigned imm = 0;
2460
2461 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2462 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2463
2464 if (Inst.getOpcode() == ARM::MOVTi16)
2465 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2466 return MCDisassembler::Fail;
2467
2468 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2469 return MCDisassembler::Fail;
2470
2471 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2472 Inst.addOperand(MCOperand::createImm(imm));
2473
2474 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2475 return MCDisassembler::Fail;
2476
2477 return S;
2478}
2479
2480static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
2481 uint64_t Address,
2482 const MCDisassembler *Decoder) {
2483 DecodeStatus S = MCDisassembler::Success;
2484
2485 unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2486 unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2487 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2488 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2489 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2490
2491 if (pred == 0xF)
2492 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2493
2494 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2495 return MCDisassembler::Fail;
2496 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2497 return MCDisassembler::Fail;
2498 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2499 return MCDisassembler::Fail;
2500 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2501 return MCDisassembler::Fail;
2502
2503 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2504 return MCDisassembler::Fail;
2505
2506 return S;
2507}
2508
2509static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
2510 uint64_t Address,
2511 const MCDisassembler *Decoder) {
2512 DecodeStatus S = MCDisassembler::Success;
2513
2514 unsigned Pred = fieldFromInstruction(Insn, 28, 4);
2515 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2516 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2517
2518 if (Pred == 0xF)
2519 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
2520
2521 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2522 return MCDisassembler::Fail;
2523 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2524 return MCDisassembler::Fail;
2525 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
2526 return MCDisassembler::Fail;
2527
2528 return S;
2529}
2530
2531static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
2532 uint64_t Address,
2533 const MCDisassembler *Decoder) {
2534 DecodeStatus S = MCDisassembler::Success;
2535
2536 unsigned Imm = fieldFromInstruction(Insn, 9, 1);
2537
2538 const FeatureBitset &FeatureBits =
2539 Decoder->getSubtargetInfo().getFeatureBits();
2540
2541 if (!FeatureBits[ARM::HasV8_1aOps] ||
2542 !FeatureBits[ARM::HasV8Ops])
2543 return MCDisassembler::Fail;
2544
2545 // Decoder can be called from DecodeTST, which does not check the full
2546 // encoding is valid.
2547 if (fieldFromInstruction(Insn, 20,12) != 0xf11 ||
2548 fieldFromInstruction(Insn, 4,4) != 0)
2549 return MCDisassembler::Fail;
2550 if (fieldFromInstruction(Insn, 10,10) != 0 ||
2551 fieldFromInstruction(Insn, 0,4) != 0)
2552 S = MCDisassembler::SoftFail;
2553
2554 Inst.setOpcode(ARM::SETPAN);
2555 Inst.addOperand(MCOperand::createImm(Imm));
2556
2557 return S;
2558}
2559
2560static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
2561 uint64_t Address,
2562 const MCDisassembler *Decoder) {
2563 DecodeStatus S = MCDisassembler::Success;
2564
2565 unsigned add = fieldFromInstruction(Val, 12, 1);
2566 unsigned imm = fieldFromInstruction(Val, 0, 12);
2567 unsigned Rn = fieldFromInstruction(Val, 13, 4);
2568
2569 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2570 return MCDisassembler::Fail;
2571
2572 if (!add) imm *= -1;
2573 if (imm == 0 && !add) imm = INT32_MIN;
2574 Inst.addOperand(MCOperand::createImm(imm));
2575 if (Rn == 15)
2576 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2577
2578 return S;
2579}
2580
2581static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2582 uint64_t Address,
2583 const MCDisassembler *Decoder) {
2584 DecodeStatus S = MCDisassembler::Success;
2585
2586 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2587 // U == 1 to add imm, 0 to subtract it.
2588 unsigned U = fieldFromInstruction(Val, 8, 1);
2589 unsigned imm = fieldFromInstruction(Val, 0, 8);
2590
2591 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2592 return MCDisassembler::Fail;
2593
2594 if (U)
2595 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2596 else
2597 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2598
2599 return S;
2600}
2601
2602static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
2603 uint64_t Address,
2604 const MCDisassembler *Decoder) {
2605 DecodeStatus S = MCDisassembler::Success;
2606
2607 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2608 // U == 1 to add imm, 0 to subtract it.
2609 unsigned U = fieldFromInstruction(Val, 8, 1);
2610 unsigned imm = fieldFromInstruction(Val, 0, 8);
2611
2612 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2613 return MCDisassembler::Fail;
2614
2615 if (U)
2616 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm)));
2617 else
2618 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm)));
2619
2620 return S;
2621}
2622
2623static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2624 uint64_t Address,
2625 const MCDisassembler *Decoder) {
2626 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2627}
2628
2629static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2630 uint64_t Address,
2631 const MCDisassembler *Decoder) {
2632 DecodeStatus Status = MCDisassembler::Success;
2633
2634 // Note the J1 and J2 values are from the encoded instruction. So here
2635 // change them to I1 and I2 values via as documented:
2636 // I1 = NOT(J1 EOR S);
2637 // I2 = NOT(J2 EOR S);
2638 // and build the imm32 with one trailing zero as documented:
2639 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2640 unsigned S = fieldFromInstruction(Insn, 26, 1);
2641 unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2642 unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2643 unsigned I1 = !(J1 ^ S);
2644 unsigned I2 = !(J2 ^ S);
2645 unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2646 unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2647 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2648 int imm32 = SignExtend32<25>(tmp << 1);
2649 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
2650 true, 4, Inst, Decoder))
2651 Inst.addOperand(MCOperand::createImm(imm32));
2652
2653 return Status;
2654}
2655
2656static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
2657 uint64_t Address,
2658 const MCDisassembler *Decoder) {
2659 DecodeStatus S = MCDisassembler::Success;
2660
2661 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2662 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2663
2664 if (pred == 0xF) {
2665 Inst.setOpcode(ARM::BLXi);
2666 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2667 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2668 true, 4, Inst, Decoder))
2669 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2670 return S;
2671 }
2672
2673 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2674 true, 4, Inst, Decoder))
2675 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2676
2677 // We already have BL_pred for BL w/ predicate, no need to add addition
2678 // predicate opreands for BL
2679 if (Inst.getOpcode() != ARM::BL)
2680 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2681 return MCDisassembler::Fail;
2682
2683 return S;
2684}
2685
2686static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2687 uint64_t Address,
2688 const MCDisassembler *Decoder) {
2689 DecodeStatus S = MCDisassembler::Success;
2690
2691 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2692 unsigned align = fieldFromInstruction(Val, 4, 2);
2693
2694 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2695 return MCDisassembler::Fail;
2696 if (!align)
2697 Inst.addOperand(MCOperand::createImm(0));
2698 else
2699 Inst.addOperand(MCOperand::createImm(4 << align));
2700
2701 return S;
2702}
2703
2704static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
2705 uint64_t Address,
2706 const MCDisassembler *Decoder) {
2707 DecodeStatus S = MCDisassembler::Success;
2708
2709 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2710 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2711 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2712 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2713 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2714 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2715
2716 // First output register
2717 switch (Inst.getOpcode()) {
2718 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2719 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2720 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2721 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2722 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2723 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2724 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2725 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2726 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2727 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2728 return MCDisassembler::Fail;
2729 break;
2730 case ARM::VLD2b16:
2731 case ARM::VLD2b32:
2732 case ARM::VLD2b8:
2733 case ARM::VLD2b16wb_fixed:
2734 case ARM::VLD2b16wb_register:
2735 case ARM::VLD2b32wb_fixed:
2736 case ARM::VLD2b32wb_register:
2737 case ARM::VLD2b8wb_fixed:
2738 case ARM::VLD2b8wb_register:
2739 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2740 return MCDisassembler::Fail;
2741 break;
2742 default:
2743 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2744 return MCDisassembler::Fail;
2745 }
2746
2747 // Second output register
2748 switch (Inst.getOpcode()) {
2749 case ARM::VLD3d8:
2750 case ARM::VLD3d16:
2751 case ARM::VLD3d32:
2752 case ARM::VLD3d8_UPD:
2753 case ARM::VLD3d16_UPD:
2754 case ARM::VLD3d32_UPD:
2755 case ARM::VLD4d8:
2756 case ARM::VLD4d16:
2757 case ARM::VLD4d32:
2758 case ARM::VLD4d8_UPD:
2759 case ARM::VLD4d16_UPD:
2760 case ARM::VLD4d32_UPD:
2761 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2762 return MCDisassembler::Fail;
2763 break;
2764 case ARM::VLD3q8:
2765 case ARM::VLD3q16:
2766 case ARM::VLD3q32:
2767 case ARM::VLD3q8_UPD:
2768 case ARM::VLD3q16_UPD:
2769 case ARM::VLD3q32_UPD:
2770 case ARM::VLD4q8:
2771 case ARM::VLD4q16:
2772 case ARM::VLD4q32:
2773 case ARM::VLD4q8_UPD:
2774 case ARM::VLD4q16_UPD:
2775 case ARM::VLD4q32_UPD:
2776 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2777 return MCDisassembler::Fail;
2778 break;
2779 default:
2780 break;
2781 }
2782
2783 // Third output register
2784 switch(Inst.getOpcode()) {
2785 case ARM::VLD3d8:
2786 case ARM::VLD3d16:
2787 case ARM::VLD3d32:
2788 case ARM::VLD3d8_UPD:
2789 case ARM::VLD3d16_UPD:
2790 case ARM::VLD3d32_UPD:
2791 case ARM::VLD4d8:
2792 case ARM::VLD4d16:
2793 case ARM::VLD4d32:
2794 case ARM::VLD4d8_UPD:
2795 case ARM::VLD4d16_UPD:
2796 case ARM::VLD4d32_UPD:
2797 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2798 return MCDisassembler::Fail;
2799 break;
2800 case ARM::VLD3q8:
2801 case ARM::VLD3q16:
2802 case ARM::VLD3q32:
2803 case ARM::VLD3q8_UPD:
2804 case ARM::VLD3q16_UPD:
2805 case ARM::VLD3q32_UPD:
2806 case ARM::VLD4q8:
2807 case ARM::VLD4q16:
2808 case ARM::VLD4q32:
2809 case ARM::VLD4q8_UPD:
2810 case ARM::VLD4q16_UPD:
2811 case ARM::VLD4q32_UPD:
2812 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2813 return MCDisassembler::Fail;
2814 break;
2815 default:
2816 break;
2817 }
2818
2819 // Fourth output register
2820 switch (Inst.getOpcode()) {
2821 case ARM::VLD4d8:
2822 case ARM::VLD4d16:
2823 case ARM::VLD4d32:
2824 case ARM::VLD4d8_UPD:
2825 case ARM::VLD4d16_UPD:
2826 case ARM::VLD4d32_UPD:
2827 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2828 return MCDisassembler::Fail;
2829 break;
2830 case ARM::VLD4q8:
2831 case ARM::VLD4q16:
2832 case ARM::VLD4q32:
2833 case ARM::VLD4q8_UPD:
2834 case ARM::VLD4q16_UPD:
2835 case ARM::VLD4q32_UPD:
2836 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2837 return MCDisassembler::Fail;
2838 break;
2839 default:
2840 break;
2841 }
2842
2843 // Writeback operand
2844 switch (Inst.getOpcode()) {
2845 case ARM::VLD1d8wb_fixed:
2846 case ARM::VLD1d16wb_fixed:
2847 case ARM::VLD1d32wb_fixed:
2848 case ARM::VLD1d64wb_fixed:
2849 case ARM::VLD1d8wb_register:
2850 case ARM::VLD1d16wb_register:
2851 case ARM::VLD1d32wb_register:
2852 case ARM::VLD1d64wb_register:
2853 case ARM::VLD1q8wb_fixed:
2854 case ARM::VLD1q16wb_fixed:
2855 case ARM::VLD1q32wb_fixed:
2856 case ARM::VLD1q64wb_fixed:
2857 case ARM::VLD1q8wb_register:
2858 case ARM::VLD1q16wb_register:
2859 case ARM::VLD1q32wb_register:
2860 case ARM::VLD1q64wb_register:
2861 case ARM::VLD1d8Twb_fixed:
2862 case ARM::VLD1d8Twb_register:
2863 case ARM::VLD1d16Twb_fixed:
2864 case ARM::VLD1d16Twb_register:
2865 case ARM::VLD1d32Twb_fixed:
2866 case ARM::VLD1d32Twb_register:
2867 case ARM::VLD1d64Twb_fixed:
2868 case ARM::VLD1d64Twb_register:
2869 case ARM::VLD1d8Qwb_fixed:
2870 case ARM::VLD1d8Qwb_register:
2871 case ARM::VLD1d16Qwb_fixed:
2872 case ARM::VLD1d16Qwb_register:
2873 case ARM::VLD1d32Qwb_fixed:
2874 case ARM::VLD1d32Qwb_register:
2875 case ARM::VLD1d64Qwb_fixed:
2876 case ARM::VLD1d64Qwb_register:
2877 case ARM::VLD2d8wb_fixed:
2878 case ARM::VLD2d16wb_fixed:
2879 case ARM::VLD2d32wb_fixed:
2880 case ARM::VLD2q8wb_fixed:
2881 case ARM::VLD2q16wb_fixed:
2882 case ARM::VLD2q32wb_fixed:
2883 case ARM::VLD2d8wb_register:
2884 case ARM::VLD2d16wb_register:
2885 case ARM::VLD2d32wb_register:
2886 case ARM::VLD2q8wb_register:
2887 case ARM::VLD2q16wb_register:
2888 case ARM::VLD2q32wb_register:
2889 case ARM::VLD2b8wb_fixed:
2890 case ARM::VLD2b16wb_fixed:
2891 case ARM::VLD2b32wb_fixed:
2892 case ARM::VLD2b8wb_register:
2893 case ARM::VLD2b16wb_register:
2894 case ARM::VLD2b32wb_register:
2895 Inst.addOperand(MCOperand::createImm(0));
2896 break;
2897 case ARM::VLD3d8_UPD:
2898 case ARM::VLD3d16_UPD:
2899 case ARM::VLD3d32_UPD:
2900 case ARM::VLD3q8_UPD:
2901 case ARM::VLD3q16_UPD:
2902 case ARM::VLD3q32_UPD:
2903 case ARM::VLD4d8_UPD:
2904 case ARM::VLD4d16_UPD:
2905 case ARM::VLD4d32_UPD:
2906 case ARM::VLD4q8_UPD:
2907 case ARM::VLD4q16_UPD:
2908 case ARM::VLD4q32_UPD:
2909 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2910 return MCDisassembler::Fail;
2911 break;
2912 default:
2913 break;
2914 }
2915
2916 // AddrMode6 Base (register+alignment)
2917 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2918 return MCDisassembler::Fail;
2919
2920 // AddrMode6 Offset (register)
2921 switch (Inst.getOpcode()) {
2922 default:
2923 // The below have been updated to have explicit am6offset split
2924 // between fixed and register offset. For those instructions not
2925 // yet updated, we need to add an additional reg0 operand for the
2926 // fixed variant.
2927 //
2928 // The fixed offset encodes as Rm == 0xd, so we check for that.
2929 if (Rm == 0xd) {
2930 Inst.addOperand(MCOperand::createReg(0));
2931 break;
2932 }
2933 // Fall through to handle the register offset variant.
2934 [[fallthrough]];
2935 case ARM::VLD1d8wb_fixed:
2936 case ARM::VLD1d16wb_fixed:
2937 case ARM::VLD1d32wb_fixed:
2938 case ARM::VLD1d64wb_fixed:
2939 case ARM::VLD1d8Twb_fixed:
2940 case ARM::VLD1d16Twb_fixed:
2941 case ARM::VLD1d32Twb_fixed:
2942 case ARM::VLD1d64Twb_fixed:
2943 case ARM::VLD1d8Qwb_fixed:
2944 case ARM::VLD1d16Qwb_fixed:
2945 case ARM::VLD1d32Qwb_fixed:
2946 case ARM::VLD1d64Qwb_fixed:
2947 case ARM::VLD1d8wb_register:
2948 case ARM::VLD1d16wb_register:
2949 case ARM::VLD1d32wb_register:
2950 case ARM::VLD1d64wb_register:
2951 case ARM::VLD1q8wb_fixed:
2952 case ARM::VLD1q16wb_fixed:
2953 case ARM::VLD1q32wb_fixed:
2954 case ARM::VLD1q64wb_fixed:
2955 case ARM::VLD1q8wb_register:
2956 case ARM::VLD1q16wb_register:
2957 case ARM::VLD1q32wb_register:
2958 case ARM::VLD1q64wb_register:
2959 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2960 // variant encodes Rm == 0xf. Anything else is a register offset post-
2961 // increment and we need to add the register operand to the instruction.
2962 if (Rm != 0xD && Rm != 0xF &&
2963 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2964 return MCDisassembler::Fail;
2965 break;
2966 case ARM::VLD2d8wb_fixed:
2967 case ARM::VLD2d16wb_fixed:
2968 case ARM::VLD2d32wb_fixed:
2969 case ARM::VLD2b8wb_fixed:
2970 case ARM::VLD2b16wb_fixed:
2971 case ARM::VLD2b32wb_fixed:
2972 case ARM::VLD2q8wb_fixed:
2973 case ARM::VLD2q16wb_fixed:
2974 case ARM::VLD2q32wb_fixed:
2975 break;
2976 }
2977
2978 return S;
2979}
2980
2981static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
2982 uint64_t Address,
2983 const MCDisassembler *Decoder) {
2984 unsigned type = fieldFromInstruction(Insn, 8, 4);
2985 unsigned align = fieldFromInstruction(Insn, 4, 2);
2986 if (type == 6 && (align & 2)) return MCDisassembler::Fail;
2987 if (type == 7 && (align & 2)) return MCDisassembler::Fail;
2988 if (type == 10 && align == 3) return MCDisassembler::Fail;
2989
2990 unsigned load = fieldFromInstruction(Insn, 21, 1);
2991 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2992 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2993}
2994
2995static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
2996 uint64_t Address,
2997 const MCDisassembler *Decoder) {
2998 unsigned size = fieldFromInstruction(Insn, 6, 2);
2999 if (size == 3) return MCDisassembler::Fail;
3000
3001 unsigned type = fieldFromInstruction(Insn, 8, 4);
3002 unsigned align = fieldFromInstruction(Insn, 4, 2);
3003 if (type == 8 && align == 3) return MCDisassembler::Fail;
3004 if (type == 9 && align == 3) return MCDisassembler::Fail;
3005
3006 unsigned load = fieldFromInstruction(Insn, 21, 1);
3007 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
3008 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
3009}
3010
3011static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
3012 uint64_t Address,
3013 const MCDisassembler *Decoder) {
3014 unsigned size = fieldFromInstruction(Insn, 6, 2);
3015 if (size == 3) return MCDisassembler::Fail;
3016
3017 unsigned align = fieldFromInstruction(Insn, 4, 2);
3018 if (align & 2) return MCDisassembler::Fail;
3019
3020 unsigned load = fieldFromInstruction(Insn, 21, 1);
3021 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
3022 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
3023}
3024
3025static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
3026 uint64_t Address,
3027 const MCDisassembler *Decoder) {
3028 unsigned size = fieldFromInstruction(Insn, 6, 2);
3029 if (size == 3) return MCDisassembler::Fail;
3030
3031 unsigned load = fieldFromInstruction(Insn, 21, 1);
3032 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
3033 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
3034}
3035
3036static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
3037 uint64_t Address,
3038 const MCDisassembler *Decoder) {
3039 DecodeStatus S = MCDisassembler::Success;
3040
3041 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3042 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3043 unsigned wb = fieldFromInstruction(Insn, 16, 4);
3044 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3045 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
3046 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3047
3048 // Writeback Operand
3049 switch (Inst.getOpcode()) {
3050 case ARM::VST1d8wb_fixed:
3051 case ARM::VST1d16wb_fixed:
3052 case ARM::VST1d32wb_fixed:
3053 case ARM::VST1d64wb_fixed:
3054 case ARM::VST1d8wb_register:
3055 case ARM::VST1d16wb_register:
3056 case ARM::VST1d32wb_register:
3057 case ARM::VST1d64wb_register:
3058 case ARM::VST1q8wb_fixed:
3059 case ARM::VST1q16wb_fixed:
3060 case ARM::VST1q32wb_fixed:
3061 case ARM::VST1q64wb_fixed:
3062 case ARM::VST1q8wb_register:
3063 case ARM::VST1q16wb_register:
3064 case ARM::VST1q32wb_register:
3065 case ARM::VST1q64wb_register:
3066 case ARM::VST1d8Twb_fixed:
3067 case ARM::VST1d16Twb_fixed:
3068 case ARM::VST1d32Twb_fixed:
3069 case ARM::VST1d64Twb_fixed:
3070 case ARM::VST1d8Twb_register:
3071 case ARM::VST1d16Twb_register:
3072 case ARM::VST1d32Twb_register:
3073 case ARM::VST1d64Twb_register:
3074 case ARM::VST1d8Qwb_fixed:
3075 case ARM::VST1d16Qwb_fixed:
3076 case ARM::VST1d32Qwb_fixed:
3077 case ARM::VST1d64Qwb_fixed:
3078 case ARM::VST1d8Qwb_register:
3079 case ARM::VST1d16Qwb_register:
3080 case ARM::VST1d32Qwb_register:
3081 case ARM::VST1d64Qwb_register:
3082 case ARM::VST2d8wb_fixed:
3083 case ARM::VST2d16wb_fixed:
3084 case ARM::VST2d32wb_fixed:
3085 case ARM::VST2d8wb_register:
3086 case ARM::VST2d16wb_register:
3087 case ARM::VST2d32wb_register:
3088 case ARM::VST2q8wb_fixed:
3089 case ARM::VST2q16wb_fixed:
3090 case ARM::VST2q32wb_fixed:
3091 case ARM::VST2q8wb_register:
3092 case ARM::VST2q16wb_register:
3093 case ARM::VST2q32wb_register:
3094 case ARM::VST2b8wb_fixed:
3095 case ARM::VST2b16wb_fixed:
3096 case ARM::VST2b32wb_fixed:
3097 case ARM::VST2b8wb_register:
3098 case ARM::VST2b16wb_register:
3099 case ARM::VST2b32wb_register:
3100 if (Rm == 0xF)
3101 return MCDisassembler::Fail;
3102 Inst.addOperand(MCOperand::createImm(0));
3103 break;
3104 case ARM::VST3d8_UPD:
3105 case ARM::VST3d16_UPD:
3106 case ARM::VST3d32_UPD:
3107 case ARM::VST3q8_UPD:
3108 case ARM::VST3q16_UPD:
3109 case ARM::VST3q32_UPD:
3110 case ARM::VST4d8_UPD:
3111 case ARM::VST4d16_UPD:
3112 case ARM::VST4d32_UPD:
3113 case ARM::VST4q8_UPD:
3114 case ARM::VST4q16_UPD:
3115 case ARM::VST4q32_UPD:
3116 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
3117 return MCDisassembler::Fail;
3118 break;
3119 default:
3120 break;
3121 }
3122
3123 // AddrMode6 Base (register+alignment)
3124 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
3125 return MCDisassembler::Fail;
3126
3127 // AddrMode6 Offset (register)
3128 switch (Inst.getOpcode()) {
3129 default:
3130 if (Rm == 0xD)
3131 Inst.addOperand(MCOperand::createReg(0));
3132 else if (Rm != 0xF) {
3133 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3134 return MCDisassembler::Fail;
3135 }
3136 break;
3137 case ARM::VST1d8wb_fixed:
3138 case ARM::VST1d16wb_fixed:
3139 case ARM::VST1d32wb_fixed:
3140 case ARM::VST1d64wb_fixed:
3141 case ARM::VST1q8wb_fixed:
3142 case ARM::VST1q16wb_fixed:
3143 case ARM::VST1q32wb_fixed:
3144 case ARM::VST1q64wb_fixed:
3145 case ARM::VST1d8Twb_fixed:
3146 case ARM::VST1d16Twb_fixed:
3147 case ARM::VST1d32Twb_fixed:
3148 case ARM::VST1d64Twb_fixed:
3149 case ARM::VST1d8Qwb_fixed:
3150 case ARM::VST1d16Qwb_fixed:
3151 case ARM::VST1d32Qwb_fixed:
3152 case ARM::VST1d64Qwb_fixed:
3153 case ARM::VST2d8wb_fixed:
3154 case ARM::VST2d16wb_fixed:
3155 case ARM::VST2d32wb_fixed:
3156 case ARM::VST2q8wb_fixed:
3157 case ARM::VST2q16wb_fixed:
3158 case ARM::VST2q32wb_fixed:
3159 case ARM::VST2b8wb_fixed:
3160 case ARM::VST2b16wb_fixed:
3161 case ARM::VST2b32wb_fixed:
3162 break;
3163 }
3164
3165 // First input register
3166 switch (Inst.getOpcode()) {
3167 case ARM::VST1q16:
3168 case ARM::VST1q32:
3169 case ARM::VST1q64:
3170 case ARM::VST1q8:
3171 case ARM::VST1q16wb_fixed:
3172 case ARM::VST1q16wb_register:
3173 case ARM::VST1q32wb_fixed:
3174 case ARM::VST1q32wb_register:
3175 case ARM::VST1q64wb_fixed:
3176 case ARM::VST1q64wb_register:
3177 case ARM::VST1q8wb_fixed:
3178 case ARM::VST1q8wb_register:
3179 case ARM::VST2d16:
3180 case ARM::VST2d32:
3181 case ARM::VST2d8:
3182 case ARM::VST2d16wb_fixed:
3183 case ARM::VST2d16wb_register:
3184 case ARM::VST2d32wb_fixed:
3185 case ARM::VST2d32wb_register:
3186 case ARM::VST2d8wb_fixed:
3187 case ARM::VST2d8wb_register:
3188 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
3189 return MCDisassembler::Fail;
3190 break;
3191 case ARM::VST2b16:
3192 case ARM::VST2b32:
3193 case ARM::VST2b8:
3194 case ARM::VST2b16wb_fixed:
3195 case ARM::VST2b16wb_register:
3196 case ARM::VST2b32wb_fixed:
3197 case ARM::VST2b32wb_register:
3198 case ARM::VST2b8wb_fixed:
3199 case ARM::VST2b8wb_register:
3200 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
3201 return MCDisassembler::Fail;
3202 break;
3203 default:
3204 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3205 return MCDisassembler::Fail;
3206 }
3207
3208 // Second input register
3209 switch (Inst.getOpcode()) {
3210 case ARM::VST3d8:
3211 case ARM::VST3d16:
3212 case ARM::VST3d32:
3213 case ARM::VST3d8_UPD:
3214 case ARM::VST3d16_UPD:
3215 case ARM::VST3d32_UPD:
3216 case ARM::VST4d8:
3217 case ARM::VST4d16:
3218 case ARM::VST4d32:
3219 case ARM::VST4d8_UPD:
3220 case ARM::VST4d16_UPD:
3221 case ARM::VST4d32_UPD:
3222 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
3223 return MCDisassembler::Fail;
3224 break;
3225 case ARM::VST3q8:
3226 case ARM::VST3q16:
3227 case ARM::VST3q32:
3228 case ARM::VST3q8_UPD:
3229 case ARM::VST3q16_UPD:
3230 case ARM::VST3q32_UPD:
3231 case ARM::VST4q8:
3232 case ARM::VST4q16:
3233 case ARM::VST4q32:
3234 case ARM::VST4q8_UPD:
3235 case ARM::VST4q16_UPD:
3236 case ARM::VST4q32_UPD:
3237 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
3238 return MCDisassembler::Fail;
3239 break;
3240 default:
3241 break;
3242 }
3243
3244 // Third input register
3245 switch (Inst.getOpcode()) {
3246 case ARM::VST3d8:
3247 case ARM::VST3d16:
3248 case ARM::VST3d32:
3249 case ARM::VST3d8_UPD:
3250 case ARM::VST3d16_UPD:
3251 case ARM::VST3d32_UPD:
3252 case ARM::VST4d8:
3253 case ARM::VST4d16:
3254 case ARM::VST4d32:
3255 case ARM::VST4d8_UPD:
3256 case ARM::VST4d16_UPD:
3257 case ARM::VST4d32_UPD:
3258 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
3259 return MCDisassembler::Fail;
3260 break;
3261 case ARM::VST3q8:
3262 case ARM::VST3q16:
3263 case ARM::VST3q32:
3264 case ARM::VST3q8_UPD:
3265 case ARM::VST3q16_UPD:
3266 case ARM::VST3q32_UPD:
3267 case ARM::VST4q8:
3268 case ARM::VST4q16:
3269 case ARM::VST4q32:
3270 case ARM::VST4q8_UPD:
3271 case ARM::VST4q16_UPD:
3272 case ARM::VST4q32_UPD:
3273 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
3274 return MCDisassembler::Fail;
3275 break;
3276 default:
3277 break;
3278 }
3279
3280 // Fourth input register
3281 switch (Inst.getOpcode()) {
3282 case ARM::VST4d8:
3283 case ARM::VST4d16:
3284 case ARM::VST4d32:
3285 case ARM::VST4d8_UPD:
3286 case ARM::VST4d16_UPD:
3287 case ARM::VST4d32_UPD:
3288 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
3289 return MCDisassembler::Fail;
3290 break;
3291 case ARM::VST4q8:
3292 case ARM::VST4q16:
3293 case ARM::VST4q32:
3294 case ARM::VST4q8_UPD:
3295 case ARM::VST4q16_UPD:
3296 case ARM::VST4q32_UPD:
3297 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
3298 return MCDisassembler::Fail;
3299 break;
3300 default:
3301 break;
3302 }
3303
3304 return S;
3305}
3306
3307static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
3308 uint64_t Address,
3309 const MCDisassembler *Decoder) {
3310 DecodeStatus S = MCDisassembler::Success;
3311
3312 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3313 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3314 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3315 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3316 unsigned align = fieldFromInstruction(Insn, 4, 1);
3317 unsigned size = fieldFromInstruction(Insn, 6, 2);
3318
3319 if (size == 0 && align == 1)
3320 return MCDisassembler::Fail;
3321 align *= (1 << size);
3322
3323 switch (Inst.getOpcode()) {
3324 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
3325 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
3326 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
3327 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
3328 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
3329 return MCDisassembler::Fail;
3330 break;
3331 default:
3332 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3333 return MCDisassembler::Fail;
3334 break;
3335 }
3336 if (Rm != 0xF) {
3337 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3338 return MCDisassembler::Fail;
3339 }
3340
3341 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3342 return MCDisassembler::Fail;
3343 Inst.addOperand(MCOperand::createImm(align));
3344
3345 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
3346 // variant encodes Rm == 0xf. Anything else is a register offset post-
3347 // increment and we need to add the register operand to the instruction.
3348 if (Rm != 0xD && Rm != 0xF &&
3349 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3350 return MCDisassembler::Fail;
3351
3352 return S;
3353}
3354
3355static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
3356 uint64_t Address,
3357 const MCDisassembler *Decoder) {
3358 DecodeStatus S = MCDisassembler::Success;
3359
3360 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3361 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3362 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3363 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3364 unsigned align = fieldFromInstruction(Insn, 4, 1);
3365 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
3366 align *= 2*size;
3367
3368 switch (Inst.getOpcode()) {
3369 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
3370 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
3371 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
3372 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
3373 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
3374 return MCDisassembler::Fail;
3375 break;
3376 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
3377 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
3378 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
3379 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
3380 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
3381 return MCDisassembler::Fail;
3382 break;
3383 default:
3384 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3385 return MCDisassembler::Fail;
3386 break;
3387 }
3388
3389 if (Rm != 0xF)
3390 Inst.addOperand(MCOperand::createImm(0));
3391
3392 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3393 return MCDisassembler::Fail;
3394 Inst.addOperand(MCOperand::createImm(align));
3395
3396 if (Rm != 0xD && Rm != 0xF) {
3397 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3398 return MCDisassembler::Fail;
3399 }
3400
3401 return S;
3402}
3403
3404static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
3405 uint64_t Address,
3406 const MCDisassembler *Decoder) {
3407 DecodeStatus S = MCDisassembler::Success;
3408
3409 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3410 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3411 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3412 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3413 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3414
3415 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3416 return MCDisassembler::Fail;
3417 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3418 return MCDisassembler::Fail;
3419 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3420 return MCDisassembler::Fail;
3421 if (Rm != 0xF) {
3422 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3423 return MCDisassembler::Fail;
3424 }
3425
3426 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3427 return MCDisassembler::Fail;
3428 Inst.addOperand(MCOperand::createImm(0));
3429
3430 if (Rm == 0xD)
3431 Inst.addOperand(MCOperand::createReg(0));
3432 else if (Rm != 0xF) {
3433 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3434 return MCDisassembler::Fail;
3435 }
3436
3437 return S;
3438}
3439
3440static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
3441 uint64_t Address,
3442 const MCDisassembler *Decoder) {
3443 DecodeStatus S = MCDisassembler::Success;
3444
3445 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3446 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3447 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3448 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3449 unsigned size = fieldFromInstruction(Insn, 6, 2);
3450 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3451 unsigned align = fieldFromInstruction(Insn, 4, 1);
3452
3453 if (size == 0x3) {
3454 if (align == 0)
3455 return MCDisassembler::Fail;
3456 align = 16;
3457 } else {
3458 if (size == 2) {
3459 align *= 8;
3460 } else {
3461 size = 1 << size;
3462 align *= 4*size;
3463 }
3464 }
3465
3466 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3467 return MCDisassembler::Fail;
3468 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3469 return MCDisassembler::Fail;
3470 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3471 return MCDisassembler::Fail;
3472 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
3473 return MCDisassembler::Fail;
3474 if (Rm != 0xF) {
3475 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3476 return MCDisassembler::Fail;
3477 }
3478
3479 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3480 return MCDisassembler::Fail;
3481 Inst.addOperand(MCOperand::createImm(align));
3482
3483 if (Rm == 0xD)
3484 Inst.addOperand(MCOperand::createReg(0));
3485 else if (Rm != 0xF) {
3486 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3487 return MCDisassembler::Fail;
3488 }
3489
3490 return S;
3491}
3492
3493static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn,
3494 uint64_t Address,
3495 const MCDisassembler *Decoder) {
3496 DecodeStatus S = MCDisassembler::Success;
3497
3498 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3499 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3500 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3501 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3502 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3503 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3504 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3505 unsigned Q = fieldFromInstruction(Insn, 6, 1);
3506
3507 if (Q) {
3508 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3509 return MCDisassembler::Fail;
3510 } else {
3511 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3512 return MCDisassembler::Fail;
3513 }
3514
3515 Inst.addOperand(MCOperand::createImm(imm));
3516
3517 switch (Inst.getOpcode()) {
3518 case ARM::VORRiv4i16:
3519 case ARM::VORRiv2i32:
3520 case ARM::VBICiv4i16:
3521 case ARM::VBICiv2i32:
3522 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3523 return MCDisassembler::Fail;
3524 break;
3525 case ARM::VORRiv8i16:
3526 case ARM::VORRiv4i32:
3527 case ARM::VBICiv8i16:
3528 case ARM::VBICiv4i32:
3529 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3530 return MCDisassembler::Fail;
3531 break;
3532 default:
3533 break;
3534 }
3535
3536 return S;
3537}
3538
3539static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn,
3540 uint64_t Address,
3541 const MCDisassembler *Decoder) {
3542 DecodeStatus S = MCDisassembler::Success;
3543
3544 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
3545 fieldFromInstruction(Insn, 13, 3));
3546 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
3547 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3548 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3549 imm |= fieldFromInstruction(Insn, 28, 1) << 7;
3550 imm |= cmode << 8;
3551 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3552
3553 if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32)
3554 return MCDisassembler::Fail;
3555
3556 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
3557 return MCDisassembler::Fail;
3558
3559 Inst.addOperand(MCOperand::createImm(imm));
3560
3561 Inst.addOperand(MCOperand::createImm(ARMVCC::None));
3562 Inst.addOperand(MCOperand::createReg(0));
3563 Inst.addOperand(MCOperand::createImm(0));
3564
3565 return S;
3566}
3567
3568static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn,
3569 uint64_t Address,
3570 const MCDisassembler *Decoder) {
3571 DecodeStatus S = MCDisassembler::Success;
3572
3573 unsigned Qd = fieldFromInstruction(Insn, 13, 3);
3574 Qd |= fieldFromInstruction(Insn, 22, 1) << 3;
3575 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
3576 return MCDisassembler::Fail;
3577 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
3578
3579 unsigned Qn = fieldFromInstruction(Insn, 17, 3);
3580 Qn |= fieldFromInstruction(Insn, 7, 1) << 3;
3581 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))
3582 return MCDisassembler::Fail;
3583 unsigned Qm = fieldFromInstruction(Insn, 1, 3);
3584 Qm |= fieldFromInstruction(Insn, 5, 1) << 3;
3585 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
3586 return MCDisassembler::Fail;
3587 if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR
3588 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
3589 Inst.addOperand(MCOperand::createImm(Qd));
3590
3591 return S;
3592}
3593
3594static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
3595 uint64_t Address,
3596 const MCDisassembler *Decoder) {
3597 DecodeStatus S = MCDisassembler::Success;
3598
3599 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3600 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3601 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3602 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3603 unsigned size = fieldFromInstruction(Insn, 18, 2);
3604
3605 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3606 return MCDisassembler::Fail;
3607 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3608 return MCDisassembler::Fail;
3609 Inst.addOperand(MCOperand::createImm(8 << size));
3610
3611 return S;
3612}
3613
3614static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
3615 uint64_t Address,
3616 const MCDisassembler *Decoder) {
3617 Inst.addOperand(MCOperand::createImm(8 - Val));
3618 return MCDisassembler::Success;
3619}
3620
3621static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
3622 uint64_t Address,
3623 const MCDisassembler *Decoder) {
3624 Inst.addOperand(MCOperand::createImm(16 - Val));
3625 return MCDisassembler::Success;
3626}
3627
3628static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
3629 uint64_t Address,
3630 const MCDisassembler *Decoder) {
3631 Inst.addOperand(MCOperand::createImm(32 - Val));
3632 return MCDisassembler::Success;
3633}
3634
3635static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
3636 uint64_t Address,
3637 const MCDisassembler *Decoder) {
3638 Inst.addOperand(MCOperand::createImm(64 - Val));
3639 return MCDisassembler::Success;
3640}
3641
3642static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
3643 uint64_t Address,
3644 const MCDisassembler *Decoder) {
3645 DecodeStatus S = MCDisassembler::Success;
3646
3647 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3648 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3649 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3650 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3651 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3652 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3653 unsigned op = fieldFromInstruction(Insn, 6, 1);
3654
3655 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3656 return MCDisassembler::Fail;
3657 if (op) {
3658 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3659 return MCDisassembler::Fail; // Writeback
3660 }
3661
3662 switch (Inst.getOpcode()) {
3663 case ARM::VTBL2:
3664 case ARM::VTBX2:
3665 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3666 return MCDisassembler::Fail;
3667 break;
3668 default:
3669 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3670 return MCDisassembler::Fail;
3671 }
3672
3673 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3674 return MCDisassembler::Fail;
3675
3676 return S;
3677}
3678
3679static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
3680 uint64_t Address,
3681 const MCDisassembler *Decoder) {
3682 DecodeStatus S = MCDisassembler::Success;
3683
3684 unsigned dst = fieldFromInstruction(Insn, 8, 3);
3685 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3686
3687 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3688 return MCDisassembler::Fail;
3689
3690 switch(Inst.getOpcode()) {
3691 default:
3692 return MCDisassembler::Fail;
3693 case ARM::tADR:
3694 break; // tADR does not explicitly represent the PC as an operand.
3695 case ARM::tADDrSPi:
3696 Inst.addOperand(MCOperand::createReg(ARM::SP));
3697 break;
3698 }
3699
3700 Inst.addOperand(MCOperand::createImm(imm));
3701 return S;
3702}
3703
3704static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3705 uint64_t Address,
3706 const MCDisassembler *Decoder) {
3707 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3708 true, 2, Inst, Decoder))
3709 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1)));
3710 return MCDisassembler::Success;
3711}
3712
3713static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3714 uint64_t Address,
3715 const MCDisassembler *Decoder) {
3716 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
3717 true, 4, Inst, Decoder))
3718 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val)));
3719 return MCDisassembler::Success;
3720}
3721
3722static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3723 uint64_t Address,
3724 const MCDisassembler *Decoder) {
3725 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
3726 true, 2, Inst, Decoder))
3727 Inst.addOperand(MCOperand::createImm(Val << 1));
3728 return MCDisassembler::Success;
3729}
3730
3731static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3732 uint64_t Address,
3733 const MCDisassembler *Decoder) {
3734 DecodeStatus S = MCDisassembler::Success;
3735
3736 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3737 unsigned Rm = fieldFromInstruction(Val, 3, 3);
3738
3739 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3740 return MCDisassembler::Fail;
3741 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3742 return MCDisassembler::Fail;
3743
3744 return S;
3745}
3746
3747static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3748 uint64_t Address,
3749 const MCDisassembler *Decoder) {
3750 DecodeStatus S = MCDisassembler::Success;
3751
3752 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3753 unsigned imm = fieldFromInstruction(Val, 3, 5);
3754
3755 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3756 return MCDisassembler::Fail;
3757 Inst.addOperand(MCOperand::createImm(imm));
3758
3759 return S;
3760}
3761
3762static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
3763 uint64_t Address,
3764 const MCDisassembler *Decoder) {
3765 unsigned imm = Val << 2;
3766
3767 Inst.addOperand(MCOperand::createImm(imm));
3768 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3769
3770 return MCDisassembler::Success;
3771}
3772
3773static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
3774 uint64_t Address,
3775 const MCDisassembler *Decoder) {
3776 Inst.addOperand(MCOperand::createReg(ARM::SP));
3777 Inst.addOperand(MCOperand::createImm(Val));
3778
3779 return MCDisassembler::Success;
3780}
3781
3782static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
3783 uint64_t Address,
3784 const MCDisassembler *Decoder) {
3785 DecodeStatus S = MCDisassembler::Success;
3786
3787 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3788 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3789 unsigned imm = fieldFromInstruction(Val, 0, 2);
3790
3791 // Thumb stores cannot use PC as dest register.
3792 switch (Inst.getOpcode()) {
3793 case ARM::t2STRHs:
3794 case ARM::t2STRBs:
3795 case ARM::t2STRs:
3796 if (Rn == 15)
3797 return MCDisassembler::Fail;
3798 break;
3799 default:
3800 break;
3801 }
3802
3803 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3804 return MCDisassembler::Fail;
3805 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3806 return MCDisassembler::Fail;
3807 Inst.addOperand(MCOperand::createImm(imm));
3808
3809 return S;
3810}
3811
3812static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
3813 uint64_t Address,
3814 const MCDisassembler *Decoder) {
3815 DecodeStatus S = MCDisassembler::Success;
3816
3817 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3818 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3819
3820 const FeatureBitset &featureBits =
3821 Decoder->getSubtargetInfo().getFeatureBits();
3822
3823 bool hasMP = featureBits[ARM::FeatureMP];
3824 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3825
3826 if (Rn == 15) {
3827 switch (Inst.getOpcode()) {
3828 case ARM::t2LDRBs:
3829 Inst.setOpcode(ARM::t2LDRBpci);
3830 break;
3831 case ARM::t2LDRHs:
3832 Inst.setOpcode(ARM::t2LDRHpci);
3833 break;
3834 case ARM::t2LDRSHs:
3835 Inst.setOpcode(ARM::t2LDRSHpci);
3836 break;
3837 case ARM::t2LDRSBs:
3838 Inst.setOpcode(ARM::t2LDRSBpci);
3839 break;
3840 case ARM::t2LDRs:
3841 Inst.setOpcode(ARM::t2LDRpci);
3842 break;
3843 case ARM::t2PLDs:
3844 Inst.setOpcode(ARM::t2PLDpci);
3845 break;
3846 case ARM::t2PLIs:
3847 Inst.setOpcode(ARM::t2PLIpci);
3848 break;
3849 default:
3850 return MCDisassembler::Fail;
3851 }
3852
3853 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3854 }
3855
3856 if (Rt == 15) {
3857 switch (Inst.getOpcode()) {
3858 case ARM::t2LDRSHs:
3859 return MCDisassembler::Fail;
3860 case ARM::t2LDRHs:
3861 Inst.setOpcode(ARM::t2PLDWs);
3862 break;
3863 case ARM::t2LDRSBs:
3864 Inst.setOpcode(ARM::t2PLIs);
3865 break;
3866 default:
3867 break;
3868 }
3869 }
3870
3871 switch (Inst.getOpcode()) {
3872 case ARM::t2PLDs:
3873 break;
3874 case ARM::t2PLIs:
3875 if (!hasV7Ops)
3876 return MCDisassembler::Fail;
3877 break;
3878 case ARM::t2PLDWs:
3879 if (!hasV7Ops || !hasMP)
3880 return MCDisassembler::Fail;
3881 break;
3882 default:
3883 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3884 return MCDisassembler::Fail;
3885 }
3886
3887 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3888 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3889 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3890 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3891 return MCDisassembler::Fail;
3892
3893 return S;
3894}
3895
3896static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
3897 uint64_t Address,
3898 const MCDisassembler *Decoder) {
3899 DecodeStatus S = MCDisassembler::Success;
3900
3901 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3902 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3903 unsigned U = fieldFromInstruction(Insn, 9, 1);
3904 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3905 imm |= (U << 8);
3906 imm |= (Rn << 9);
3907 unsigned add = fieldFromInstruction(Insn, 9, 1);
3908
3909 const FeatureBitset &featureBits =
3910 Decoder->getSubtargetInfo().getFeatureBits();
3911
3912 bool hasMP = featureBits[ARM::FeatureMP];
3913 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3914
3915 if (Rn == 15) {
3916 switch (Inst.getOpcode()) {
3917 case ARM::t2LDRi8:
3918 Inst.setOpcode(ARM::t2LDRpci);
3919 break;
3920 case ARM::t2LDRBi8:
3921 Inst.setOpcode(ARM::t2LDRBpci);
3922 break;
3923 case ARM::t2LDRSBi8:
3924 Inst.setOpcode(ARM::t2LDRSBpci);
3925 break;
3926 case ARM::t2LDRHi8:
3927 Inst.setOpcode(ARM::t2LDRHpci);
3928 break;
3929 case ARM::t2LDRSHi8:
3930 Inst.setOpcode(ARM::t2LDRSHpci);
3931 break;
3932 case ARM::t2PLDi8:
3933 Inst.setOpcode(ARM::t2PLDpci);
3934 break;
3935 case ARM::t2PLIi8:
3936 Inst.setOpcode(ARM::t2PLIpci);
3937 break;
3938 default:
3939 return MCDisassembler::Fail;
3940 }
3941 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3942 }
3943
3944 if (Rt == 15) {
3945 switch (Inst.getOpcode()) {
3946 case ARM::t2LDRSHi8:
3947 return MCDisassembler::Fail;
3948 case ARM::t2LDRHi8:
3949 if (!add)
3950 Inst.setOpcode(ARM::t2PLDWi8);
3951 break;
3952 case ARM::t2LDRSBi8:
3953 Inst.setOpcode(ARM::t2PLIi8);
3954 break;
3955 default:
3956 break;
3957 }
3958 }
3959
3960 switch (Inst.getOpcode()) {
3961 case ARM::t2PLDi8:
3962 break;
3963 case ARM::t2PLIi8:
3964 if (!hasV7Ops)
3965 return MCDisassembler::Fail;
3966 break;
3967 case ARM::t2PLDWi8:
3968 if (!hasV7Ops || !hasMP)
3969 return MCDisassembler::Fail;
3970 break;
3971 default:
3972 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3973 return MCDisassembler::Fail;
3974 }
3975
3976 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3977 return MCDisassembler::Fail;
3978 return S;
3979}
3980
3981static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
3982 uint64_t Address,
3983 const MCDisassembler *Decoder) {
3984 DecodeStatus S = MCDisassembler::Success;
3985
3986 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3987 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3988 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3989 imm |= (Rn << 13);
3990
3991 const FeatureBitset &featureBits =
3992 Decoder->getSubtargetInfo().getFeatureBits();
3993
3994 bool hasMP = featureBits[ARM::FeatureMP];
3995 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3996
3997 if (Rn == 15) {
3998 switch (Inst.getOpcode()) {
3999 case ARM::t2LDRi12:
4000 Inst.setOpcode(ARM::t2LDRpci);
4001 break;
4002 case ARM::t2LDRHi12:
4003 Inst.setOpcode(ARM::t2LDRHpci);
4004 break;
4005 case ARM::t2LDRSHi12:
4006 Inst.setOpcode(ARM::t2LDRSHpci);
4007 break;
4008 case ARM::t2LDRBi12:
4009 Inst.setOpcode(ARM::t2LDRBpci);
4010 break;
4011 case ARM::t2LDRSBi12:
4012 Inst.setOpcode(ARM::t2LDRSBpci);
4013 break;
4014 case ARM::t2PLDi12:
4015 Inst.setOpcode(ARM::t2PLDpci);
4016 break;
4017 case ARM::t2PLIi12:
4018 Inst.setOpcode(ARM::t2PLIpci);
4019 break;
4020 default:
4021 return MCDisassembler::Fail;
4022 }
4023 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4024 }
4025
4026 if (Rt == 15) {
4027 switch (Inst.getOpcode()) {
4028 case ARM::t2LDRSHi12:
4029 return MCDisassembler::Fail;
4030 case ARM::t2LDRHi12:
4031 Inst.setOpcode(ARM::t2PLDWi12);
4032 break;
4033 case ARM::t2LDRSBi12:
4034 Inst.setOpcode(ARM::t2PLIi12);
4035 break;
4036 default:
4037 break;
4038 }
4039 }
4040
4041 switch (Inst.getOpcode()) {
4042 case ARM::t2PLDi12:
4043 break;
4044 case ARM::t2PLIi12:
4045 if (!hasV7Ops)
4046 return MCDisassembler::Fail;
4047 break;
4048 case ARM::t2PLDWi12:
4049 if (!hasV7Ops || !hasMP)
4050 return MCDisassembler::Fail;
4051 break;
4052 default:
4053 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4054 return MCDisassembler::Fail;
4055 }
4056
4057 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
4058 return MCDisassembler::Fail;
4059 return S;
4060}
4061
4062static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address,
4063 const MCDisassembler *Decoder) {
4064 DecodeStatus S = MCDisassembler::Success;
4065
4066 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4067 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4068 unsigned imm = fieldFromInstruction(Insn, 0, 8);
4069 imm |= (Rn << 9);
4070
4071 if (Rn == 15) {
4072 switch (Inst.getOpcode()) {
4073 case ARM::t2LDRT:
4074 Inst.setOpcode(ARM::t2LDRpci);
4075 break;
4076 case ARM::t2LDRBT:
4077 Inst.setOpcode(ARM::t2LDRBpci);
4078 break;
4079 case ARM::t2LDRHT:
4080 Inst.setOpcode(ARM::t2LDRHpci);
4081 break;
4082 case ARM::t2LDRSBT:
4083 Inst.setOpcode(ARM::t2LDRSBpci);
4084 break;
4085 case ARM::t2LDRSHT:
4086 Inst.setOpcode(ARM::t2LDRSHpci);
4087 break;
4088 default:
4089 return MCDisassembler::Fail;
4090 }
4091 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4092 }
4093
4094 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4095 return MCDisassembler::Fail;
4096 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
4097 return MCDisassembler::Fail;
4098 return S;
4099}
4100
4101static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
4102 uint64_t Address,
4103 const MCDisassembler *Decoder) {
4104 DecodeStatus S = MCDisassembler::Success;
4105
4106 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4107 unsigned U = fieldFromInstruction(Insn, 23, 1);
4108 int imm = fieldFromInstruction(Insn, 0, 12);
4109
4110 const FeatureBitset &featureBits =
4111 Decoder->getSubtargetInfo().getFeatureBits();
4112
4113 bool hasV7Ops = featureBits[ARM::HasV7Ops];
4114
4115 if (Rt == 15) {
4116 switch (Inst.getOpcode()) {
4117 case ARM::t2LDRBpci:
4118 case ARM::t2LDRHpci:
4119 Inst.setOpcode(ARM::t2PLDpci);
4120 break;
4121 case ARM::t2LDRSBpci:
4122 Inst.setOpcode(ARM::t2PLIpci);
4123 break;
4124 case ARM::t2LDRSHpci:
4125 return MCDisassembler::Fail;
4126 default:
4127 break;
4128 }
4129 }
4130
4131 switch(Inst.getOpcode()) {
4132 case ARM::t2PLDpci:
4133 break;
4134 case ARM::t2PLIpci:
4135 if (!hasV7Ops)
4136 return MCDisassembler::Fail;
4137 break;
4138 default:
4139 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4140 return MCDisassembler::Fail;
4141 }
4142
4143 if (!U) {
4144 // Special case for #-0.
4145 if (imm == 0)
4146 imm = INT32_MIN;
4147 else
4148 imm = -imm;
4149 }
4150 Inst.addOperand(MCOperand::createImm(imm));
4151
4152 return S;
4153}
4154
4155static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address,
4156 const MCDisassembler *Decoder) {
4157 if (Val == 0)
4158 Inst.addOperand(MCOperand::createImm(INT32_MIN));
4159 else {
4160 int imm = Val & 0xFF;
4161
4162 if (!(Val & 0x100)) imm *= -1;
4163 Inst.addOperand(MCOperand::createImm(imm * 4));
4164 }
4165
4166 return MCDisassembler::Success;
4167}
4168
4169static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address,
4170 const MCDisassembler *Decoder) {
4171 if (Val == 0)
4172 Inst.addOperand(MCOperand::createImm(INT32_MIN));
4173 else {
4174 int imm = Val & 0x7F;
4175
4176 if (!(Val & 0x80))
4177 imm *= -1;
4178 Inst.addOperand(MCOperand::createImm(imm * 4));
4179 }
4180
4181 return MCDisassembler::Success;
4182}
4183
4184static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
4185 uint64_t Address,
4186 const MCDisassembler *Decoder) {
4187 DecodeStatus S = MCDisassembler::Success;
4188
4189 unsigned Rn = fieldFromInstruction(Val, 9, 4);
4190 unsigned imm = fieldFromInstruction(Val, 0, 9);
4191
4192 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4193 return MCDisassembler::Fail;
4194 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
4195 return MCDisassembler::Fail;
4196
4197 return S;
4198}
4199
4200static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val,
4201 uint64_t Address,
4202 const MCDisassembler *Decoder) {
4203 DecodeStatus S = MCDisassembler::Success;
4204
4205 unsigned Rn = fieldFromInstruction(Val, 8, 4);
4206 unsigned imm = fieldFromInstruction(Val, 0, 8);
4207
4208 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4209 return MCDisassembler::Fail;
4210 if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder)))
4211 return MCDisassembler::Fail;
4212
4213 return S;
4214}
4215
4216static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst, unsigned Val,
4217 uint64_t Address,
4218 const MCDisassembler *Decoder) {
4219 DecodeStatus S = MCDisassembler::Success;
4220
4221 unsigned Rn = fieldFromInstruction(Val, 8, 4);
4222 unsigned imm = fieldFromInstruction(Val, 0, 8);
4223
4224 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4225 return MCDisassembler::Fail;
4226
4227 Inst.addOperand(MCOperand::createImm(imm));
4228
4229 return S;
4230}
4231
4232static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address,
4233 const MCDisassembler *Decoder) {
4234 int imm = Val & 0xFF;
4235 if (Val == 0)
4236 imm = INT32_MIN;
4237 else if (!(Val & 0x100))
4238 imm *= -1;
4239 Inst.addOperand(MCOperand::createImm(imm));
4240
4241 return MCDisassembler::Success;
4242}
4243
4244template <int shift>
4245static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address,
4246 const MCDisassembler *Decoder) {
4247 int imm = Val & 0x7F;
4248 if (Val == 0)
4249 imm = INT32_MIN;
4250 else if (!(Val & 0x80))
4251 imm *= -1;
4252 if (imm != INT32_MIN)
4253 imm *= (1U << shift);
4254 Inst.addOperand(MCOperand::createImm(imm));
4255
4256 return MCDisassembler::Success;
4257}
4258
4259static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
4260 uint64_t Address,
4261 const MCDisassembler *Decoder) {
4262 DecodeStatus S = MCDisassembler::Success;
4263
4264 unsigned Rn = fieldFromInstruction(Val, 9, 4);
4265 unsigned imm = fieldFromInstruction(Val, 0, 9);
4266
4267 // Thumb stores cannot use PC as dest register.
4268 switch (Inst.getOpcode()) {
4269 case ARM::t2STRT:
4270 case ARM::t2STRBT:
4271 case ARM::t2STRHT:
4272 case ARM::t2STRi8:
4273 case ARM::t2STRHi8:
4274 case ARM::t2STRBi8:
4275 if (Rn == 15)
4276 return MCDisassembler::Fail;
4277 break;
4278 default:
4279 break;
4280 }
4281
4282 // Some instructions always use an additive offset.
4283 switch (Inst.getOpcode()) {
4284 case ARM::t2LDRT:
4285 case ARM::t2LDRBT:
4286 case ARM::t2LDRHT:
4287 case ARM::t2LDRSBT:
4288 case ARM::t2LDRSHT:
4289 case ARM::t2STRT:
4290 case ARM::t2STRBT:
4291 case ARM::t2STRHT:
4292 imm |= 0x100;
4293 break;
4294 default:
4295 break;
4296 }
4297
4298 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4299 return MCDisassembler::Fail;
4300 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
4301 return MCDisassembler::Fail;
4302
4303 return S;
4304}
4305
4306template <int shift>
4307static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val,
4308 uint64_t Address,
4309 const MCDisassembler *Decoder) {
4310 DecodeStatus S = MCDisassembler::Success;
4311
4312 unsigned Rn = fieldFromInstruction(Val, 8, 3);
4313 unsigned imm = fieldFromInstruction(Val, 0, 8);
4314
4315 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
4316 return MCDisassembler::Fail;
4317 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
4318 return MCDisassembler::Fail;
4319
4320 return S;
4321}
4322
4323template <int shift, int WriteBack>
4324static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val,
4325 uint64_t Address,
4326 const MCDisassembler *Decoder) {
4327 DecodeStatus S = MCDisassembler::Success;
4328
4329 unsigned Rn = fieldFromInstruction(Val, 8, 4);
4330 unsigned imm = fieldFromInstruction(Val, 0, 8);
4331 if (WriteBack) {
4332 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4333 return MCDisassembler::Fail;
4334 } else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4335 return MCDisassembler::Fail;
4336 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
4337 return MCDisassembler::Fail;
4338
4339 return S;
4340}
4341
4342static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
4343 uint64_t Address,
4344 const MCDisassembler *Decoder) {
4345 DecodeStatus S = MCDisassembler::Success;
4346
4347 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4348 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4349 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4350 addr |= fieldFromInstruction(Insn, 9, 1) << 8;
4351 addr |= Rn << 9;
4352 unsigned load = fieldFromInstruction(Insn, 20, 1);
4353
4354 if (Rn == 15) {
4355 switch (Inst.getOpcode()) {
4356 case ARM::t2LDR_PRE:
4357 case ARM::t2LDR_POST:
4358 Inst.setOpcode(ARM::t2LDRpci);
4359 break;
4360 case ARM::t2LDRB_PRE:
4361 case ARM::t2LDRB_POST:
4362 Inst.setOpcode(ARM::t2LDRBpci);
4363 break;
4364 case ARM::t2LDRH_PRE:
4365 case ARM::t2LDRH_POST:
4366 Inst.setOpcode(ARM::t2LDRHpci);
4367 break;
4368 case ARM::t2LDRSB_PRE:
4369 case ARM::t2LDRSB_POST:
4370 if (Rt == 15)
4371 Inst.setOpcode(ARM::t2PLIpci);
4372 else
4373 Inst.setOpcode(ARM::t2LDRSBpci);
4374 break;
4375 case ARM::t2LDRSH_PRE:
4376 case ARM::t2LDRSH_POST:
4377 Inst.setOpcode(ARM::t2LDRSHpci);
4378 break;
4379 default:
4380 return MCDisassembler::Fail;
4381 }
4382 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4383 }
4384
4385 if (!load) {
4386 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4387 return MCDisassembler::Fail;
4388 }
4389
4390 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4391 return MCDisassembler::Fail;
4392
4393 if (load) {
4394 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4395 return MCDisassembler::Fail;
4396 }
4397
4398 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
4399 return MCDisassembler::Fail;
4400
4401 return S;
4402}
4403
4404static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
4405 uint64_t Address,
4406 const MCDisassembler *Decoder) {
4407 DecodeStatus S = MCDisassembler::Success;
4408
4409 unsigned Rn = fieldFromInstruction(Val, 13, 4);
4410 unsigned imm = fieldFromInstruction(Val, 0, 12);
4411
4412 // Thumb stores cannot use PC as dest register.
4413 switch (Inst.getOpcode()) {
4414 case ARM::t2STRi12:
4415 case ARM::t2STRBi12:
4416 case ARM::t2STRHi12:
4417 if (Rn == 15)
4418 return MCDisassembler::Fail;
4419 break;
4420 default:
4421 break;
4422 }
4423
4424 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4425 return MCDisassembler::Fail;
4426 Inst.addOperand(MCOperand::createImm(imm));
4427
4428 return S;
4429}
4430
4431static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
4432 uint64_t Address,
4433 const MCDisassembler *Decoder) {
4434 unsigned imm = fieldFromInstruction(Insn, 0, 7);
4435
4436 Inst.addOperand(MCOperand::createReg(ARM::SP));
4437 Inst.addOperand(MCOperand::createReg(ARM::SP));
4438 Inst.addOperand(MCOperand::createImm(imm));
4439
4440 return MCDisassembler::Success;
4441}
4442
4443static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
4444 uint64_t Address,
4445 const MCDisassembler *Decoder) {
4446 DecodeStatus S = MCDisassembler::Success;
4447
4448 if (Inst.getOpcode() == ARM::tADDrSP) {
4449 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
4450 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
4451
4452 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
4453 return MCDisassembler::Fail;
4454 Inst.addOperand(MCOperand::createReg(ARM::SP));
4455 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
4456 return MCDisassembler::Fail;
4457 } else if (Inst.getOpcode() == ARM::tADDspr) {
4458 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
4459
4460 Inst.addOperand(MCOperand::createReg(ARM::SP));
4461 Inst.addOperand(MCOperand::createReg(ARM::SP));
4462 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4463 return MCDisassembler::Fail;
4464 }
4465
4466 return S;
4467}
4468
4469static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
4470 uint64_t Address,
4471 const MCDisassembler *Decoder) {
4472 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
4473 unsigned flags = fieldFromInstruction(Insn, 0, 3);
4474
4475 Inst.addOperand(MCOperand::createImm(imod));
4476 Inst.addOperand(MCOperand::createImm(flags));
4477
4478 return MCDisassembler::Success;
4479}
4480
4481static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
4482 uint64_t Address,
4483 const MCDisassembler *Decoder) {
4484 DecodeStatus S = MCDisassembler::Success;
4485 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4486 unsigned add = fieldFromInstruction(Insn, 4, 1);
4487
4488 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
4489 return MCDisassembler::Fail;
4490 Inst.addOperand(MCOperand::createImm(add));
4491
4492 return S;
4493}
4494
4495static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn,
4496 uint64_t Address,
4497 const MCDisassembler *Decoder) {
4498 DecodeStatus S = MCDisassembler::Success;
4499 unsigned Rn = fieldFromInstruction(Insn, 3, 4);
4500 unsigned Qm = fieldFromInstruction(Insn, 0, 3);
4501
4502 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4503 return MCDisassembler::Fail;
4504 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
4505 return MCDisassembler::Fail;
4506
4507 return S;
4508}
4509
4510template <int shift>
4511static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn,
4512 uint64_t Address,
4513 const MCDisassembler *Decoder) {
4514 DecodeStatus S = MCDisassembler::Success;
4515 unsigned Qm = fieldFromInstruction(Insn, 8, 3);
4516 int imm = fieldFromInstruction(Insn, 0, 7);
4517
4518 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
4519 return MCDisassembler::Fail;
4520
4521 if(!fieldFromInstruction(Insn, 7, 1)) {
4522 if (imm == 0)
4523 imm = INT32_MIN; // indicate -0
4524 else
4525 imm *= -1;
4526 }
4527 if (imm != INT32_MIN)
4528 imm *= (1U << shift);
4529 Inst.addOperand(MCOperand::createImm(imm));
4530
4531 return S;
4532}
4533
4534static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
4535 uint64_t Address,
4536 const MCDisassembler *Decoder) {
4537 // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
4538 // Note only one trailing zero not two. Also the J1 and J2 values are from
4539 // the encoded instruction. So here change to I1 and I2 values via:
4540 // I1 = NOT(J1 EOR S);
4541 // I2 = NOT(J2 EOR S);
4542 // and build the imm32 with two trailing zeros as documented:
4543 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
4544 unsigned S = (Val >> 23) & 1;
4545 unsigned J1 = (Val >> 22) & 1;
4546 unsigned J2 = (Val >> 21) & 1;
4547 unsigned I1 = !(J1 ^ S);
4548 unsigned I2 = !(J2 ^ S);
4549 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4550 int imm32 = SignExtend32<25>(tmp << 1);
4551
4552 if (!tryAddingSymbolicOperand(Address,
4553 (Address & ~2u) + imm32 + 4,
4554 true, 4, Inst, Decoder))
4555 Inst.addOperand(MCOperand::createImm(imm32));
4556 return MCDisassembler::Success;
4557}
4558
4559static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
4560 uint64_t Address,
4561 const MCDisassembler *Decoder) {
4562 if (Val == 0xA || Val == 0xB)
4563 return MCDisassembler::Fail;
4564
4565 const FeatureBitset &featureBits =
4566 Decoder->getSubtargetInfo().getFeatureBits();
4567
4568 if (!isValidCoprocessorNumber(Val, featureBits))
4569 return MCDisassembler::Fail;
4570
4571 Inst.addOperand(MCOperand::createImm(Val));
4572 return MCDisassembler::Success;
4573}
4574
4575static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
4576 uint64_t Address,
4577 const MCDisassembler *Decoder) {
4578 const FeatureBitset &FeatureBits =
4579 Decoder->getSubtargetInfo().getFeatureBits();
4580 DecodeStatus S = MCDisassembler::Success;
4581
4582 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4583 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4584
4585 if (Rn == 13 && !FeatureBits[ARM::HasV8Ops]) S = MCDisassembler::SoftFail;
4586 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4587 return MCDisassembler::Fail;
4588 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
4589 return MCDisassembler::Fail;
4590 return S;
4591}
4592
4593static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
4594 uint64_t Address,
4595 const MCDisassembler *Decoder) {
4596 DecodeStatus S = MCDisassembler::Success;
4597
4598 unsigned pred = fieldFromInstruction(Insn, 22, 4);
4599 if (pred == 0xE || pred == 0xF) {
4600 unsigned opc = fieldFromInstruction(Insn, 4, 28);
4601 switch (opc) {
4602 default:
4603 return MCDisassembler::Fail;
4604 case 0xf3bf8f4:
4605 Inst.setOpcode(ARM::t2DSB);
4606 break;
4607 case 0xf3bf8f5:
4608 Inst.setOpcode(ARM::t2DMB);
4609 break;
4610 case 0xf3bf8f6:
4611 Inst.setOpcode(ARM::t2ISB);
4612 break;
4613 }
4614
4615 unsigned imm = fieldFromInstruction(Insn, 0, 4);
4616 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
4617 }
4618
4619 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
4620 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
4621 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
4622 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
4623 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
4624
4625 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
4626 return MCDisassembler::Fail;
4627 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4628 return MCDisassembler::Fail;
4629
4630 return S;
4631}
4632
4633// Decode a shifted immediate operand. These basically consist
4634// of an 8-bit value, and a 4-bit directive that specifies either
4635// a splat operation or a rotation.
4636static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address,
4637 const MCDisassembler *Decoder) {
4638 unsigned ctrl = fieldFromInstruction(Val, 10, 2);
4639 if (ctrl == 0) {
4640 unsigned byte = fieldFromInstruction(Val, 8, 2);
4641 unsigned imm = fieldFromInstruction(Val, 0, 8);
4642 switch (byte) {
4643 case 0:
4644 Inst.addOperand(MCOperand::createImm(imm));
4645 break;
4646 case 1:
4647 Inst.addOperand(MCOperand::createImm((imm << 16) | imm));
4648 break;
4649 case 2:
4650 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8)));
4651 break;
4652 case 3:
4653 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) |
4654 (imm << 8) | imm));
4655 break;
4656 }
4657 } else {
4658 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
4659 unsigned rot = fieldFromInstruction(Val, 7, 5);
4660 unsigned imm = llvm::rotr<uint32_t>(unrot, rot);
4661 Inst.addOperand(MCOperand::createImm(imm));
4662 }
4663
4664 return MCDisassembler::Success;
4665}
4666
4667static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
4668 uint64_t Address,
4669 const MCDisassembler *Decoder) {
4670 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
4671 true, 2, Inst, Decoder))
4672 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1)));
4673 return MCDisassembler::Success;
4674}
4675
4676static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
4677 uint64_t Address,
4678 const MCDisassembler *Decoder) {
4679 // Val is passed in as S:J1:J2:imm10:imm11
4680 // Note no trailing zero after imm11. Also the J1 and J2 values are from
4681 // the encoded instruction. So here change to I1 and I2 values via:
4682 // I1 = NOT(J1 EOR S);
4683 // I2 = NOT(J2 EOR S);
4684 // and build the imm32 with one trailing zero as documented:
4685 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
4686 unsigned S = (Val >> 23) & 1;
4687 unsigned J1 = (Val >> 22) & 1;
4688 unsigned J2 = (Val >> 21) & 1;
4689 unsigned I1 = !(J1 ^ S);
4690 unsigned I2 = !(J2 ^ S);
4691 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4692 int imm32 = SignExtend32<25>(tmp << 1);
4693
4694 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
4695 true, 4, Inst, Decoder))
4696 Inst.addOperand(MCOperand::createImm(imm32));
4697 return MCDisassembler::Success;
4698}
4699
4700static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
4701 uint64_t Address,
4702 const MCDisassembler *Decoder) {
4703 if (Val & ~0xf)
4704 return MCDisassembler::Fail;
4705
4706 Inst.addOperand(MCOperand::createImm(Val));
4707 return MCDisassembler::Success;
4708}
4709
4710static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
4711 uint64_t Address,
4712 const MCDisassembler *Decoder) {
4713 if (Val & ~0xf)
4714 return MCDisassembler::Fail;
4715
4716 Inst.addOperand(MCOperand::createImm(Val));
4717 return MCDisassembler::Success;
4718}
4719
4720static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, uint64_t Address,
4721 const MCDisassembler *Decoder) {
4722 DecodeStatus S = MCDisassembler::Success;
4723 const FeatureBitset &FeatureBits =
4724 Decoder->getSubtargetInfo().getFeatureBits();
4725
4726 if (FeatureBits[ARM::FeatureMClass]) {
4727 unsigned ValLow = Val & 0xff;
4728
4729 // Validate the SYSm value first.
4730 switch (ValLow) {
4731 case 0: // apsr
4732 case 1: // iapsr
4733 case 2: // eapsr
4734 case 3: // xpsr
4735 case 5: // ipsr
4736 case 6: // epsr
4737 case 7: // iepsr
4738 case 8: // msp
4739 case 9: // psp
4740 case 16: // primask
4741 case 20: // control
4742 break;
4743 case 17: // basepri
4744 case 18: // basepri_max
4745 case 19: // faultmask
4746 if (!(FeatureBits[ARM::HasV7Ops]))
4747 // Values basepri, basepri_max and faultmask are only valid for v7m.
4748 return MCDisassembler::Fail;
4749 break;
4750 case 0x8a: // msplim_ns
4751 case 0x8b: // psplim_ns
4752 case 0x91: // basepri_ns
4753 case 0x93: // faultmask_ns
4754 if (!(FeatureBits[ARM::HasV8MMainlineOps]))
4755 return MCDisassembler::Fail;
4756 [[fallthrough]];
4757 case 10: // msplim
4758 case 11: // psplim
4759 case 0x88: // msp_ns
4760 case 0x89: // psp_ns
4761 case 0x90: // primask_ns
4762 case 0x94: // control_ns
4763 case 0x98: // sp_ns
4764 if (!(FeatureBits[ARM::Feature8MSecExt]))
4765 return MCDisassembler::Fail;
4766 break;
4767 case 0x20: // pac_key_p_0
4768 case 0x21: // pac_key_p_1
4769 case 0x22: // pac_key_p_2
4770 case 0x23: // pac_key_p_3
4771 case 0x24: // pac_key_u_0
4772 case 0x25: // pac_key_u_1
4773 case 0x26: // pac_key_u_2
4774 case 0x27: // pac_key_u_3
4775 case 0xa0: // pac_key_p_0_ns
4776 case 0xa1: // pac_key_p_1_ns
4777 case 0xa2: // pac_key_p_2_ns
4778 case 0xa3: // pac_key_p_3_ns
4779 case 0xa4: // pac_key_u_0_ns
4780 case 0xa5: // pac_key_u_1_ns
4781 case 0xa6: // pac_key_u_2_ns
4782 case 0xa7: // pac_key_u_3_ns
4783 if (!(FeatureBits[ARM::FeaturePACBTI]))
4784 return MCDisassembler::Fail;
4785 break;
4786 default:
4787 // Architecturally defined as unpredictable
4788 S = MCDisassembler::SoftFail;
4789 break;
4790 }
4791
4792 if (Inst.getOpcode() == ARM::t2MSR_M) {
4793 unsigned Mask = fieldFromInstruction(Val, 10, 2);
4794 if (!(FeatureBits[ARM::HasV7Ops])) {
4795 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
4796 // unpredictable.
4797 if (Mask != 2)
4798 S = MCDisassembler::SoftFail;
4799 }
4800 else {
4801 // The ARMv7-M architecture stores an additional 2-bit mask value in
4802 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
4803 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
4804 // the NZCVQ bits should be moved by the instruction. Bit mask{0}
4805 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set
4806 // only if the processor includes the DSP extension.
4807 if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
4808 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))
4809 S = MCDisassembler::SoftFail;
4810 }
4811 }
4812 } else {
4813 // A/R class
4814 if (Val == 0)
4815 return MCDisassembler::Fail;
4816 }
4817 Inst.addOperand(MCOperand::createImm(Val));
4818 return S;
4819}
4820
4821static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
4822 uint64_t Address,
4823 const MCDisassembler *Decoder) {
4824 unsigned R = fieldFromInstruction(Val, 5, 1);
4825 unsigned SysM = fieldFromInstruction(Val, 0, 5);
4826
4827 // The table of encodings for these banked registers comes from B9.2.3 of the
4828 // ARM ARM. There are patterns, but nothing regular enough to make this logic
4829 // neater. So by fiat, these values are UNPREDICTABLE:
4830 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM))
4831 return MCDisassembler::Fail;
4832
4833 Inst.addOperand(MCOperand::createImm(Val));
4834 return MCDisassembler::Success;
4835}
4836
4837static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
4838 uint64_t Address,
4839 const MCDisassembler *Decoder) {
4840 DecodeStatus S = MCDisassembler::Success;
4841
4842 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4843 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4844 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4845
4846 if (Rn == 0xF)
4847 S = MCDisassembler::SoftFail;
4848
4849 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4850 return MCDisassembler::Fail;
4851 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4852 return MCDisassembler::Fail;
4853 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4854 return MCDisassembler::Fail;
4855
4856 return S;
4857}
4858
4859static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
4860 uint64_t Address,
4861 const MCDisassembler *Decoder) {
4862 DecodeStatus S = MCDisassembler::Success;
4863
4864 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4865 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
4866 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4867 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4868
4869 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
4870 return MCDisassembler::Fail;
4871
4872 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
4873 S = MCDisassembler::SoftFail;
4874
4875 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4876 return MCDisassembler::Fail;
4877 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4878 return MCDisassembler::Fail;
4879 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4880 return MCDisassembler::Fail;
4881
4882 return S;
4883}
4884
4885static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
4886 uint64_t Address,
4887 const MCDisassembler *Decoder) {
4888 DecodeStatus S = MCDisassembler::Success;
4889
4890 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4891 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4892 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4893 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4894 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4895 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4896
4897 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4898
4899 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4900 return MCDisassembler::Fail;
4901 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4902 return MCDisassembler::Fail;
4903 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4904 return MCDisassembler::Fail;
4905 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4906 return MCDisassembler::Fail;
4907
4908 return S;
4909}
4910
4911static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
4912 uint64_t Address,
4913 const MCDisassembler *Decoder) {
4914 DecodeStatus S = MCDisassembler::Success;
4915
4916 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4917 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4918 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4919 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4920 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4921 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4922 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4923
4924 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4925 if (Rm == 0xF) S = MCDisassembler::SoftFail;
4926
4927 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4928 return MCDisassembler::Fail;
4929 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4930 return MCDisassembler::Fail;
4931 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4932 return MCDisassembler::Fail;
4933 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4934 return MCDisassembler::Fail;
4935
4936 return S;
4937}
4938
4939static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
4940 uint64_t Address,
4941 const MCDisassembler *Decoder) {
4942 DecodeStatus S = MCDisassembler::Success;
4943
4944 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4945 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4946 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4947 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4948 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4949 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4950
4951 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4952
4953 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4954 return MCDisassembler::Fail;
4955 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4956 return MCDisassembler::Fail;
4957 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4958 return MCDisassembler::Fail;
4959 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4960 return MCDisassembler::Fail;
4961
4962 return S;
4963}
4964
4965static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
4966 uint64_t Address,
4967 const MCDisassembler *Decoder) {
4968 DecodeStatus S = MCDisassembler::Success;
4969
4970 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4971 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4972 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4973 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4974 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4975 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4976
4977 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4978
4979 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4980 return MCDisassembler::Fail;
4981 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4982 return MCDisassembler::Fail;
4983 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4984 return MCDisassembler::Fail;
4985 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4986 return MCDisassembler::Fail;
4987
4988 return S;
4989}
4990
4991static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address,
4992 const MCDisassembler *Decoder) {
4993 DecodeStatus S = MCDisassembler::Success;
4994
4995 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4996 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4997 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4998 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4999 unsigned size = fieldFromInstruction(Insn, 10, 2);
5000
5001 unsigned align = 0;
5002 unsigned index = 0;
5003 switch (size) {
5004 default:
5005 return MCDisassembler::Fail;
5006 case 0:
5007 if (fieldFromInstruction(Insn, 4, 1))
5008 return MCDisassembler::Fail; // UNDEFINED
5009 index = fieldFromInstruction(Insn, 5, 3);
5010 break;
5011 case 1:
5012 if (fieldFromInstruction(Insn, 5, 1))
5013 return MCDisassembler::Fail; // UNDEFINED
5014 index = fieldFromInstruction(Insn, 6, 2);
5015 if (fieldFromInstruction(Insn, 4, 1))
5016 align = 2;
5017 break;
5018 case 2:
5019 if (fieldFromInstruction(Insn, 6, 1))
5020 return MCDisassembler::Fail; // UNDEFINED
5021 index = fieldFromInstruction(Insn, 7, 1);
5022
5023 switch (fieldFromInstruction(Insn, 4, 2)) {
5024 case 0 :
5025 align = 0; break;
5026 case 3:
5027 align = 4; break;
5028 default:
5029 return MCDisassembler::Fail;
5030 }
5031 break;
5032 }
5033
5034 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5035 return MCDisassembler::Fail;
5036 if (Rm != 0xF) { // Writeback
5037 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5038 return MCDisassembler::Fail;
5039 }
5040 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5041 return MCDisassembler::Fail;
5042 Inst.addOperand(MCOperand::createImm(align));
5043 if (Rm != 0xF) {
5044 if (Rm != 0xD) {
5045 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5046 return MCDisassembler::Fail;
5047 } else
5048 Inst.addOperand(MCOperand::createReg(0));
5049 }
5050
5051 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5052 return MCDisassembler::Fail;
5053 Inst.addOperand(MCOperand::createImm(index));
5054
5055 return S;
5056}
5057
5058static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address,
5059 const MCDisassembler *Decoder) {
5060 DecodeStatus S = MCDisassembler::Success;
5061
5062 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5063 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5064 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
5065 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
5066 unsigned size = fieldFromInstruction(Insn, 10, 2);
5067
5068 unsigned align = 0;
5069 unsigned index = 0;
5070 switch (size) {
5071 default:
5072 return MCDisassembler::Fail;
5073 case 0:
5074 if (fieldFromInstruction(Insn, 4, 1))
5075 return MCDisassembler::Fail; // UNDEFINED
5076 index = fieldFromInstruction(Insn, 5, 3);
5077 break;
5078 case 1:
5079 if (fieldFromInstruction(Insn, 5, 1))
5080 return MCDisassembler::Fail; // UNDEFINED
5081 index = fieldFromInstruction(Insn, 6, 2);
5082 if (fieldFromInstruction(Insn, 4, 1))
5083 align = 2;
5084 break;
5085 case 2:
5086 if (fieldFromInstruction(Insn, 6, 1))
5087 return MCDisassembler::Fail; // UNDEFINED
5088 index = fieldFromInstruction(Insn, 7, 1);
5089
5090 switch (fieldFromInstruction(Insn, 4, 2)) {
5091 case 0:
5092 align = 0; break;
5093 case 3:
5094 align = 4; break;
5095 default:
5096 return MCDisassembler::Fail;
5097 }
5098 break;
5099 }
5100
5101 if (Rm != 0xF) { // Writeback
5102 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5103 return MCDisassembler::Fail;
5104 }
5105 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5106 return MCDisassembler::Fail;
5107 Inst.addOperand(MCOperand::createImm(align));
5108 if (Rm != 0xF) {
5109 if (Rm != 0xD) {
5110 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5111 return MCDisassembler::Fail;
5112 } else
5113 Inst.addOperand(MCOperand::createReg(0));
5114 }
5115
5116 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5117 return MCDisassembler::Fail;
5118 Inst.addOperand(MCOperand::createImm(index));
5119
5120 return S;
5121}
5122
5123static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address,
5124 const MCDisassembler *Decoder) {
5125 DecodeStatus S = MCDisassembler::Success;
5126
5127 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5128 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5129 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
5130 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
5131 unsigned size = fieldFromInstruction(Insn, 10, 2);
5132
5133 unsigned align = 0;
5134 unsigned index = 0;
5135 unsigned inc = 1;
5136 switch (size) {
5137 default:
5138 return MCDisassembler::Fail;
5139 case 0:
5140 index = fieldFromInstruction(Insn, 5, 3);
5141 if (fieldFromInstruction(Insn, 4, 1))
5142 align = 2;
5143 break;
5144 case 1:
5145 index = fieldFromInstruction(Insn, 6, 2);
5146 if (fieldFromInstruction(Insn, 4, 1))
5147 align = 4;
5148 if (fieldFromInstruction(Insn, 5, 1))
5149 inc = 2;
5150 break;
5151 case 2:
5152 if (fieldFromInstruction(Insn, 5, 1))
5153 return MCDisassembler::Fail; // UNDEFINED
5154 index = fieldFromInstruction(Insn, 7, 1);
5155 if (fieldFromInstruction(Insn, 4, 1) != 0)
5156 align = 8;
5157 if (fieldFromInstruction(Insn, 6, 1))
5158 inc = 2;
5159 break;
5160 }
5161
5162 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5163 return MCDisassembler::Fail;
5164 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5165 return MCDisassembler::Fail;
5166 if (Rm != 0xF) { // Writeback
5167 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5168 return MCDisassembler::Fail;
5169 }
5170 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5171 return MCDisassembler::Fail;
5172 Inst.addOperand(MCOperand::createImm(align));
5173 if (Rm != 0xF) {
5174 if (Rm != 0xD) {
5175 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5176 return MCDisassembler::Fail;
5177 } else
5178 Inst.addOperand(MCOperand::createReg(0));
5179 }
5180
5181 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5182 return MCDisassembler::Fail;
5183 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5184 return MCDisassembler::Fail;
5185 Inst.addOperand(MCOperand::createImm(index));
5186
5187 return S;
5188}
5189
5190static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address,
5191 const MCDisassembler *Decoder) {
5192 DecodeStatus S = MCDisassembler::Success;
5193
5194 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5195 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5196 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
5197 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
5198 unsigned size = fieldFromInstruction(Insn, 10, 2);
5199
5200 unsigned align = 0;
5201 unsigned index = 0;
5202 unsigned inc = 1;
5203 switch (size) {
5204 default:
5205 return MCDisassembler::Fail;
5206 case 0:
5207 index = fieldFromInstruction(Insn, 5, 3);
5208 if (fieldFromInstruction(Insn, 4, 1))
5209 align = 2;
5210 break;
5211 case 1:
5212 index = fieldFromInstruction(Insn, 6, 2);
5213 if (fieldFromInstruction(Insn, 4, 1))
5214 align = 4;
5215 if (fieldFromInstruction(Insn, 5, 1))
5216 inc = 2;
5217 break;
5218 case 2:
5219 if (fieldFromInstruction(Insn, 5, 1))
5220 return MCDisassembler::Fail; // UNDEFINED
5221 index = fieldFromInstruction(Insn, 7, 1);
5222 if (fieldFromInstruction(Insn, 4, 1) != 0)
5223 align = 8;
5224 if (fieldFromInstruction(Insn, 6, 1))
5225 inc = 2;
5226 break;
5227 }
5228
5229 if (Rm != 0xF) { // Writeback
5230 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5231 return MCDisassembler::Fail;
5232 }
5233 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5234 return MCDisassembler::Fail;
5235 Inst.addOperand(MCOperand::createImm(align));
5236 if (Rm != 0xF) {
5237 if (Rm != 0xD) {
5238 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5239 return MCDisassembler::Fail;
5240 } else
5241 Inst.addOperand(MCOperand::createReg(0));
5242 }
5243
5244 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5245 return MCDisassembler::Fail;
5246 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5247 return MCDisassembler::Fail;
5248 Inst.addOperand(MCOperand::createImm(index));
5249
5250 return S;
5251}
5252
5253static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address,
5254 const MCDisassembler *Decoder) {
5255 DecodeStatus S = MCDisassembler::Success;
5256
5257 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5258 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5259 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
5260 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
5261 unsigned size = fieldFromInstruction(Insn, 10, 2);
5262
5263 unsigned align = 0;
5264 unsigned index = 0;
5265 unsigned inc = 1;
5266 switch (size) {
5267 default:
5268 return MCDisassembler::Fail;
5269 case 0:
5270 if (fieldFromInstruction(Insn, 4, 1))
5271 return MCDisassembler::Fail; // UNDEFINED
5272 index = fieldFromInstruction(Insn, 5, 3);
5273 break;
5274 case 1:
5275 if (fieldFromInstruction(Insn, 4, 1))
5276 return MCDisassembler::Fail; // UNDEFINED
5277 index = fieldFromInstruction(Insn, 6, 2);
5278 if (fieldFromInstruction(Insn, 5, 1))
5279 inc = 2;
5280 break;
5281 case 2:
5282 if (fieldFromInstruction(Insn, 4, 2))
5283 return MCDisassembler::Fail; // UNDEFINED
5284 index = fieldFromInstruction(Insn, 7, 1);
5285 if (fieldFromInstruction(Insn, 6, 1))
5286 inc = 2;
5287 break;
5288 }
5289
5290 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5291 return MCDisassembler::Fail;
5292 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5293 return MCDisassembler::Fail;
5294 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
5295 return MCDisassembler::Fail;
5296
5297 if (Rm != 0xF) { // Writeback
5298 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5299 return MCDisassembler::Fail;
5300 }
5301 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5302 return MCDisassembler::Fail;
5303 Inst.addOperand(MCOperand::createImm(align));
5304 if (Rm != 0xF) {
5305 if (Rm != 0xD) {
5306 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5307 return MCDisassembler::Fail;
5308 } else
5309 Inst.addOperand(MCOperand::createReg(0));
5310 }
5311
5312 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5313 return MCDisassembler::Fail;
5314 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5315 return MCDisassembler::Fail;
5316 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
5317 return MCDisassembler::Fail;
5318 Inst.addOperand(MCOperand::createImm(index));
5319
5320 return S;
5321}
5322
5323static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address,
5324 const MCDisassembler *Decoder) {
5325 DecodeStatus S = MCDisassembler::Success;
5326
5327 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5328 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5329 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
5330 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
5331 unsigned size = fieldFromInstruction(Insn, 10, 2);
5332
5333 unsigned align = 0;
5334 unsigned index = 0;
5335 unsigned inc = 1;
5336 switch (size) {
5337 default:
5338 return MCDisassembler::Fail;
5339 case 0:
5340 if (fieldFromInstruction(Insn, 4, 1))
5341 return MCDisassembler::Fail; // UNDEFINED
5342 index = fieldFromInstruction(Insn, 5, 3);
5343 break;
5344 case 1:
5345 if (fieldFromInstruction(Insn, 4, 1))
5346 return MCDisassembler::Fail; // UNDEFINED
5347 index = fieldFromInstruction(Insn, 6, 2);
5348 if (fieldFromInstruction(Insn, 5, 1))
5349 inc = 2;
5350 break;
5351 case 2:
5352 if (fieldFromInstruction(Insn, 4, 2))
5353 return MCDisassembler::Fail; // UNDEFINED
5354 index = fieldFromInstruction(Insn, 7, 1);
5355 if (fieldFromInstruction(Insn, 6, 1))
5356 inc = 2;
5357 break;
5358 }
5359
5360 if (Rm != 0xF) { // Writeback
5361 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5362 return MCDisassembler::Fail;
5363 }
5364 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5365 return MCDisassembler::Fail;
5366 Inst.addOperand(MCOperand::createImm(align));
5367 if (Rm != 0xF) {
5368 if (Rm != 0xD) {
5369 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5370 return MCDisassembler::Fail;
5371 } else
5372 Inst.addOperand(MCOperand::createReg(0));
5373 }
5374
5375 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5376 return MCDisassembler::Fail;
5377 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5378 return MCDisassembler::Fail;
5379 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
5380 return MCDisassembler::Fail;
5381 Inst.addOperand(MCOperand::createImm(index));
5382
5383 return S;
5384}
5385
5386static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address,
5387 const MCDisassembler *Decoder) {
5388 DecodeStatus S = MCDisassembler::Success;
5389
5390 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5391 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5392 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
5393 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
5394 unsigned size = fieldFromInstruction(Insn, 10, 2);
5395
5396 unsigned align = 0;
5397 unsigned index = 0;
5398 unsigned inc = 1;
5399 switch (size) {
5400 default:
5401 return MCDisassembler::Fail;
5402 case 0:
5403 if (fieldFromInstruction(Insn, 4, 1))
5404 align = 4;
5405 index = fieldFromInstruction(Insn, 5, 3);
5406 break;
5407 case 1:
5408 if (fieldFromInstruction(Insn, 4, 1))
5409 align = 8;
5410 index = fieldFromInstruction(Insn, 6, 2);
5411 if (fieldFromInstruction(Insn, 5, 1))
5412 inc = 2;
5413 break;
5414 case 2:
5415 switch (fieldFromInstruction(Insn, 4, 2)) {
5416 case 0:
5417 align = 0; break;
5418 case 3:
5419 return MCDisassembler::Fail;
5420 default:
5421 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
5422 }
5423
5424 index = fieldFromInstruction(Insn, 7, 1);
5425 if (fieldFromInstruction(Insn, 6, 1))
5426 inc = 2;
5427 break;
5428 }
5429
5430 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5431 return MCDisassembler::Fail;
5432 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5433 return MCDisassembler::Fail;
5434 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
5435 return MCDisassembler::Fail;
5436 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
5437 return MCDisassembler::Fail;
5438
5439 if (Rm != 0xF) { // Writeback
5440 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5441 return MCDisassembler::Fail;
5442 }
5443 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5444 return MCDisassembler::Fail;
5445 Inst.addOperand(MCOperand::createImm(align));
5446 if (Rm != 0xF) {
5447 if (Rm != 0xD) {
5448 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5449 return MCDisassembler::Fail;
5450 } else
5451 Inst.addOperand(MCOperand::createReg(0));
5452 }
5453
5454 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5455 return MCDisassembler::Fail;
5456 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5457 return MCDisassembler::Fail;
5458 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
5459 return MCDisassembler::Fail;
5460 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
5461 return MCDisassembler::Fail;
5462 Inst.addOperand(MCOperand::createImm(index));
5463
5464 return S;
5465}
5466
5467static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address,
5468 const MCDisassembler *Decoder) {
5469 DecodeStatus S = MCDisassembler::Success;
5470
5471 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5472 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5473 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
5474 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
5475 unsigned size = fieldFromInstruction(Insn, 10, 2);
5476
5477 unsigned align = 0;
5478 unsigned index = 0;
5479 unsigned inc = 1;
5480 switch (size) {
5481 default:
5482 return MCDisassembler::Fail;
5483 case 0:
5484 if (fieldFromInstruction(Insn, 4, 1))
5485 align = 4;
5486 index = fieldFromInstruction(Insn, 5, 3);
5487 break;
5488 case 1:
5489 if (fieldFromInstruction(Insn, 4, 1))
5490 align = 8;
5491 index = fieldFromInstruction(Insn, 6, 2);
5492 if (fieldFromInstruction(Insn, 5, 1))
5493 inc = 2;
5494 break;
5495 case 2:
5496 switch (fieldFromInstruction(Insn, 4, 2)) {
5497 case 0:
5498 align = 0; break;
5499 case 3:
5500 return MCDisassembler::Fail;
5501 default:
5502 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
5503 }
5504
5505 index = fieldFromInstruction(Insn, 7, 1);
5506 if (fieldFromInstruction(Insn, 6, 1))
5507 inc = 2;
5508 break;
5509 }
5510
5511 if (Rm != 0xF) { // Writeback
5512 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5513 return MCDisassembler::Fail;
5514 }
5515 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5516 return MCDisassembler::Fail;
5517 Inst.addOperand(MCOperand::createImm(align));
5518 if (Rm != 0xF) {
5519 if (Rm != 0xD) {
5520 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5521 return MCDisassembler::Fail;
5522 } else
5523 Inst.addOperand(MCOperand::createReg(0));
5524 }
5525
5526 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5527 return MCDisassembler::Fail;
5528 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5529 return MCDisassembler::Fail;
5530 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
5531 return MCDisassembler::Fail;
5532 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
5533 return MCDisassembler::Fail;
5534 Inst.addOperand(MCOperand::createImm(index));
5535
5536 return S;
5537}
5538
5539static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address,
5540 const MCDisassembler *Decoder) {
5541 DecodeStatus S = MCDisassembler::Success;
5542 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5543 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
5544 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
5545 unsigned pred = fieldFromInstruction(Insn, 28, 4);
5546 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
5547
5548 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
5549 S = MCDisassembler::SoftFail;
5550
5551 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
5552 return MCDisassembler::Fail;
5553 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
5554 return MCDisassembler::Fail;
5555 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
5556 return MCDisassembler::Fail;
5557 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
5558 return MCDisassembler::Fail;
5559 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5560 return MCDisassembler::Fail;
5561
5562 return S;
5563}
5564
5565static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address,
5566 const MCDisassembler *Decoder) {
5567 DecodeStatus S = MCDisassembler::Success;
5568 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5569 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
5570 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
5571 unsigned pred = fieldFromInstruction(Insn, 28, 4);
5572 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
5573
5574 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
5575 S = MCDisassembler::SoftFail;
5576
5577 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
5578 return MCDisassembler::Fail;
5579 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
5580 return MCDisassembler::Fail;
5581 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
5582 return MCDisassembler::Fail;
5583 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
5584 return MCDisassembler::Fail;
5585 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5586 return MCDisassembler::Fail;
5587
5588 return S;
5589}
5590
5591static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, uint64_t Address,
5592 const MCDisassembler *Decoder) {
5593 DecodeStatus S = MCDisassembler::Success;
5594 unsigned pred = fieldFromInstruction(Insn, 4, 4);
5595 unsigned mask = fieldFromInstruction(Insn, 0, 4);
5596
5597 if (pred == 0xF) {
5598 pred = 0xE;
5599 S = MCDisassembler::SoftFail;
5600 }
5601
5602 if (mask == 0x0)
5603 return MCDisassembler::Fail;
5604
5605 // IT masks are encoded as a sequence of replacement low-order bits
5606 // for the condition code. So if the low bit of the starting
5607 // condition code is 1, then we have to flip all the bits above the
5608 // terminating bit (which is the lowest 1 bit).
5609 if (pred & 1) {
5610 unsigned LowBit = mask & -mask;
5611 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1);
5612 mask ^= BitsAboveLowBit;
5613 }
5614
5615 Inst.addOperand(MCOperand::createImm(pred));
5616 Inst.addOperand(MCOperand::createImm(mask));
5617 return S;
5618}
5619
5620static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
5621 uint64_t Address,
5622 const MCDisassembler *Decoder) {
5623 DecodeStatus S = MCDisassembler::Success;
5624
5625 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5626 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
5627 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5628 unsigned addr = fieldFromInstruction(Insn, 0, 8);
5629 unsigned W = fieldFromInstruction(Insn, 21, 1);
5630 unsigned U = fieldFromInstruction(Insn, 23, 1);
5631 unsigned P = fieldFromInstruction(Insn, 24, 1);
5632 bool writeback = (W == 1) | (P == 0);
5633
5634 addr |= (U << 8) | (Rn << 9);
5635
5636 if (writeback && (Rn == Rt || Rn == Rt2))
5637 Check(S, MCDisassembler::SoftFail);
5638 if (Rt == Rt2)
5639 Check(S, MCDisassembler::SoftFail);
5640
5641 // Rt
5642 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
5643 return MCDisassembler::Fail;
5644 // Rt2
5645 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
5646 return MCDisassembler::Fail;
5647 // Writeback operand
5648 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
5649 return MCDisassembler::Fail;
5650 // addr
5651 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
5652 return MCDisassembler::Fail;
5653
5654 return S;
5655}
5656
5657static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
5658 uint64_t Address,
5659 const MCDisassembler *Decoder) {
5660 DecodeStatus S = MCDisassembler::Success;
5661
5662 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5663 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
5664 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5665 unsigned addr = fieldFromInstruction(Insn, 0, 8);
5666 unsigned W = fieldFromInstruction(Insn, 21, 1);
5667 unsigned U = fieldFromInstruction(Insn, 23, 1);
5668 unsigned P = fieldFromInstruction(Insn, 24, 1);
5669 bool writeback = (W == 1) | (P == 0);
5670
5671 addr |= (U << 8) | (Rn << 9);
5672
5673 if (writeback && (Rn == Rt || Rn == Rt2))
5674 Check(S, MCDisassembler::SoftFail);
5675
5676 // Writeback operand
5677 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
5678 return MCDisassembler::Fail;
5679 // Rt
5680 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
5681 return MCDisassembler::Fail;
5682 // Rt2
5683 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
5684 return MCDisassembler::Fail;
5685 // addr
5686 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
5687 return MCDisassembler::Fail;
5688
5689 return S;
5690}
5691
5692static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, uint64_t Address,
5693 const MCDisassembler *Decoder) {
5694 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
5695 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
5696 if (sign1 != sign2) return MCDisassembler::Fail;
5697 const unsigned Rd = fieldFromInstruction(Insn, 8, 4);
5698 assert(Inst.getNumOperands() == 0 && "We should receive an empty Inst");
5699 DecodeStatus S = DecoderGPRRegisterClass(Inst, Rd, Address, Decoder);
5700
5701 unsigned Val = fieldFromInstruction(Insn, 0, 8);
5702 Val |= fieldFromInstruction(Insn, 12, 3) << 8;
5703 Val |= fieldFromInstruction(Insn, 26, 1) << 11;
5704 // If sign, then it is decreasing the address.
5705 if (sign1) {
5706 // Following ARMv7 Architecture Manual, when the offset
5707 // is zero, it is decoded as a subw, not as a adr.w
5708 if (!Val) {
5709 Inst.setOpcode(ARM::t2SUBri12);
5710 Inst.addOperand(MCOperand::createReg(ARM::PC));
5711 } else
5712 Val = -Val;
5713 }
5714 Inst.addOperand(MCOperand::createImm(Val));
5715 return S;
5716}
5717
5718static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
5719 uint64_t Address,
5720 const MCDisassembler *Decoder) {
5721 DecodeStatus S = MCDisassembler::Success;
5722
5723 // Shift of "asr #32" is not allowed in Thumb2 mode.
5724 if (Val == 0x20) S = MCDisassembler::Fail;
5725 Inst.addOperand(MCOperand::createImm(Val));
5726 return S;
5727}
5728
5729static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address,
5730 const MCDisassembler *Decoder) {
5731 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5732 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
5733 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5734 unsigned pred = fieldFromInstruction(Insn, 28, 4);
5735
5736 if (pred == 0xF)
5737 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
5738
5739 DecodeStatus S = MCDisassembler::Success;
5740
5741 if (Rt == Rn || Rn == Rt2)
5742 S = MCDisassembler::SoftFail;
5743
5744 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5745 return MCDisassembler::Fail;
5746 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5747 return MCDisassembler::Fail;
5748 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5749 return MCDisassembler::Fail;
5750 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5751 return MCDisassembler::Fail;
5752
5753 return S;
5754}
5755
5756static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address,
5757 const MCDisassembler *Decoder) {
5758 const FeatureBitset &featureBits =
5759 Decoder->getSubtargetInfo().getFeatureBits();
5760 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5761
5762 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5763 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5764 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5765 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5766 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5767 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5768 unsigned op = fieldFromInstruction(Insn, 5, 1);
5769
5770 DecodeStatus S = MCDisassembler::Success;
5771
5772 // If the top 3 bits of imm are clear, this is a VMOV (immediate)
5773 if (!(imm & 0x38)) {
5774 if (cmode == 0xF) {
5775 if (op == 1) return MCDisassembler::Fail;
5776 Inst.setOpcode(ARM::VMOVv2f32);
5777 }
5778 if (hasFullFP16) {
5779 if (cmode == 0xE) {
5780 if (op == 1) {
5781 Inst.setOpcode(ARM::VMOVv1i64);
5782 } else {
5783 Inst.setOpcode(ARM::VMOVv8i8);
5784 }
5785 }
5786 if (cmode == 0xD) {
5787 if (op == 1) {
5788 Inst.setOpcode(ARM::VMVNv2i32);
5789 } else {
5790 Inst.setOpcode(ARM::VMOVv2i32);
5791 }
5792 }
5793 if (cmode == 0xC) {
5794 if (op == 1) {
5795 Inst.setOpcode(ARM::VMVNv2i32);
5796 } else {
5797 Inst.setOpcode(ARM::VMOVv2i32);
5798 }
5799 }
5800 }
5801 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder);
5802 }
5803
5804 if (!(imm & 0x20)) return MCDisassembler::Fail;
5805
5806 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
5807 return MCDisassembler::Fail;
5808 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
5809 return MCDisassembler::Fail;
5810 Inst.addOperand(MCOperand::createImm(64 - imm));
5811
5812 return S;
5813}
5814
5815static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address,
5816 const MCDisassembler *Decoder) {
5817 const FeatureBitset &featureBits =
5818 Decoder->getSubtargetInfo().getFeatureBits();
5819 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5820
5821 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5822 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5823 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5824 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5825 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5826 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5827 unsigned op = fieldFromInstruction(Insn, 5, 1);
5828
5829 DecodeStatus S = MCDisassembler::Success;
5830
5831 // If the top 3 bits of imm are clear, this is a VMOV (immediate)
5832 if (!(imm & 0x38)) {
5833 if (cmode == 0xF) {
5834 if (op == 1) return MCDisassembler::Fail;
5835 Inst.setOpcode(ARM::VMOVv4f32);
5836 }
5837 if (hasFullFP16) {
5838 if (cmode == 0xE) {
5839 if (op == 1) {
5840 Inst.setOpcode(ARM::VMOVv2i64);
5841 } else {
5842 Inst.setOpcode(ARM::VMOVv16i8);
5843 }
5844 }
5845 if (cmode == 0xD) {
5846 if (op == 1) {
5847 Inst.setOpcode(ARM::VMVNv4i32);
5848 } else {
5849 Inst.setOpcode(ARM::VMOVv4i32);
5850 }
5851 }
5852 if (cmode == 0xC) {
5853 if (op == 1) {
5854 Inst.setOpcode(ARM::VMVNv4i32);
5855 } else {
5856 Inst.setOpcode(ARM::VMOVv4i32);
5857 }
5858 }
5859 }
5860 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder);
5861 }
5862
5863 if (!(imm & 0x20)) return MCDisassembler::Fail;
5864
5865 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
5866 return MCDisassembler::Fail;
5867 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
5868 return MCDisassembler::Fail;
5869 Inst.addOperand(MCOperand::createImm(64 - imm));
5870
5871 return S;
5872}
5873
5874static DecodeStatus
5875DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Insn,
5876 uint64_t Address,
5877 const MCDisassembler *Decoder) {
5878 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5879 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5880 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0);
5881 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4);
5882 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5883 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5884 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0);
5885 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0);
5886
5887 DecodeStatus S = MCDisassembler::Success;
5888
5889 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass;
5890
5891 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
5892 return MCDisassembler::Fail;
5893 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
5894 return MCDisassembler::Fail;
5895 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder)))
5896 return MCDisassembler::Fail;
5897 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
5898 return MCDisassembler::Fail;
5899 // The lane index does not have any bits in the encoding, because it can only
5900 // be 0.
5901 Inst.addOperand(MCOperand::createImm(0));
5902 Inst.addOperand(MCOperand::createImm(rotate));
5903
5904 return S;
5905}
5906
5907static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address,
5908 const MCDisassembler *Decoder) {
5909 DecodeStatus S = MCDisassembler::Success;
5910
5911 unsigned Rn = fieldFromInstruction(Val, 16, 4);
5912 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5913 unsigned Rm = fieldFromInstruction(Val, 0, 4);
5914 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
5915 unsigned Cond = fieldFromInstruction(Val, 28, 4);
5916
5917 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
5918 S = MCDisassembler::SoftFail;
5919
5920 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5921 return MCDisassembler::Fail;
5922 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5923 return MCDisassembler::Fail;
5924 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
5925 return MCDisassembler::Fail;
5926 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
5927 return MCDisassembler::Fail;
5928 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
5929 return MCDisassembler::Fail;
5930
5931 return S;
5932}
5933
5934static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
5935 uint64_t Address,
5936 const MCDisassembler *Decoder) {
5937 DecodeStatus S = MCDisassembler::Success;
5938
5939 unsigned CRm = fieldFromInstruction(Val, 0, 4);
5940 unsigned opc1 = fieldFromInstruction(Val, 4, 4);
5941 unsigned cop = fieldFromInstruction(Val, 8, 4);
5942 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5943 unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
5944
5945 if ((cop & ~0x1) == 0xa)
5946 return MCDisassembler::Fail;
5947
5948 if (Rt == Rt2)
5949 S = MCDisassembler::SoftFail;
5950
5951 // We have to check if the instruction is MRRC2
5952 // or MCRR2 when constructing the operands for
5953 // Inst. Reason is because MRRC2 stores to two
5954 // registers so it's tablegen desc has two
5955 // outputs whereas MCRR doesn't store to any
5956 // registers so all of it's operands are listed
5957 // as inputs, therefore the operand order for
5958 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm]
5959 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm]
5960
5961 if (Inst.getOpcode() == ARM::MRRC2) {
5962 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5963 return MCDisassembler::Fail;
5964 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5965 return MCDisassembler::Fail;
5966 }
5967 Inst.addOperand(MCOperand::createImm(cop));
5968 Inst.addOperand(MCOperand::createImm(opc1));
5969 if (Inst.getOpcode() == ARM::MCRR2) {
5970 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5971 return MCDisassembler::Fail;
5972 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5973 return MCDisassembler::Fail;
5974 }
5975 Inst.addOperand(MCOperand::createImm(CRm));
5976
5977 return S;
5978}
5979
5980static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
5981 uint64_t Address,
5982 const MCDisassembler *Decoder) {
5983 const FeatureBitset &featureBits =
5984 Decoder->getSubtargetInfo().getFeatureBits();
5985 DecodeStatus S = MCDisassembler::Success;
5986
5987 // Add explicit operand for the destination sysreg, for cases where
5988 // we have to model it for code generation purposes.
5989 switch (Inst.getOpcode()) {
5990 case ARM::VMSR_FPSCR_NZCVQC:
5991 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
5992 break;
5993 case ARM::VMSR_P0:
5994 Inst.addOperand(MCOperand::createReg(ARM::VPR));
5995 break;
5996 }
5997
5998 if (Inst.getOpcode() != ARM::FMSTAT) {
5999 unsigned Rt = fieldFromInstruction(Val, 12, 4);
6000
6001 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) {
6002 if (Rt == 13 || Rt == 15)
6003 S = MCDisassembler::SoftFail;
6004 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
6005 } else
6006 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder));
6007 }
6008
6009 // Add explicit operand for the source sysreg, similarly to above.
6010 switch (Inst.getOpcode()) {
6011 case ARM::VMRS_FPSCR_NZCVQC:
6012 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
6013 break;
6014 case ARM::VMRS_P0:
6015 Inst.addOperand(MCOperand::createReg(ARM::VPR));
6016 break;
6017 }
6018
6019 if (featureBits[ARM::ModeThumb]) {
6020 Inst.addOperand(MCOperand::createImm(ARMCC::AL));
6021 Inst.addOperand(MCOperand::createReg(0));
6022 } else {
6023 unsigned pred = fieldFromInstruction(Val, 28, 4);
6024 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
6025 return MCDisassembler::Fail;
6026 }
6027
6028 return S;
6029}
6030
6031template <bool isSigned, bool isNeg, bool zeroPermitted, int size>
6032static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val,
6033 uint64_t Address,
6034 const MCDisassembler *Decoder) {
6035 DecodeStatus S = MCDisassembler::Success;
6036 if (Val == 0 && !zeroPermitted)
6037 S = MCDisassembler::Fail;
6038
6039 uint64_t DecVal;
6040 if (isSigned)
6041 DecVal = SignExtend32<size + 1>(Val << 1);
6042 else
6043 DecVal = (Val << 1);
6044
6045 if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst,
6046 Decoder))
6047 Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal));
6048 return S;
6049}
6050
6051static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val,
6052 uint64_t Address,
6053 const MCDisassembler *Decoder) {
6054
6055 uint64_t LocImm = Inst.getOperand(0).getImm();
6056 Val = LocImm + (2 << Val);
6057 if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst,
6058 Decoder))
6059 Inst.addOperand(MCOperand::createImm(Val));
6060 return MCDisassembler::Success;
6061}
6062
6063static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val,
6064 uint64_t Address,
6065 const MCDisassembler *Decoder) {
6066 if (Val >= ARMCC::AL) // also exclude the non-condition NV
6067 return MCDisassembler::Fail;
6068 Inst.addOperand(MCOperand::createImm(Val));
6069 return MCDisassembler::Success;
6070}
6071
6072static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address,
6073 const MCDisassembler *Decoder) {
6074 DecodeStatus S = MCDisassembler::Success;
6075
6076 if (Inst.getOpcode() == ARM::MVE_LCTP)
6077 return S;
6078
6079 unsigned Imm = fieldFromInstruction(Insn, 11, 1) |
6080 fieldFromInstruction(Insn, 1, 10) << 1;
6081 switch (Inst.getOpcode()) {
6082 case ARM::t2LEUpdate:
6083 case ARM::MVE_LETP:
6084 Inst.addOperand(MCOperand::createReg(ARM::LR));
6085 Inst.addOperand(MCOperand::createReg(ARM::LR));
6086 [[fallthrough]];
6087 case ARM::t2LE:
6088 if (!Check(S, DecodeBFLabelOperand<false, true, true, 11>(
6089 Inst, Imm, Address, Decoder)))
6090 return MCDisassembler::Fail;
6091 break;
6092 case ARM::t2WLS:
6093 case ARM::MVE_WLSTP_8:
6094 case ARM::MVE_WLSTP_16:
6095 case ARM::MVE_WLSTP_32:
6096 case ARM::MVE_WLSTP_64:
6097 Inst.addOperand(MCOperand::createReg(ARM::LR));
6098 if (!Check(S,
6099 DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4),
6100 Address, Decoder)) ||
6101 !Check(S, DecodeBFLabelOperand<false, false, true, 11>(
6102 Inst, Imm, Address, Decoder)))
6103 return MCDisassembler::Fail;
6104 break;
6105 case ARM::t2DLS:
6106 case ARM::MVE_DLSTP_8:
6107 case ARM::MVE_DLSTP_16:
6108 case ARM::MVE_DLSTP_32:
6109 case ARM::MVE_DLSTP_64:
6110 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
6111 if (Rn == 0xF) {
6112 // Enforce all the rest of the instruction bits in LCTP, which
6113 // won't have been reliably checked based on LCTP's own tablegen
6114 // record, because we came to this decode by a roundabout route.
6115 uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE;
6116 if ((Insn & ~SBZMask) != CanonicalLCTP)
6117 return MCDisassembler::Fail; // a mandatory bit is wrong: hard fail
6118 if (Insn != CanonicalLCTP)
6119 Check(S, MCDisassembler::SoftFail); // an SBZ bit is wrong: soft fail
6120
6121 Inst.setOpcode(ARM::MVE_LCTP);
6122 } else {
6123 Inst.addOperand(MCOperand::createReg(ARM::LR));
6124 if (!Check(S, DecoderGPRRegisterClass(Inst,
6125 fieldFromInstruction(Insn, 16, 4),
6126 Address, Decoder)))
6127 return MCDisassembler::Fail;
6128 }
6129 break;
6130 }
6131 return S;
6132}
6133
6134static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val,
6135 uint64_t Address,
6136 const MCDisassembler *Decoder) {
6137 DecodeStatus S = MCDisassembler::Success;
6138
6139 if (Val == 0)
6140 Val = 32;
6141
6142 Inst.addOperand(MCOperand::createImm(Val));
6143
6144 return S;
6145}
6146
6147static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo,
6148 uint64_t Address,
6149 const MCDisassembler *Decoder) {
6150 if ((RegNo) + 1 > 11)
6151 return MCDisassembler::Fail;
6152
6153 unsigned Register = GPRDecoderTable[(RegNo) + 1];
6154 Inst.addOperand(MCOperand::createReg(Register));
6155 return MCDisassembler::Success;
6156}
6157
6158static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo,
6159 uint64_t Address,
6160 const MCDisassembler *Decoder) {
6161 if ((RegNo) > 14)
6162 return MCDisassembler::Fail;
6163
6164 unsigned Register = GPRDecoderTable[(RegNo)];
6165 Inst.addOperand(MCOperand::createReg(Register));
6166 return MCDisassembler::Success;
6167}
6168
6169static DecodeStatus
6170DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo,
6171 uint64_t Address,
6172 const MCDisassembler *Decoder) {
6173 if (RegNo == 15) {
6174 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
6175 return MCDisassembler::Success;
6176 }
6177
6178 unsigned Register = GPRDecoderTable[RegNo];
6179 Inst.addOperand(MCOperand::createReg(Register));
6180
6181 if (RegNo == 13)
6182 return MCDisassembler::SoftFail;
6183
6184 return MCDisassembler::Success;
6185}
6186
6187static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address,
6188 const MCDisassembler *Decoder) {
6189 DecodeStatus S = MCDisassembler::Success;
6190
6191 Inst.addOperand(MCOperand::createImm(ARMCC::AL));
6192 Inst.addOperand(MCOperand::createReg(0));
6193 unsigned regs = fieldFromInstruction(Insn, 0, 8);
6194 if (regs == 0) {
6195 // Register list contains only VPR
6196 } else if (Inst.getOpcode() == ARM::VSCCLRMD) {
6197 unsigned reglist = regs | (fieldFromInstruction(Insn, 12, 4) << 8) |
6198 (fieldFromInstruction(Insn, 22, 1) << 12);
6199 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) {
6200 return MCDisassembler::Fail;
6201 }
6202 } else {
6203 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 1) |
6204 fieldFromInstruction(Insn, 22, 1);
6205 // Registers past s31 are permitted and treated as being half of a d
6206 // register, though both halves of each d register must be present.
6207 unsigned max_reg = Vd + regs;
6208 if (max_reg > 64 || (max_reg > 32 && (max_reg & 1)))
6209 S = MCDisassembler::SoftFail;
6210 unsigned max_sreg = std::min(32u, max_reg);
6211 unsigned max_dreg = std::min(32u, max_reg / 2);
6212 for (unsigned i = Vd; i < max_sreg; ++i)
6213 if (!Check(S, DecodeSPRRegisterClass(Inst, i, Address, Decoder)))
6214 return MCDisassembler::Fail;
6215 for (unsigned i = 16; i < max_dreg; ++i)
6216 if (!Check(S, DecodeDPRRegisterClass(Inst, i, Address, Decoder)))
6217 return MCDisassembler::Fail;
6218 }
6219 Inst.addOperand(MCOperand::createReg(ARM::VPR));
6220
6221 return S;
6222}
6223
6224static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo,
6225 uint64_t Address,
6226 const MCDisassembler *Decoder) {
6227 if (RegNo > 7)
6228 return MCDisassembler::Fail;
6229
6230 unsigned Register = QPRDecoderTable[RegNo];
6231 Inst.addOperand(MCOperand::createReg(Register));
6232 return MCDisassembler::Success;
6233}
6234
6235static const MCPhysReg QQPRDecoderTable[] = {
6236 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4,
6237 ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7
6238};
6239
6240static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
6241 uint64_t Address,
6242 const MCDisassembler *Decoder) {
6243 if (RegNo > 6)
6244 return MCDisassembler::Fail;
6245
6246 unsigned Register = QQPRDecoderTable[RegNo];
6247 Inst.addOperand(MCOperand::createReg(Register));
6248 return MCDisassembler::Success;
6249}
6250
6251static const MCPhysReg QQQQPRDecoderTable[] = {
6252 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5,
6253 ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7
6254};
6255
6256static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
6257 uint64_t Address,
6258 const MCDisassembler *Decoder) {
6259 if (RegNo > 4)
6260 return MCDisassembler::Fail;
6261
6262 unsigned Register = QQQQPRDecoderTable[RegNo];
6263 Inst.addOperand(MCOperand::createReg(Register));
6264 return MCDisassembler::Success;
6265}
6266
6267static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val,
6268 uint64_t Address,
6269 const MCDisassembler *Decoder) {
6270 DecodeStatus S = MCDisassembler::Success;
6271
6272 // Parse VPT mask and encode it in the MCInst as an immediate with the same
6273 // format as the it_mask. That is, from the second 'e|t' encode 'e' as 1 and
6274 // 't' as 0 and finish with a 1.
6275 unsigned Imm = 0;
6276 // We always start with a 't'.
6277 unsigned CurBit = 0;
6278 for (int i = 3; i >= 0; --i) {
6279 // If the bit we are looking at is not the same as last one, invert the
6280 // CurBit, if it is the same leave it as is.
6281 CurBit ^= (Val >> i) & 1U;
6282
6283 // Encode the CurBit at the right place in the immediate.
6284 Imm |= (CurBit << i);
6285
6286 // If we are done, finish the encoding with a 1.
6287 if ((Val & ~(~0U << i)) == 0) {
6288 Imm |= 1U << i;
6289 break;
6290 }
6291 }
6292
6293 Inst.addOperand(MCOperand::createImm(Imm));
6294
6295 return S;
6296}
6297
6298static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo,
6299 uint64_t Address,
6300 const MCDisassembler *Decoder) {
6301 // The vpred_r operand type includes an MQPR register field derived
6302 // from the encoding. But we don't actually want to add an operand
6303 // to the MCInst at this stage, because AddThumbPredicate will do it
6304 // later, and will infer the register number from the TIED_TO
6305 // constraint. So this is a deliberately empty decoder method that
6306 // will inhibit the auto-generated disassembly code from adding an
6307 // operand at all.
6308 return MCDisassembler::Success;
6309}
6310
6311[[maybe_unused]] static DecodeStatus
6312DecodeVpredNOperand(MCInst &Inst, unsigned RegNo, uint64_t Address,
6313 const MCDisassembler *Decoder) {
6314 // Similar to above, we want to ensure that no operands are added for the
6315 // vpred operands. (This is marked "maybe_unused" for the moment; because
6316 // DecoderEmitter currently (wrongly) omits operands with no instruction bits,
6317 // the decoder doesn't actually call it yet. That will be addressed in a
6318 // future change.)
6319 return MCDisassembler::Success;
6320}
6321
6322static DecodeStatus
6323DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
6324 const MCDisassembler *Decoder) {
6325 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE));
6326 return MCDisassembler::Success;
6327}
6328
6329static DecodeStatus
6330DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
6331 const MCDisassembler *Decoder) {
6332 unsigned Code;
6333 switch (Val & 0x3) {
6334 case 0:
6335 Code = ARMCC::GE;
6336 break;
6337 case 1:
6338 Code = ARMCC::LT;
6339 break;
6340 case 2:
6341 Code = ARMCC::GT;
6342 break;
6343 case 3:
6344 Code = ARMCC::LE;
6345 break;
6346 }
6347 Inst.addOperand(MCOperand::createImm(Code));
6348 return MCDisassembler::Success;
6349}
6350
6351static DecodeStatus
6352DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
6353 const MCDisassembler *Decoder) {
6354 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI));
6355 return MCDisassembler::Success;
6356}
6357
6358static DecodeStatus
6359DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
6360 const MCDisassembler *Decoder) {
6361 unsigned Code;
6362 switch (Val) {
6363 default:
6364 return MCDisassembler::Fail;
6365 case 0:
6366 Code = ARMCC::EQ;
6367 break;
6368 case 1:
6369 Code = ARMCC::NE;
6370 break;
6371 case 4:
6372 Code = ARMCC::GE;
6373 break;
6374 case 5:
6375 Code = ARMCC::LT;
6376 break;
6377 case 6:
6378 Code = ARMCC::GT;
6379 break;
6380 case 7:
6381 Code = ARMCC::LE;
6382 break;
6383 }
6384
6385 Inst.addOperand(MCOperand::createImm(Code));
6386 return MCDisassembler::Success;
6387}
6388
6389static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val,
6390 uint64_t Address,
6391 const MCDisassembler *Decoder) {
6392 DecodeStatus S = MCDisassembler::Success;
6393
6394 unsigned DecodedVal = 64 - Val;
6395
6396 switch (Inst.getOpcode()) {
6397 case ARM::MVE_VCVTf16s16_fix:
6398 case ARM::MVE_VCVTs16f16_fix:
6399 case ARM::MVE_VCVTf16u16_fix:
6400 case ARM::MVE_VCVTu16f16_fix:
6401 if (DecodedVal > 16)
6402 return MCDisassembler::Fail;
6403 break;
6404 case ARM::MVE_VCVTf32s32_fix:
6405 case ARM::MVE_VCVTs32f32_fix:
6406 case ARM::MVE_VCVTf32u32_fix:
6407 case ARM::MVE_VCVTu32f32_fix:
6408 if (DecodedVal > 32)
6409 return MCDisassembler::Fail;
6410 break;
6411 }
6412
6413 Inst.addOperand(MCOperand::createImm(64 - Val));
6414
6415 return S;
6416}
6417
6418static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) {
6419 switch (Opcode) {
6420 case ARM::VSTR_P0_off:
6421 case ARM::VSTR_P0_pre:
6422 case ARM::VSTR_P0_post:
6423 case ARM::VLDR_P0_off:
6424 case ARM::VLDR_P0_pre:
6425 case ARM::VLDR_P0_post:
6426 return ARM::P0;
6427 case ARM::VSTR_FPSCR_NZCVQC_off:
6428 case ARM::VSTR_FPSCR_NZCVQC_pre:
6429 case ARM::VSTR_FPSCR_NZCVQC_post:
6430 case ARM::VLDR_FPSCR_NZCVQC_off:
6431 case ARM::VLDR_FPSCR_NZCVQC_pre:
6432 case ARM::VLDR_FPSCR_NZCVQC_post:
6433 return ARM::FPSCR;
6434 default:
6435 return 0;
6436 }
6437}
6438
6439template <bool Writeback>
6440static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val,
6441 uint64_t Address,
6442 const MCDisassembler *Decoder) {
6443 switch (Inst.getOpcode()) {
6444 case ARM::VSTR_FPSCR_pre:
6445 case ARM::VSTR_FPSCR_NZCVQC_pre:
6446 case ARM::VLDR_FPSCR_pre:
6447 case ARM::VLDR_FPSCR_NZCVQC_pre:
6448 case ARM::VSTR_FPSCR_off:
6449 case ARM::VSTR_FPSCR_NZCVQC_off:
6450 case ARM::VLDR_FPSCR_off:
6451 case ARM::VLDR_FPSCR_NZCVQC_off:
6452 case ARM::VSTR_FPSCR_post:
6453 case ARM::VSTR_FPSCR_NZCVQC_post:
6454 case ARM::VLDR_FPSCR_post:
6455 case ARM::VLDR_FPSCR_NZCVQC_post:
6456 const FeatureBitset &featureBits =
6457 Decoder->getSubtargetInfo().getFeatureBits();
6458
6459 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2])
6460 return MCDisassembler::Fail;
6461 }
6462
6463 DecodeStatus S = MCDisassembler::Success;
6464 if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode()))
6465 Inst.addOperand(MCOperand::createReg(Sysreg));
6466 unsigned Rn = fieldFromInstruction(Val, 16, 4);
6467 unsigned addr = fieldFromInstruction(Val, 0, 7) |
6468 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8);
6469
6470 if (Writeback) {
6471 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
6472 return MCDisassembler::Fail;
6473 }
6474 if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder)))
6475 return MCDisassembler::Fail;
6476
6477 Inst.addOperand(MCOperand::createImm(ARMCC::AL));
6478 Inst.addOperand(MCOperand::createReg(0));
6479
6480 return S;
6481}
6482
6483static inline DecodeStatus
6484DecodeMVE_MEM_pre(MCInst &Inst, unsigned Val, uint64_t Address,
6485 const MCDisassembler *Decoder, unsigned Rn,
6486 OperandDecoder RnDecoder, OperandDecoder AddrDecoder) {
6487 DecodeStatus S = MCDisassembler::Success;
6488
6489 unsigned Qd = fieldFromInstruction(Val, 13, 3);
6490 unsigned addr = fieldFromInstruction(Val, 0, 7) |
6491 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8);
6492
6493 if (!Check(S, RnDecoder(Inst, Rn, Address, Decoder)))
6494 return MCDisassembler::Fail;
6495 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
6496 return MCDisassembler::Fail;
6497 if (!Check(S, AddrDecoder(Inst, addr, Address, Decoder)))
6498 return MCDisassembler::Fail;
6499
6500 return S;
6501}
6502
6503template <int shift>
6504static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val,
6505 uint64_t Address,
6506 const MCDisassembler *Decoder) {
6507 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,
6508 fieldFromInstruction(Val, 16, 3),
6509 DecodetGPRRegisterClass,
6510 DecodeTAddrModeImm7<shift>);
6511}
6512
6513template <int shift>
6514static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val,
6515 uint64_t Address,
6516 const MCDisassembler *Decoder) {
6517 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,
6518 fieldFromInstruction(Val, 16, 4),
6519 DecoderGPRRegisterClass,
6520 DecodeT2AddrModeImm7<shift,1>);
6521}
6522
6523template <int shift>
6524static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val,
6525 uint64_t Address,
6526 const MCDisassembler *Decoder) {
6527 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,
6528 fieldFromInstruction(Val, 17, 3),
6529 DecodeMQPRRegisterClass,
6530 DecodeMveAddrModeQ<shift>);
6531}
6532
6533template <unsigned MinLog, unsigned MaxLog>
6534static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,
6535 uint64_t Address,
6536 const MCDisassembler *Decoder) {
6537 DecodeStatus S = MCDisassembler::Success;
6538
6539 if (Val < MinLog || Val > MaxLog)
6540 return MCDisassembler::Fail;
6541
6542 Inst.addOperand(MCOperand::createImm(1LL << Val));
6543 return S;
6544}
6545
6546template <unsigned start>
6547static DecodeStatus
6548DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address,
6549 const MCDisassembler *Decoder) {
6550 DecodeStatus S = MCDisassembler::Success;
6551
6552 Inst.addOperand(MCOperand::createImm(start + Val));
6553
6554 return S;
6555}
6556
6557static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn,
6558 uint64_t Address,
6559 const MCDisassembler *Decoder) {
6560 DecodeStatus S = MCDisassembler::Success;
6561 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
6562 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
6563 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
6564 fieldFromInstruction(Insn, 13, 3));
6565 unsigned index = fieldFromInstruction(Insn, 4, 1);
6566
6567 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
6568 return MCDisassembler::Fail;
6569 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder)))
6570 return MCDisassembler::Fail;
6571 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
6572 return MCDisassembler::Fail;
6573 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder)))
6574 return MCDisassembler::Fail;
6575 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder)))
6576 return MCDisassembler::Fail;
6577
6578 return S;
6579}
6580
6581static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn,
6582 uint64_t Address,
6583 const MCDisassembler *Decoder) {
6584 DecodeStatus S = MCDisassembler::Success;
6585 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
6586 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
6587 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
6588 fieldFromInstruction(Insn, 13, 3));
6589 unsigned index = fieldFromInstruction(Insn, 4, 1);
6590
6591 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
6592 return MCDisassembler::Fail;
6593 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
6594 return MCDisassembler::Fail;
6595 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
6596 return MCDisassembler::Fail;
6597 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder)))
6598 return MCDisassembler::Fail;
6599 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder)))
6600 return MCDisassembler::Fail;
6601 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder)))
6602 return MCDisassembler::Fail;
6603
6604 return S;
6605}
6606
6607static DecodeStatus
6608DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address,
6609 const MCDisassembler *Decoder) {
6610 DecodeStatus S = MCDisassembler::Success;
6611
6612 unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1;
6613 unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1;
6614 unsigned Rm = fieldFromInstruction(Insn, 12, 4);
6615
6616 if (RdaHi == 14) {
6617 // This value of RdaHi (really indicating pc, because RdaHi has to
6618 // be an odd-numbered register, so the low bit will be set by the
6619 // decode function below) indicates that we must decode as SQRSHR
6620 // or UQRSHL, which both have a single Rda register field with all
6621 // four bits.
6622 unsigned Rda = fieldFromInstruction(Insn, 16, 4);
6623
6624 switch (Inst.getOpcode()) {
6625 case ARM::MVE_ASRLr:
6626 case ARM::MVE_SQRSHRL:
6627 Inst.setOpcode(ARM::MVE_SQRSHR);
6628 break;
6629 case ARM::MVE_LSLLr:
6630 case ARM::MVE_UQRSHLL:
6631 Inst.setOpcode(ARM::MVE_UQRSHL);
6632 break;
6633 default:
6634 llvm_unreachable("Unexpected starting opcode!");
6635 }
6636
6637 // Rda as output parameter
6638 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder)))
6639 return MCDisassembler::Fail;
6640
6641 // Rda again as input parameter
6642 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder)))
6643 return MCDisassembler::Fail;
6644
6645 // Rm, the amount to shift by
6646 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
6647 return MCDisassembler::Fail;
6648
6649 if (fieldFromInstruction (Insn, 6, 3) != 4)
6650 return MCDisassembler::SoftFail;
6651
6652 if (Rda == Rm)
6653 return MCDisassembler::SoftFail;
6654
6655 return S;
6656 }
6657
6658 // Otherwise, we decode as whichever opcode our caller has already
6659 // put into Inst. Those all look the same:
6660
6661 // RdaLo,RdaHi as output parameters
6662 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder)))
6663 return MCDisassembler::Fail;
6664 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder)))
6665 return MCDisassembler::Fail;
6666
6667 // RdaLo,RdaHi again as input parameters
6668 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder)))
6669 return MCDisassembler::Fail;
6670 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder)))
6671 return MCDisassembler::Fail;
6672
6673 // Rm, the amount to shift by
6674 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
6675 return MCDisassembler::Fail;
6676
6677 if (Inst.getOpcode() == ARM::MVE_SQRSHRL ||
6678 Inst.getOpcode() == ARM::MVE_UQRSHLL) {
6679 unsigned Saturate = fieldFromInstruction(Insn, 7, 1);
6680 // Saturate, the bit position for saturation
6681 Inst.addOperand(MCOperand::createImm(Saturate));
6682 }
6683
6684 return S;
6685}
6686
6687static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn,
6688 uint64_t Address,
6689 const MCDisassembler *Decoder) {
6690 DecodeStatus S = MCDisassembler::Success;
6691 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
6692 fieldFromInstruction(Insn, 13, 3));
6693 unsigned Qm = ((fieldFromInstruction(Insn, 5, 1) << 3) |
6694 fieldFromInstruction(Insn, 1, 3));
6695 unsigned imm6 = fieldFromInstruction(Insn, 16, 6);
6696
6697 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
6698 return MCDisassembler::Fail;
6699 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
6700 return MCDisassembler::Fail;
6701 if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder)))
6702 return MCDisassembler::Fail;
6703
6704 return S;
6705}
6706
6707template <bool scalar, OperandDecoder predicate_decoder>
6708static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address,
6709 const MCDisassembler *Decoder) {
6710 DecodeStatus S = MCDisassembler::Success;
6711 Inst.addOperand(MCOperand::createReg(ARM::VPR));
6712 unsigned Qn = fieldFromInstruction(Insn, 17, 3);
6713 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))
6714 return MCDisassembler::Fail;
6715
6716 unsigned fc;
6717
6718 if (scalar) {
6719 fc = fieldFromInstruction(Insn, 12, 1) << 2 |
6720 fieldFromInstruction(Insn, 7, 1) |
6721 fieldFromInstruction(Insn, 5, 1) << 1;
6722 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
6723 if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder)))
6724 return MCDisassembler::Fail;
6725 } else {
6726 fc = fieldFromInstruction(Insn, 12, 1) << 2 |
6727 fieldFromInstruction(Insn, 7, 1) |
6728 fieldFromInstruction(Insn, 0, 1) << 1;
6729 unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 |
6730 fieldFromInstruction(Insn, 1, 3);
6731 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
6732 return MCDisassembler::Fail;
6733 }
6734
6735 if (!Check(S, predicate_decoder(Inst, fc, Address, Decoder)))
6736 return MCDisassembler::Fail;
6737
6738 Inst.addOperand(MCOperand::createImm(ARMVCC::None));
6739 Inst.addOperand(MCOperand::createReg(0));
6740 Inst.addOperand(MCOperand::createImm(0));
6741
6742 return S;
6743}
6744
6745static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address,
6746 const MCDisassembler *Decoder) {
6747 DecodeStatus S = MCDisassembler::Success;
6748 Inst.addOperand(MCOperand::createReg(ARM::VPR));
6749 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
6750 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
6751 return MCDisassembler::Fail;
6752 return S;
6753}
6754
6755static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn,
6756 uint64_t Address,
6757 const MCDisassembler *Decoder) {
6758 DecodeStatus S = MCDisassembler::Success;
6759 Inst.addOperand(MCOperand::createReg(ARM::VPR));
6760 Inst.addOperand(MCOperand::createReg(ARM::VPR));
6761 return S;
6762}
6763
6764static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn,
6765 uint64_t Address,
6766 const MCDisassembler *Decoder) {
6767 const unsigned Rd = fieldFromInstruction(Insn, 8, 4);
6768 const unsigned Rn = fieldFromInstruction(Insn, 16, 4);
6769 const unsigned Imm12 = fieldFromInstruction(Insn, 26, 1) << 11 |
6770 fieldFromInstruction(Insn, 12, 3) << 8 |
6771 fieldFromInstruction(Insn, 0, 8);
6772 const unsigned TypeT3 = fieldFromInstruction(Insn, 25, 1);
6773 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
6774 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
6775 unsigned S = fieldFromInstruction(Insn, 20, 1);
6776 if (sign1 != sign2)
6777 return MCDisassembler::Fail;
6778
6779 // T3 does a zext of imm12, where T2 does a ThumbExpandImm (T2SOImm)
6780 DecodeStatus DS = MCDisassembler::Success;
6781 if ((!Check(DS,
6782 DecodeGPRspRegisterClass(Inst, Rd, Address, Decoder))) || // dst
6783 (!Check(DS, DecodeGPRspRegisterClass(Inst, Rn, Address, Decoder))))
6784 return MCDisassembler::Fail;
6785 if (TypeT3) {
6786 Inst.setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12);
6787 Inst.addOperand(MCOperand::createImm(Imm12)); // zext imm12
6788 } else {
6789 Inst.setOpcode(sign1 ? ARM::t2SUBspImm : ARM::t2ADDspImm);
6790 if (!Check(DS, DecodeT2SOImm(Inst, Imm12, Address, Decoder))) // imm12
6791 return MCDisassembler::Fail;
6792 if (!Check(DS, DecodeCCOutOperand(Inst, S, Address, Decoder))) // cc_out
6793 return MCDisassembler::Fail;
6794 }
6795
6796 return DS;
6797}
6798
6799static DecodeStatus DecodeLazyLoadStoreMul(MCInst &Inst, unsigned Insn,
6800 uint64_t Address,
6801 const MCDisassembler *Decoder) {
6802 DecodeStatus S = MCDisassembler::Success;
6803
6804 const unsigned Rn = fieldFromInstruction(Insn, 16, 4);
6805 // Adding Rn, holding memory location to save/load to/from, the only argument
6806 // that is being encoded.
6807 // '$Rn' in the assembly.
6808 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
6809 return MCDisassembler::Fail;
6810 // An optional predicate, '$p' in the assembly.
6811 DecodePredicateOperand(Inst, ARMCC::AL, Address, Decoder);
6812 // An immediate that represents a floating point registers list. '$regs' in
6813 // the assembly.
6814 Inst.addOperand(MCOperand::createImm(0)); // Arbitrary value, has no effect.
6815
6816 return S;
6817}
6818
6819// Thumb VFP instructions are a special case. Because we share their
6820// encodings between ARM and Thumb modes, and they are predicable in ARM
6821// mode, the auto-generated decoder will give them an (incorrect)
6822// predicate operand. We need to rewrite these operands based on the IT
6823// context as a post-pass.
6824void ARMDisassembler::UpdateThumbVFPPredicate(
6825 DecodeStatus &S, MCInst &MI) const {
6826 unsigned CC;
6827 CC = ITBlock.getITCC();
6828 if (CC == 0xF)
6829 CC = ARMCC::AL;
6830 if (ITBlock.instrInITBlock())
6831 ITBlock.advanceITState();
6832 else if (VPTBlock.instrInVPTBlock()) {
6833 CC = VPTBlock.getVPTPred();
6834 VPTBlock.advanceVPTState();
6835 }
6836
6837 const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
6838 ArrayRef<MCOperandInfo> OpInfo = MCID.operands();
6839 MCInst::iterator I = MI.begin();
6840 unsigned short NumOps = MCID.NumOperands;
6841 for (unsigned i = 0; i < NumOps; ++i, ++I) {
6842 if (OpInfo[i].isPredicate() ) {
6843 if (CC != ARMCC::AL && !MCID.isPredicable())
6844 Check(S, SoftFail);
6845 I->setImm(CC);
6846 ++I;
6847 if (CC == ARMCC::AL)
6848 I->setReg(ARM::NoRegister);
6849 else
6850 I->setReg(ARM::CPSR);
6851 return;
6852 }
6853 }
6854}
6855
6856DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size,
6857 ArrayRef<uint8_t> Bytes,
6858 uint64_t Address,
6859 raw_ostream &CS) const {
6860 CommentStream = &CS;
6861
6862 assert(STI.hasFeature(ARM::ModeThumb) &&
6863 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
6864
6865 // We want to read exactly 2 bytes of data.
6866 if (Bytes.size() < 2) {
6867 Size = 0;
6868 return MCDisassembler::Fail;
6869 }
6870
6871 uint16_t Insn16 = llvm::support::endian::read<uint16_t>(
6872 Bytes.data(), InstructionEndianness);
6873 DecodeStatus Result =
6874 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);
6875 if (Result != MCDisassembler::Fail) {
6876 Size = 2;
6877 Check(Result, AddThumbPredicate(MI));
6878 return Result;
6879 }
6880
6881 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,
6882 STI);
6883 if (Result) {
6884 Size = 2;
6885 bool InITBlock = ITBlock.instrInITBlock();
6886 Check(Result, AddThumbPredicate(MI));
6887 AddThumb1SBit(MI, InITBlock);
6888 return Result;
6889 }
6890
6891 Result =
6892 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);
6893 if (Result != MCDisassembler::Fail) {
6894 Size = 2;
6895
6896 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
6897 // the Thumb predicate.
6898 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
6899 Result = MCDisassembler::SoftFail;
6900
6901 Check(Result, AddThumbPredicate(MI));
6902
6903 // If we find an IT instruction, we need to parse its condition
6904 // code and mask operands so that we can apply them correctly
6905 // to the subsequent instructions.
6906 if (MI.getOpcode() == ARM::t2IT) {
6907 unsigned Firstcond = MI.getOperand(0).getImm();
6908 unsigned Mask = MI.getOperand(1).getImm();
6909 ITBlock.setITState(Firstcond, Mask);
6910
6911 // An IT instruction that would give a 'NV' predicate is unpredictable.
6912 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask))
6913 CS << "unpredictable IT predicate sequence";
6914 }
6915
6916 return Result;
6917 }
6918
6919 // We want to read exactly 4 bytes of data.
6920 if (Bytes.size() < 4) {
6921 Size = 0;
6922 return MCDisassembler::Fail;
6923 }
6924
6925 uint32_t Insn32 =
6926 (uint32_t(Insn16) << 16) | llvm::support::endian::read<uint16_t>(
6927 Bytes.data() + 2, InstructionEndianness);
6928
6929 Result =
6930 decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI);
6931 if (Result != MCDisassembler::Fail) {
6932 Size = 4;
6933
6934 // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add
6935 // the VPT predicate.
6936 if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock())
6937 Result = MCDisassembler::SoftFail;
6938
6939 Check(Result, AddThumbPredicate(MI));
6940
6941 if (isVPTOpcode(MI.getOpcode())) {
6942 unsigned Mask = MI.getOperand(0).getImm();
6943 VPTBlock.setVPTState(Mask);
6944 }
6945
6946 return Result;
6947 }
6948
6949 Result =
6950 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
6951 if (Result != MCDisassembler::Fail) {
6952 Size = 4;
6953 bool InITBlock = ITBlock.instrInITBlock();
6954 Check(Result, AddThumbPredicate(MI));
6955 AddThumb1SBit(MI, InITBlock);
6956 return Result;
6957 }
6958
6959 Result =
6960 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);
6961 if (Result != MCDisassembler::Fail) {
6962 Size = 4;
6963 Check(Result, AddThumbPredicate(MI));
6964 return checkDecodedInstruction(MI, Size, Address, CS, Insn32, Result);
6965 }
6966
6967 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
6968 Result =
6969 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
6970 if (Result != MCDisassembler::Fail) {
6971 Size = 4;
6972 UpdateThumbVFPPredicate(Result, MI);
6973 return Result;
6974 }
6975 }
6976
6977 Result =
6978 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);
6979 if (Result != MCDisassembler::Fail) {
6980 Size = 4;
6981 return Result;
6982 }
6983
6984 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
6985 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,
6986 STI);
6987 if (Result != MCDisassembler::Fail) {
6988 Size = 4;
6989 Check(Result, AddThumbPredicate(MI));
6990 return Result;
6991 }
6992 }
6993
6994 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
6995 uint32_t NEONLdStInsn = Insn32;
6996 NEONLdStInsn &= 0xF0FFFFFF;
6997 NEONLdStInsn |= 0x04000000;
6998 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
6999 Address, this, STI);
7000 if (Result != MCDisassembler::Fail) {
7001 Size = 4;
7002 Check(Result, AddThumbPredicate(MI));
7003 return Result;
7004 }
7005 }
7006
7007 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
7008 uint32_t NEONDataInsn = Insn32;
7009 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
7010 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
7011 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
7012 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
7013 Address, this, STI);
7014 if (Result != MCDisassembler::Fail) {
7015 Size = 4;
7016 Check(Result, AddThumbPredicate(MI));
7017 return Result;
7018 }
7019
7020 uint32_t NEONCryptoInsn = Insn32;
7021 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
7022 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
7023 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
7024 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
7025 Address, this, STI);
7026 if (Result != MCDisassembler::Fail) {
7027 Size = 4;
7028 return Result;
7029 }
7030
7031 uint32_t NEONv8Insn = Insn32;
7032 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
7033 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
7034 this, STI);
7035 if (Result != MCDisassembler::Fail) {
7036 Size = 4;
7037 return Result;
7038 }
7039 }
7040
7041 uint32_t Coproc = fieldFromInstruction(Insn32, 8, 4);
7042 const uint8_t *DecoderTable = ARM::isCDECoproc(Coproc, STI)
7043 ? DecoderTableThumb2CDE32
7044 : DecoderTableThumb2CoProc32;
7045 Result =
7046 decodeInstruction(DecoderTable, MI, Insn32, Address, this, STI);
7047 if (Result != MCDisassembler::Fail) {
7048 Size = 4;
7049 Check(Result, AddThumbPredicate(MI));
7050 return Result;
7051 }
7052
7053 // Advance IT state to prevent next instruction inheriting
7054 // the wrong IT state.
7055 if (ITBlock.instrInITBlock())
7056 ITBlock.advanceITState();
7057 Size = 0;
7058 return MCDisassembler::Fail;
7059}
7060
7061extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
7062LLVMInitializeARMDisassembler() {
7063 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(),
7064 createARMDisassembler);
7065 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(),
7066 createARMDisassembler);
7067 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(),
7068 createARMDisassembler);
7069 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(),
7070 createARMDisassembler);
7071}
SoftFail
#define SoftFail
Definition: AArch64Disassembler.cpp:44
Success
#define Success
Definition: AArch64Disassembler.cpp:42
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
load
AMDGPU Mark last scratch load
Definition: AMDGPUMarkLastScratchLoad.cpp:164
isVectorPredicable
static bool isVectorPredicable(const MCInstrDesc &MCID)
Definition: ARMAsmParser.cpp:7647
DecodeDPairSpacedRegisterClass
static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:1365
DecodeCCOutOperand
static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:1395
DecodeAddrMode2IdxInstruction
static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:1787
DecodeT2AddrModeImm0_1020s4
static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:4216
DecodeT2AddrModeImm12
static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:4404
GPRPairDecoderTable
static const uint16_t GPRPairDecoderTable[]
Definition: ARMDisassembler.cpp:1137
DecodeNEONComplexLane64Instruction
static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:5875
DecodeLDRPreReg
static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:4911
DecodeGPRPairnospRegisterClass
static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:1161
DecodeDoubleRegStore
static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:4859
DecodeT2SOImm
static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:4636
DecodeT2LoadT
static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:4062
DecodeAddrMode6Operand
static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:2686
DecodeVSHLMaxInstruction
static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:3594
DecodeMVEVPNOT
static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:6755
DecodeGPRRegisterClass
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:1035
DecodeMVEVCMP
static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:6708
DecodeMVEVMOVDRegtoQ
static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:6581
DecodeShiftRight16Imm
static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:3621
DecodeAddrMode5FP16Operand
static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:2602
DecodeSORegImmOperand
static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:1405
QQPRDecoderTable
static const MCPhysReg QQPRDecoderTable[]
Definition: ARMDisassembler.cpp:6235
DecodeT2LoadLabel
static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:4101
DecodeQPRRegisterClass
static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:1321
DecodeSORegMemOperand
static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:1892
DecodeShiftRight64Imm
static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:3635
DecodeThumbTableBranch
static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:4575
DecodeVLD4LN
static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:5386
DecodeDPRRegListOperand
static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:1552
DecoderForMRRC2AndMCRR2
static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:5934
DecodeBitfieldMaskOperand
static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:1579
DecodeThumbAddrModePC
static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:3762
DecodeMVEPairVectorIndexOperand
static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:6548
DecodeThumb2BCCInstruction
static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:4593
DecodeGPRnopcRegisterClass
static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:1060
DecodeArmMOVTWInstruction
static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:2452
DecodeT2AddrModeImm8
static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:4259
DecoderGPRRegisterClass
static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:1216
DecodeTAddrModeImm7
static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:4307
DecodeBranchImmInstruction
static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:2656
DecodeT2AddrModeImm7s4
static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:4200
tryAddingPcLoadReferenceComment
static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, const MCDisassembler *Decoder)
tryAddingPcLoadReferenceComment - trys to add a comment as to what is being referenced by a load inst...
Definition: ARMDisassembler.cpp:726
DecodeGPRwithAPSRRegisterClass
static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:1087
DecodeShiftRight32Imm
static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:3628
LLVMInitializeARMDisassembler
LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMDisassembler()
Definition: ARMDisassembler.cpp:7062
DecodeT2MOVTWInstruction
static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:2427
DPairDecoderTable
static const MCPhysReg DPairDecoderTable[]
Definition: ARMDisassembler.cpp:1333
DecodeTSBInstruction
static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:1936
DecodeMVE_MEM_1_pre
static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:6504
DecodeDoubleRegLoad
static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:4837
DecodeVMOVModImmInstruction
static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:3493
DecodeThumbAddrModeIS
static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:3747
DecodePowerTwoOperand
static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:6534
DecodeT2Imm7S4
static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:4169
DecodeQADDInstruction
static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:2171
DPairSpacedDecoderTable
static const MCPhysReg DPairSpacedDecoderTable[]
Definition: ARMDisassembler.cpp:1353
DecodeThumbBROperand
static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:3704
DecodeRestrictedIPredicateOperand
static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:6323
DecodeSTRPreReg
static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:4965
DecodeVLD1DupInstruction
static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:3307
DecodeSPRRegisterClass
static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:1242
DecodeSETPANInstruction
static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:2531
DecodeThumbAddSPReg
static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:4443
DecodeMQQQQPRRegisterClass
static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:6256
DecodeVLD4DupInstruction
static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:3440
DecodeT2ShifterImmOperand
static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
DecodeVLD2LN
static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:5123
DecodeT2AddSubSPImm
static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:6764
createARMDisassembler
static MCDisassembler * createARMDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: ARMDisassembler.cpp:733
DecodeT2LoadImm12
static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:3981
FixedRegForVSTRVLDR_SYSREG
static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode)
Definition: ARMDisassembler.cpp:6418
DecodeVST1LN
static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:5058
DecodeLDR
static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:5907
QPRDecoderTable
static const MCPhysReg QPRDecoderTable[]
Definition: ARMDisassembler.cpp:1314
DecodeVST3LN
static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:5323
SPRDecoderTable
static const MCPhysReg SPRDecoderTable[]
Definition: ARMDisassembler.cpp:1231
DecodeRestrictedUPredicateOperand
static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:6352
DecodetGPRRegisterClass
static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:1129
DecodeCLRMGPRRegisterClass
static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:1046
DecodeAddrMode5Operand
static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:2581
DecodeMQQPRRegisterClass
static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:6240
DecodeVMOVRRS
static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:5565
DecodeGPRwithAPSR_NZCVnospRegisterClass
static DecodeStatus DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:6170
DecodeVLDST3Instruction
static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:3011
OperandDecoder
DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:674
DecodeThumbBLTargetOperand
static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:4676
DecodeVLDST2Instruction
static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:2995
DecodeAddrMode3Instruction
static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:1949
DecodeSMLAInstruction
static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:2480
DecodeSwap
static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:5729
DecodeGPRwithZRRegisterClass
static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:1102
DecodeVCVTD
static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:5756
DecodeCopMemInstruction
static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:1607
DecodeVLD3DupInstruction
static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:3404
DecodeMemBarrierOption
static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:4700
DecodeVpredNOperand
static DecodeStatus DecodeVpredNOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:6312
DecodeDPR_VFP2RegisterClass
static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:1306
DecodeT2CPSInstruction
static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:2359
DecodeThumbBCCTargetOperand
static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:4667
DecodeMVE_MEM_3_pre
static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:6524
DecodeIT
static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:5591
DecodeVSTInstruction
static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:3036
DecodeAddrMode7Operand
static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:2623
DecodeThumbAddrModeSP
static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:3773
DecodeT2STRDPreInstruction
static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:5657
DecodeVLD1LN
static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:4991
PermitsD32
static bool PermitsD32(const MCInst &Inst, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:1271
DecodeVSTRVLDR_SYSREG
static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:6440
DecodeT2Imm8
static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:4232
DecodeThumbAddSPImm
static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:4431
CLRMGPRDecoderTable
static const uint16_t CLRMGPRDecoderTable[]
Definition: ARMDisassembler.cpp:1028
DPRDecoderTable
static const MCPhysReg DPRDecoderTable[]
Definition: ARMDisassembler.cpp:1259
DecodePostIdxReg
static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:4481
DecodeCoprocessor
static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:4559
DecodeVLD3LN
static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:5253
DecodeT2LDRDPreInstruction
static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:5620
DecodeT2Imm8S4
static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:4155
DecodeThumbCPS
static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:4469
DecodeCPSInstruction
static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:2311
DecodeThumbAddSpecialReg
static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:3679
DecodeRestrictedSPredicateOperand
static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:6330
DecodeVCVTQ
static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:5815
DecodeSPRRegListOperand
static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:1527
DecodeVLDST4Instruction
static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:3025
DecodeT2LdStPre
static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:4342
DecodeGPRPairRegisterClass
static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:1142
DecodeMQPRRegisterClass
static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:6224
DecodeVLDInstruction
static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:2704
tryAddingSymbolicOperand
static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, bool isBranch, uint64_t InstSize, MCInst &MI, const MCDisassembler *Decoder)
tryAddingSymbolicOperand - trys to add a symbolic operand in place of the immediate Value in the MCIn...
Definition: ARMDisassembler.cpp:707
DecodeT2LoadImm8
static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:3896
DecodeMVEModImmInstruction
static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:3539
DecodeGPRwithZRnospRegisterClass
static DecodeStatus DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:1120
GPRDecoderTable
static const uint16_t GPRDecoderTable[]
Definition: ARMDisassembler.cpp:1021
DecodeVCVTImmOperand
static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:6389
DecodeMveAddrModeQ
static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:4511
DecodeT2LoadShift
static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:3812
DecodeT2Imm7
static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:4245
DecodeDPRRegisterClass
static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:1279
DecodeThumbCmpBROperand
static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:3722
DecodeMVE_MEM_2_pre
static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:6514
DecodeMVEVCVTt1fp
static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:6687
DecodeMSRMask
static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:4720
DecodeMVEVMOVQtoDReg
static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:6557
QQQQPRDecoderTable
static const MCPhysReg QQQQPRDecoderTable[]
Definition: ARMDisassembler.cpp:6251
DecodeLongShiftOperand
static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:6134
DecodeMveAddrModeRQ
static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:4495
DecodeBFAfterTargetOperand
static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:6051
DecodeGPRspRegisterClass
static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:1174
DecodeMVE_MEM_pre
static DecodeStatus DecodeMVE_MEM_pre(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder, unsigned Rn, OperandDecoder RnDecoder, OperandDecoder AddrDecoder)
Definition: ARMDisassembler.cpp:6484
DecodeT2AddrModeImm8s4
static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:4184
DecodeVpredROperand
static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:6298
DecodeMveVCTP
static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:6745
checkDecodedInstruction
static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, uint64_t Address, raw_ostream &CS, uint32_t Insn, DecodeStatus Result)
Definition: ARMDisassembler.cpp:740
DecodeVST4LN
static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:5467
DecodeSTRPreImm
static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:4939
DecodetcGPRRegisterClass
static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:1185
DecodePredNoALOperand
static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:6063
DecodeVST2LN
static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:5190
DecodeVLDST1Instruction
static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:2981
DecodeVPTMaskOperand
static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:6267
DecodeRegListOperand
static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:1479
DecodeMVEOverlappingLongShift
static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:6608
DecodeInstSyncBarrierOption
static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:4710
DecodePredicateOperand
static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:1375
DecodeT2AddrModeSOReg
static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:3782
DecodeShiftRight8Imm
static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:3614
DecodeT2AddrModeImm7
static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:4324
DecodeVLD2DupInstruction
static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:3355
DecodeTSTInstruction
static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:2509
DecodeAddrModeImm12Operand
static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:2560
DecodeTBLInstruction
static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:3642
DecodeLDRPreImm
static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:4885
DecodeT2HintSpaceInstruction
static DecodeStatus DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:2403
DecodeBFLabelOperand
static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:6032
DecodeHPRRegisterClass
static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:1253
DecodeDPairRegisterClass
static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:1342
DecodeRestrictedFPPredicateOperand
static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:6359
DecodeHINTInstruction
static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:2288
DecodeVSCCLRM
static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:6187
DecodeT2BROperand
static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:3713
DecodeBankedReg
static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:4821
DecodeMVEVADCInstruction
static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:3568
DecodeRFEInstruction
static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:2141
DecodeMemMultipleWritebackInstruction
static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn, uint64_t Adddress, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:2196
DecodeT2BInstruction
static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:2629
DecodeThumbBLXOffset
static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:4534
DecodeDPR_8RegisterClass
static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:1290
DecodetGPREvenRegisterClass
static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:6158
DecodeThumbAddrModeRR
static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:3731
DecodetGPROddRegisterClass
static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:6147
DecodeT2Adr
static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
DecodeGPRnospRegisterClass
static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:1073
DecodeSORegRegOperand
static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:1443
DecodeSPR_8RegisterClass
static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:1298
DecodeVMOVSRR
static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:5539
DecodeLazyLoadStoreMul
static DecodeStatus DecodeLazyLoadStoreMul(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:6799
DecodeForVMRSandVMSR
static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:5980
DecodeLOLoop
static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: ARMDisassembler.cpp:6072
LLVM_ABI
#define LLVM_ABI
Definition: Compiler.h:213
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:132
isNeg
static bool isNeg(Value *V)
Returns true if the operation is a negation of V, and it works for both integers and floats.
Definition: ComplexDeinterleavingPass.cpp:614
Size
uint64_t Size
Definition: ELFObjHandler.cpp:81
isSigned
static bool isSigned(unsigned int Opcode)
Definition: ExpandLargeDivRem.cpp:52
Check
#define Check(C,...)
Definition: GenericConvergenceVerifierImpl.h:34
op
#define op(i)
mode
amode Optimize addressing mode
Definition: HexagonOptAddrMode.cpp:132
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:110
I
#define I(x, y, z)
Definition: MD5.cpp:58
P
#define P(N)
isBranch
static bool isBranch(unsigned Opcode)
Definition: R600InstrInfo.cpp:632
Cond
const SmallVectorImpl< MachineOperand > & Cond
Definition: RISCVRedundantCopyElimination.cpp:71
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:147
llvm::ArrayRef::data
const T * data() const
Definition: ArrayRef.h:144
llvm::DWARFExpression::Operation
This class represents an Operation in the Expression.
Definition: DWARFExpression.h:33
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:42
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:83
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:85
llvm::MCDisassembler::tryAddingSymbolicOperand
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const
Definition: MCDisassembler.cpp:28
llvm::MCDisassembler::getSubtargetInfo
const MCSubtargetInfo & getSubtargetInfo() const
Definition: MCDisassembler.h:230
llvm::MCDisassembler::tryAddingPcLoadReferenceComment
void tryAddingPcLoadReferenceComment(int64_t Value, uint64_t Address) const
Definition: MCDisassembler.cpp:41
llvm::MCDisassembler::suggestBytesToSkip
virtual uint64_t suggestBytesToSkip(ArrayRef< uint8_t > Bytes, uint64_t Address) const
Suggest a distance to skip in a buffer of data to find the next place to look for the start of an ins...
Definition: MCDisassembler.cpp:23
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:109
llvm::MCDisassembler::getInstruction
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:188
llvm::MCInst::getNumOperands
unsigned getNumOperands() const
Definition: MCInst.h:212
llvm::MCInst::iterator
SmallVectorImpl< MCOperand >::iterator iterator
Definition: MCInst.h:220
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:202
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:215
llvm::MCInst::end
iterator end()
Definition: MCInst.h:229
llvm::MCInst::setOpcode
void setOpcode(unsigned Op)
Definition: MCInst.h:201
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:210
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:199
llvm::MCInstrDesc::operands
ArrayRef< MCOperandInfo > operands() const
Definition: MCInstrDesc.h:240
llvm::MCInstrDesc::NumOperands
unsigned short NumOperands
Definition: MCInstrDesc.h:207
llvm::MCInstrDesc::getOperandConstraint
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
Definition: MCInstrDesc.h:220
llvm::MCInstrDesc::isPredicable
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
Definition: MCInstrDesc.h:340
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:27
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:64
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:40
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:84
llvm::MCOperand::createReg
static MCOperand createReg(MCRegister Reg)
Definition: MCInst.h:138
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:145
llvm::MCOperand::getReg
MCRegister getReg() const
Returns the register number.
Definition: MCInst.h:73
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:77
llvm::MCSubtargetInfo::hasFeature
bool hasFeature(unsigned Feature) const
Definition: MCSubtargetInfo.h:122
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:115
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1197
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:146
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
uint16_t
uint32_t
uint64_t
uint8_t
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:164
llvm::ARM_AM::da
@ da
Definition: ARMAddressingModes.h:70
llvm::ARM_AM::ib
@ ib
Definition: ARMAddressingModes.h:69
llvm::ARM_AM::db
@ db
Definition: ARMAddressingModes.h:71
llvm::ARM_AM::ia
@ ia
Definition: ARMAddressingModes.h:68
llvm::ARM_AM::getAM2Opc
unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO, unsigned IdxMode=0)
Definition: ARMAddressingModes.h:400
llvm::ARM_AM::getAM5Opc
unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset)
getAM5Opc - This function encodes the addrmode5 opc field.
Definition: ARMAddressingModes.h:476
llvm::ARM_AM::AddrOpc
AddrOpc
Definition: ARMAddressingModes.h:37
llvm::ARM_AM::sub
@ sub
Definition: ARMAddressingModes.h:38
llvm::ARM_AM::add
@ add
Definition: ARMAddressingModes.h:39
llvm::ARM_AM::getAM5FP16Opc
unsigned getAM5FP16Opc(AddrOpc Opc, unsigned char Offset)
getAM5FP16Opc - This function encodes the addrmode5fp16 opc field.
Definition: ARMAddressingModes.h:497
llvm::ARM_AM::ShiftOpc
ShiftOpc
Definition: ARMAddressingModes.h:27
llvm::ARM_AM::lsr
@ lsr
Definition: ARMAddressingModes.h:31
llvm::ARM_AM::asr
@ asr
Definition: ARMAddressingModes.h:29
llvm::ARM_AM::lsl
@ lsl
Definition: ARMAddressingModes.h:30
llvm::ARM_AM::rrx
@ rrx
Definition: ARMAddressingModes.h:33
llvm::ARM_AM::ror
@ ror
Definition: ARMAddressingModes.h:32
llvm::ARM_TSB::CSYNC
@ CSYNC
Definition: ARMBaseInfo.h:102
llvm::ARM::isVpred
bool isVpred(OperandType op)
Definition: ARMMCTargetDesc.h:118
llvm::ARM::isCDECoproc
bool isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI)
Definition: ARMMCTargetDesc.cpp:759
llvm::ARM::FPURestriction::D16
@ D16
Only 16 D registers.
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:126
llvm::MCD::fieldFromInstruction
std::enable_if_t< std::is_integral_v< IntType >, IntType > fieldFromInstruction(const IntType &Insn, unsigned StartBit, unsigned NumBits)
Definition: MCDecoder.h:37
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::size
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition: STLExtras.h:1702
llvm::getTheThumbBETarget
Target & getTheThumbBETarget()
Definition: ARMTargetInfo.cpp:27
llvm::isVPTOpcode
static bool isVPTOpcode(int Opc)
Definition: ARMBaseInstrInfo.h:569
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:288
llvm::isValidCoprocessorNumber
static bool isValidCoprocessorNumber(unsigned Num, const FeatureBitset &featureBits)
isValidCoprocessorNumber - decide whether an explicit coprocessor number is legal in generic instruct...
Definition: ARMBaseInstrInfo.h:739
llvm::endianness
endianness
Definition: bit.h:71
llvm::getTheARMLETarget
Target & getTheARMLETarget()
Definition: ARMTargetInfo.cpp:15
llvm::getTheARMBETarget
Target & getTheARMBETarget()
Definition: ARMTargetInfo.cpp:19
llvm::getTheThumbLETarget
Target & getTheThumbLETarget()
Definition: ARMTargetInfo.cpp:23
raw_ostream.h
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition: TargetRegistry.h:897
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