LLVM 22.0.0git
NVVMIntrinsicUtils.h
Go to the documentation of this file.
1//===--- NVVMIntrinsicUtils.h -----------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// This file contains the definitions of the enumerations and flags
11/// associated with NVVM Intrinsics, along with some helper functions.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_IR_NVVMINTRINSICUTILS_H
16#define LLVM_IR_NVVMINTRINSICUTILS_H
17
18#include <stdint.h>
19
20#include "llvm/ADT/APFloat.h"
21#include "llvm/IR/Intrinsics.h"
22#include "llvm/IR/IntrinsicsNVPTX.h"
23
24namespace llvm {
25namespace nvvm {
26
27// Reduction Ops supported with TMA Copy from Shared
28// to Global Memory for the "cp.reduce.async.bulk.tensor.*"
29// family of PTX instructions.
30enum class TMAReductionOp : uint8_t {
31 ADD = 0,
32 MIN = 1,
33 MAX = 2,
34 INC = 3,
35 DEC = 4,
36 AND = 5,
37 OR = 6,
38 XOR = 7,
39};
40
41// Enum to represent the cta_group::1 and
42// cta_group::2 variants in TMA/TCGEN05 family of
43// PTX instructions.
44enum class CTAGroupKind : uint8_t {
45 CG_NONE = 0, // default with no cta_group modifier
46 CG_1 = 1, // cta_group::1 modifier
47 CG_2 = 2, // cta_group::2 modifier
48};
49
50inline bool FPToIntegerIntrinsicShouldFTZ(Intrinsic::ID IntrinsicID) {
51 switch (IntrinsicID) {
52 case Intrinsic::nvvm_f2i_rm_ftz:
53 case Intrinsic::nvvm_f2i_rn_ftz:
54 case Intrinsic::nvvm_f2i_rp_ftz:
55 case Intrinsic::nvvm_f2i_rz_ftz:
56
57 case Intrinsic::nvvm_f2ui_rm_ftz:
58 case Intrinsic::nvvm_f2ui_rn_ftz:
59 case Intrinsic::nvvm_f2ui_rp_ftz:
60 case Intrinsic::nvvm_f2ui_rz_ftz:
61
62 case Intrinsic::nvvm_f2ll_rm_ftz:
63 case Intrinsic::nvvm_f2ll_rn_ftz:
64 case Intrinsic::nvvm_f2ll_rp_ftz:
65 case Intrinsic::nvvm_f2ll_rz_ftz:
66
67 case Intrinsic::nvvm_f2ull_rm_ftz:
68 case Intrinsic::nvvm_f2ull_rn_ftz:
69 case Intrinsic::nvvm_f2ull_rp_ftz:
70 case Intrinsic::nvvm_f2ull_rz_ftz:
71 return true;
72
73 case Intrinsic::nvvm_f2i_rm:
74 case Intrinsic::nvvm_f2i_rn:
75 case Intrinsic::nvvm_f2i_rp:
76 case Intrinsic::nvvm_f2i_rz:
77
78 case Intrinsic::nvvm_f2ui_rm:
79 case Intrinsic::nvvm_f2ui_rn:
80 case Intrinsic::nvvm_f2ui_rp:
81 case Intrinsic::nvvm_f2ui_rz:
82
83 case Intrinsic::nvvm_d2i_rm:
84 case Intrinsic::nvvm_d2i_rn:
85 case Intrinsic::nvvm_d2i_rp:
86 case Intrinsic::nvvm_d2i_rz:
87
88 case Intrinsic::nvvm_d2ui_rm:
89 case Intrinsic::nvvm_d2ui_rn:
90 case Intrinsic::nvvm_d2ui_rp:
91 case Intrinsic::nvvm_d2ui_rz:
92
93 case Intrinsic::nvvm_f2ll_rm:
94 case Intrinsic::nvvm_f2ll_rn:
95 case Intrinsic::nvvm_f2ll_rp:
96 case Intrinsic::nvvm_f2ll_rz:
97
98 case Intrinsic::nvvm_f2ull_rm:
99 case Intrinsic::nvvm_f2ull_rn:
100 case Intrinsic::nvvm_f2ull_rp:
101 case Intrinsic::nvvm_f2ull_rz:
102
103 case Intrinsic::nvvm_d2ll_rm:
104 case Intrinsic::nvvm_d2ll_rn:
105 case Intrinsic::nvvm_d2ll_rp:
106 case Intrinsic::nvvm_d2ll_rz:
107
108 case Intrinsic::nvvm_d2ull_rm:
109 case Intrinsic::nvvm_d2ull_rn:
110 case Intrinsic::nvvm_d2ull_rp:
111 case Intrinsic::nvvm_d2ull_rz:
112 return false;
113 }
114 llvm_unreachable("Checking FTZ flag for invalid f2i/d2i intrinsic");
115}
116
117inline bool FPToIntegerIntrinsicResultIsSigned(Intrinsic::ID IntrinsicID) {
118 switch (IntrinsicID) {
119 // f2i
120 case Intrinsic::nvvm_f2i_rm:
121 case Intrinsic::nvvm_f2i_rm_ftz:
122 case Intrinsic::nvvm_f2i_rn:
123 case Intrinsic::nvvm_f2i_rn_ftz:
124 case Intrinsic::nvvm_f2i_rp:
125 case Intrinsic::nvvm_f2i_rp_ftz:
126 case Intrinsic::nvvm_f2i_rz:
127 case Intrinsic::nvvm_f2i_rz_ftz:
128 // d2i
129 case Intrinsic::nvvm_d2i_rm:
130 case Intrinsic::nvvm_d2i_rn:
131 case Intrinsic::nvvm_d2i_rp:
132 case Intrinsic::nvvm_d2i_rz:
133 // f2ll
134 case Intrinsic::nvvm_f2ll_rm:
135 case Intrinsic::nvvm_f2ll_rm_ftz:
136 case Intrinsic::nvvm_f2ll_rn:
137 case Intrinsic::nvvm_f2ll_rn_ftz:
138 case Intrinsic::nvvm_f2ll_rp:
139 case Intrinsic::nvvm_f2ll_rp_ftz:
140 case Intrinsic::nvvm_f2ll_rz:
141 case Intrinsic::nvvm_f2ll_rz_ftz:
142 // d2ll
143 case Intrinsic::nvvm_d2ll_rm:
144 case Intrinsic::nvvm_d2ll_rn:
145 case Intrinsic::nvvm_d2ll_rp:
146 case Intrinsic::nvvm_d2ll_rz:
147 return true;
148
149 // f2ui
150 case Intrinsic::nvvm_f2ui_rm:
151 case Intrinsic::nvvm_f2ui_rm_ftz:
152 case Intrinsic::nvvm_f2ui_rn:
153 case Intrinsic::nvvm_f2ui_rn_ftz:
154 case Intrinsic::nvvm_f2ui_rp:
155 case Intrinsic::nvvm_f2ui_rp_ftz:
156 case Intrinsic::nvvm_f2ui_rz:
157 case Intrinsic::nvvm_f2ui_rz_ftz:
158 // d2ui
159 case Intrinsic::nvvm_d2ui_rm:
160 case Intrinsic::nvvm_d2ui_rn:
161 case Intrinsic::nvvm_d2ui_rp:
162 case Intrinsic::nvvm_d2ui_rz:
163 // f2ull
164 case Intrinsic::nvvm_f2ull_rm:
165 case Intrinsic::nvvm_f2ull_rm_ftz:
166 case Intrinsic::nvvm_f2ull_rn:
167 case Intrinsic::nvvm_f2ull_rn_ftz:
168 case Intrinsic::nvvm_f2ull_rp:
169 case Intrinsic::nvvm_f2ull_rp_ftz:
170 case Intrinsic::nvvm_f2ull_rz:
171 case Intrinsic::nvvm_f2ull_rz_ftz:
172 // d2ull
173 case Intrinsic::nvvm_d2ull_rm:
174 case Intrinsic::nvvm_d2ull_rn:
175 case Intrinsic::nvvm_d2ull_rp:
176 case Intrinsic::nvvm_d2ull_rz:
177 return false;
178 }
179 llvm_unreachable(
180 "Checking invalid f2i/d2i intrinsic for signed int conversion");
181}
182
183inline APFloat::roundingMode
184GetFPToIntegerRoundingMode(Intrinsic::ID IntrinsicID) {
185 switch (IntrinsicID) {
186 // RM:
187 case Intrinsic::nvvm_f2i_rm:
188 case Intrinsic::nvvm_f2ui_rm:
189 case Intrinsic::nvvm_f2i_rm_ftz:
190 case Intrinsic::nvvm_f2ui_rm_ftz:
191 case Intrinsic::nvvm_d2i_rm:
192 case Intrinsic::nvvm_d2ui_rm:
193
194 case Intrinsic::nvvm_f2ll_rm:
195 case Intrinsic::nvvm_f2ull_rm:
196 case Intrinsic::nvvm_f2ll_rm_ftz:
197 case Intrinsic::nvvm_f2ull_rm_ftz:
198 case Intrinsic::nvvm_d2ll_rm:
199 case Intrinsic::nvvm_d2ull_rm:
200 return APFloat::rmTowardNegative;
201
202 // RN:
203 case Intrinsic::nvvm_f2i_rn:
204 case Intrinsic::nvvm_f2ui_rn:
205 case Intrinsic::nvvm_f2i_rn_ftz:
206 case Intrinsic::nvvm_f2ui_rn_ftz:
207 case Intrinsic::nvvm_d2i_rn:
208 case Intrinsic::nvvm_d2ui_rn:
209
210 case Intrinsic::nvvm_f2ll_rn:
211 case Intrinsic::nvvm_f2ull_rn:
212 case Intrinsic::nvvm_f2ll_rn_ftz:
213 case Intrinsic::nvvm_f2ull_rn_ftz:
214 case Intrinsic::nvvm_d2ll_rn:
215 case Intrinsic::nvvm_d2ull_rn:
216 return APFloat::rmNearestTiesToEven;
217
218 // RP:
219 case Intrinsic::nvvm_f2i_rp:
220 case Intrinsic::nvvm_f2ui_rp:
221 case Intrinsic::nvvm_f2i_rp_ftz:
222 case Intrinsic::nvvm_f2ui_rp_ftz:
223 case Intrinsic::nvvm_d2i_rp:
224 case Intrinsic::nvvm_d2ui_rp:
225
226 case Intrinsic::nvvm_f2ll_rp:
227 case Intrinsic::nvvm_f2ull_rp:
228 case Intrinsic::nvvm_f2ll_rp_ftz:
229 case Intrinsic::nvvm_f2ull_rp_ftz:
230 case Intrinsic::nvvm_d2ll_rp:
231 case Intrinsic::nvvm_d2ull_rp:
232 return APFloat::rmTowardPositive;
233
234 // RZ:
235 case Intrinsic::nvvm_f2i_rz:
236 case Intrinsic::nvvm_f2ui_rz:
237 case Intrinsic::nvvm_f2i_rz_ftz:
238 case Intrinsic::nvvm_f2ui_rz_ftz:
239 case Intrinsic::nvvm_d2i_rz:
240 case Intrinsic::nvvm_d2ui_rz:
241
242 case Intrinsic::nvvm_f2ll_rz:
243 case Intrinsic::nvvm_f2ull_rz:
244 case Intrinsic::nvvm_f2ll_rz_ftz:
245 case Intrinsic::nvvm_f2ull_rz_ftz:
246 case Intrinsic::nvvm_d2ll_rz:
247 case Intrinsic::nvvm_d2ull_rz:
248 return APFloat::rmTowardZero;
249 }
250 llvm_unreachable("Checking rounding mode for invalid f2i/d2i intrinsic");
251}
252
253inline bool FMinFMaxShouldFTZ(Intrinsic::ID IntrinsicID) {
254 switch (IntrinsicID) {
255 case Intrinsic::nvvm_fmax_ftz_f:
256 case Intrinsic::nvvm_fmax_ftz_nan_f:
257 case Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs_f:
258 case Intrinsic::nvvm_fmax_ftz_xorsign_abs_f:
259
260 case Intrinsic::nvvm_fmin_ftz_f:
261 case Intrinsic::nvvm_fmin_ftz_nan_f:
262 case Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs_f:
263 case Intrinsic::nvvm_fmin_ftz_xorsign_abs_f:
264 return true;
265
266 case Intrinsic::nvvm_fmax_d:
267 case Intrinsic::nvvm_fmax_f:
268 case Intrinsic::nvvm_fmax_nan_f:
269 case Intrinsic::nvvm_fmax_nan_xorsign_abs_f:
270 case Intrinsic::nvvm_fmax_xorsign_abs_f:
271
272 case Intrinsic::nvvm_fmin_d:
273 case Intrinsic::nvvm_fmin_f:
274 case Intrinsic::nvvm_fmin_nan_f:
275 case Intrinsic::nvvm_fmin_nan_xorsign_abs_f:
276 case Intrinsic::nvvm_fmin_xorsign_abs_f:
277 return false;
278 }
279 llvm_unreachable("Checking FTZ flag for invalid fmin/fmax intrinsic");
280}
281
282inline bool FMinFMaxPropagatesNaNs(Intrinsic::ID IntrinsicID) {
283 switch (IntrinsicID) {
284 case Intrinsic::nvvm_fmax_ftz_nan_f:
285 case Intrinsic::nvvm_fmax_nan_f:
286 case Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs_f:
287 case Intrinsic::nvvm_fmax_nan_xorsign_abs_f:
288
289 case Intrinsic::nvvm_fmin_ftz_nan_f:
290 case Intrinsic::nvvm_fmin_nan_f:
291 case Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs_f:
292 case Intrinsic::nvvm_fmin_nan_xorsign_abs_f:
293 return true;
294
295 case Intrinsic::nvvm_fmax_d:
296 case Intrinsic::nvvm_fmax_f:
297 case Intrinsic::nvvm_fmax_ftz_f:
298 case Intrinsic::nvvm_fmax_ftz_xorsign_abs_f:
299 case Intrinsic::nvvm_fmax_xorsign_abs_f:
300
301 case Intrinsic::nvvm_fmin_d:
302 case Intrinsic::nvvm_fmin_f:
303 case Intrinsic::nvvm_fmin_ftz_f:
304 case Intrinsic::nvvm_fmin_ftz_xorsign_abs_f:
305 case Intrinsic::nvvm_fmin_xorsign_abs_f:
306 return false;
307 }
308 llvm_unreachable("Checking NaN flag for invalid fmin/fmax intrinsic");
309}
310
311inline bool FMinFMaxIsXorSignAbs(Intrinsic::ID IntrinsicID) {
312 switch (IntrinsicID) {
313 case Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs_f:
314 case Intrinsic::nvvm_fmax_ftz_xorsign_abs_f:
315 case Intrinsic::nvvm_fmax_nan_xorsign_abs_f:
316 case Intrinsic::nvvm_fmax_xorsign_abs_f:
317
318 case Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs_f:
319 case Intrinsic::nvvm_fmin_ftz_xorsign_abs_f:
320 case Intrinsic::nvvm_fmin_nan_xorsign_abs_f:
321 case Intrinsic::nvvm_fmin_xorsign_abs_f:
322 return true;
323
324 case Intrinsic::nvvm_fmax_d:
325 case Intrinsic::nvvm_fmax_f:
326 case Intrinsic::nvvm_fmax_ftz_f:
327 case Intrinsic::nvvm_fmax_ftz_nan_f:
328 case Intrinsic::nvvm_fmax_nan_f:
329
330 case Intrinsic::nvvm_fmin_d:
331 case Intrinsic::nvvm_fmin_f:
332 case Intrinsic::nvvm_fmin_ftz_f:
333 case Intrinsic::nvvm_fmin_ftz_nan_f:
334 case Intrinsic::nvvm_fmin_nan_f:
335 return false;
336 }
337 llvm_unreachable("Checking XorSignAbs flag for invalid fmin/fmax intrinsic");
338}
339
340inline bool UnaryMathIntrinsicShouldFTZ(Intrinsic::ID IntrinsicID) {
341 switch (IntrinsicID) {
342 case Intrinsic::nvvm_ceil_ftz_f:
343 case Intrinsic::nvvm_fabs_ftz:
344 case Intrinsic::nvvm_floor_ftz_f:
345 case Intrinsic::nvvm_round_ftz_f:
346 case Intrinsic::nvvm_saturate_ftz_f:
347 case Intrinsic::nvvm_sqrt_rn_ftz_f:
348 return true;
349 case Intrinsic::nvvm_ceil_f:
350 case Intrinsic::nvvm_ceil_d:
351 case Intrinsic::nvvm_fabs:
352 case Intrinsic::nvvm_floor_f:
353 case Intrinsic::nvvm_floor_d:
354 case Intrinsic::nvvm_round_f:
355 case Intrinsic::nvvm_round_d:
356 case Intrinsic::nvvm_saturate_d:
357 case Intrinsic::nvvm_saturate_f:
358 case Intrinsic::nvvm_sqrt_f:
359 case Intrinsic::nvvm_sqrt_rn_d:
360 case Intrinsic::nvvm_sqrt_rn_f:
361 return false;
362 }
363 llvm_unreachable("Checking FTZ flag for invalid unary intrinsic");
364}
365
366inline bool RCPShouldFTZ(Intrinsic::ID IntrinsicID) {
367 switch (IntrinsicID) {
368 case Intrinsic::nvvm_rcp_rm_ftz_f:
369 case Intrinsic::nvvm_rcp_rn_ftz_f:
370 case Intrinsic::nvvm_rcp_rp_ftz_f:
371 case Intrinsic::nvvm_rcp_rz_ftz_f:
372 return true;
373 case Intrinsic::nvvm_rcp_rm_d:
374 case Intrinsic::nvvm_rcp_rm_f:
375 case Intrinsic::nvvm_rcp_rn_d:
376 case Intrinsic::nvvm_rcp_rn_f:
377 case Intrinsic::nvvm_rcp_rp_d:
378 case Intrinsic::nvvm_rcp_rp_f:
379 case Intrinsic::nvvm_rcp_rz_d:
380 case Intrinsic::nvvm_rcp_rz_f:
381 return false;
382 }
383 llvm_unreachable("Checking FTZ flag for invalid rcp intrinsic");
384}
385
386inline APFloat::roundingMode GetRCPRoundingMode(Intrinsic::ID IntrinsicID) {
387 switch (IntrinsicID) {
388 case Intrinsic::nvvm_rcp_rm_f:
389 case Intrinsic::nvvm_rcp_rm_d:
390 case Intrinsic::nvvm_rcp_rm_ftz_f:
391 return APFloat::rmTowardNegative;
392
393 case Intrinsic::nvvm_rcp_rn_f:
394 case Intrinsic::nvvm_rcp_rn_d:
395 case Intrinsic::nvvm_rcp_rn_ftz_f:
396 return APFloat::rmNearestTiesToEven;
397
398 case Intrinsic::nvvm_rcp_rp_f:
399 case Intrinsic::nvvm_rcp_rp_d:
400 case Intrinsic::nvvm_rcp_rp_ftz_f:
401 return APFloat::rmTowardPositive;
402
403 case Intrinsic::nvvm_rcp_rz_f:
404 case Intrinsic::nvvm_rcp_rz_d:
405 case Intrinsic::nvvm_rcp_rz_ftz_f:
406 return APFloat::rmTowardZero;
407 }
408 llvm_unreachable("Checking rounding mode for invalid rcp intrinsic");
409}
410
411inline DenormalMode GetNVVMDenormMode(bool ShouldFTZ) {
412 if (ShouldFTZ)
413 return DenormalMode::getPreserveSign();
414 return DenormalMode::getIEEE();
415}
416
417inline bool FAddShouldFTZ(Intrinsic::ID IntrinsicID) {
418 switch (IntrinsicID) {
419 case Intrinsic::nvvm_add_rm_ftz_f:
420 case Intrinsic::nvvm_add_rn_ftz_f:
421 case Intrinsic::nvvm_add_rp_ftz_f:
422 case Intrinsic::nvvm_add_rz_ftz_f:
423 return true;
424
425 case Intrinsic::nvvm_add_rm_f:
426 case Intrinsic::nvvm_add_rn_f:
427 case Intrinsic::nvvm_add_rp_f:
428 case Intrinsic::nvvm_add_rz_f:
429 case Intrinsic::nvvm_add_rm_d:
430 case Intrinsic::nvvm_add_rn_d:
431 case Intrinsic::nvvm_add_rp_d:
432 case Intrinsic::nvvm_add_rz_d:
433 return false;
434 }
435 llvm_unreachable("Checking FTZ flag for invalid NVVM add intrinsic");
436}
437
438inline APFloat::roundingMode GetFAddRoundingMode(Intrinsic::ID IntrinsicID) {
439 switch (IntrinsicID) {
440 case Intrinsic::nvvm_add_rm_f:
441 case Intrinsic::nvvm_add_rm_d:
442 case Intrinsic::nvvm_add_rm_ftz_f:
443 return APFloat::rmTowardNegative;
444 case Intrinsic::nvvm_add_rn_f:
445 case Intrinsic::nvvm_add_rn_d:
446 case Intrinsic::nvvm_add_rn_ftz_f:
447 return APFloat::rmNearestTiesToEven;
448 case Intrinsic::nvvm_add_rp_f:
449 case Intrinsic::nvvm_add_rp_d:
450 case Intrinsic::nvvm_add_rp_ftz_f:
451 return APFloat::rmTowardPositive;
452 case Intrinsic::nvvm_add_rz_f:
453 case Intrinsic::nvvm_add_rz_d:
454 case Intrinsic::nvvm_add_rz_ftz_f:
455 return APFloat::rmTowardZero;
456 }
457 llvm_unreachable("Invalid FP instrinsic rounding mode for NVVM add");
458}
459
460inline bool FMulShouldFTZ(Intrinsic::ID IntrinsicID) {
461 switch (IntrinsicID) {
462 case Intrinsic::nvvm_mul_rm_ftz_f:
463 case Intrinsic::nvvm_mul_rn_ftz_f:
464 case Intrinsic::nvvm_mul_rp_ftz_f:
465 case Intrinsic::nvvm_mul_rz_ftz_f:
466 return true;
467
468 case Intrinsic::nvvm_mul_rm_f:
469 case Intrinsic::nvvm_mul_rn_f:
470 case Intrinsic::nvvm_mul_rp_f:
471 case Intrinsic::nvvm_mul_rz_f:
472 case Intrinsic::nvvm_mul_rm_d:
473 case Intrinsic::nvvm_mul_rn_d:
474 case Intrinsic::nvvm_mul_rp_d:
475 case Intrinsic::nvvm_mul_rz_d:
476 return false;
477 }
478 llvm_unreachable("Checking FTZ flag for invalid NVVM mul intrinsic");
479}
480
481inline APFloat::roundingMode GetFMulRoundingMode(Intrinsic::ID IntrinsicID) {
482 switch (IntrinsicID) {
483 case Intrinsic::nvvm_mul_rm_f:
484 case Intrinsic::nvvm_mul_rm_d:
485 case Intrinsic::nvvm_mul_rm_ftz_f:
486 return APFloat::rmTowardNegative;
487 case Intrinsic::nvvm_mul_rn_f:
488 case Intrinsic::nvvm_mul_rn_d:
489 case Intrinsic::nvvm_mul_rn_ftz_f:
490 return APFloat::rmNearestTiesToEven;
491 case Intrinsic::nvvm_mul_rp_f:
492 case Intrinsic::nvvm_mul_rp_d:
493 case Intrinsic::nvvm_mul_rp_ftz_f:
494 return APFloat::rmTowardPositive;
495 case Intrinsic::nvvm_mul_rz_f:
496 case Intrinsic::nvvm_mul_rz_d:
497 case Intrinsic::nvvm_mul_rz_ftz_f:
498 return APFloat::rmTowardZero;
499 }
500 llvm_unreachable("Invalid FP instrinsic rounding mode for NVVM mul");
501}
502
503inline bool FDivShouldFTZ(Intrinsic::ID IntrinsicID) {
504 switch (IntrinsicID) {
505 case Intrinsic::nvvm_div_rm_ftz_f:
506 case Intrinsic::nvvm_div_rn_ftz_f:
507 case Intrinsic::nvvm_div_rp_ftz_f:
508 case Intrinsic::nvvm_div_rz_ftz_f:
509 return true;
510
511 case Intrinsic::nvvm_div_rm_f:
512 case Intrinsic::nvvm_div_rn_f:
513 case Intrinsic::nvvm_div_rp_f:
514 case Intrinsic::nvvm_div_rz_f:
515 case Intrinsic::nvvm_div_rm_d:
516 case Intrinsic::nvvm_div_rn_d:
517 case Intrinsic::nvvm_div_rp_d:
518 case Intrinsic::nvvm_div_rz_d:
519 return false;
520 }
521 llvm_unreachable("Checking FTZ flag for invalid NVVM div intrinsic");
522}
523
524inline APFloat::roundingMode GetFDivRoundingMode(Intrinsic::ID IntrinsicID) {
525 switch (IntrinsicID) {
526 case Intrinsic::nvvm_div_rm_f:
527 case Intrinsic::nvvm_div_rm_d:
528 case Intrinsic::nvvm_div_rm_ftz_f:
529 return APFloat::rmTowardNegative;
530 case Intrinsic::nvvm_div_rn_f:
531 case Intrinsic::nvvm_div_rn_d:
532 case Intrinsic::nvvm_div_rn_ftz_f:
533 return APFloat::rmNearestTiesToEven;
534 case Intrinsic::nvvm_div_rp_f:
535 case Intrinsic::nvvm_div_rp_d:
536 case Intrinsic::nvvm_div_rp_ftz_f:
537 return APFloat::rmTowardPositive;
538 case Intrinsic::nvvm_div_rz_f:
539 case Intrinsic::nvvm_div_rz_d:
540 case Intrinsic::nvvm_div_rz_ftz_f:
541 return APFloat::rmTowardZero;
542 }
543 llvm_unreachable("Invalid FP instrinsic rounding mode for NVVM div");
544}
545
546inline bool FMAShouldFTZ(Intrinsic::ID IntrinsicID) {
547 switch (IntrinsicID) {
548 case Intrinsic::nvvm_fma_rm_ftz_f:
549 case Intrinsic::nvvm_fma_rn_ftz_f:
550 case Intrinsic::nvvm_fma_rp_ftz_f:
551 case Intrinsic::nvvm_fma_rz_ftz_f:
552 return true;
553
554 case Intrinsic::nvvm_fma_rm_f:
555 case Intrinsic::nvvm_fma_rn_f:
556 case Intrinsic::nvvm_fma_rp_f:
557 case Intrinsic::nvvm_fma_rz_f:
558 case Intrinsic::nvvm_fma_rm_d:
559 case Intrinsic::nvvm_fma_rn_d:
560 case Intrinsic::nvvm_fma_rp_d:
561 case Intrinsic::nvvm_fma_rz_d:
562 return false;
563 }
564 llvm_unreachable("Checking FTZ flag for invalid NVVM fma intrinsic");
565}
566
567inline APFloat::roundingMode GetFMARoundingMode(Intrinsic::ID IntrinsicID) {
568 switch (IntrinsicID) {
569 case Intrinsic::nvvm_fma_rm_f:
570 case Intrinsic::nvvm_fma_rm_d:
571 case Intrinsic::nvvm_fma_rm_ftz_f:
572 return APFloat::rmTowardNegative;
573 case Intrinsic::nvvm_fma_rn_f:
574 case Intrinsic::nvvm_fma_rn_d:
575 case Intrinsic::nvvm_fma_rn_ftz_f:
576 return APFloat::rmNearestTiesToEven;
577 case Intrinsic::nvvm_fma_rp_f:
578 case Intrinsic::nvvm_fma_rp_d:
579 case Intrinsic::nvvm_fma_rp_ftz_f:
580 return APFloat::rmTowardPositive;
581 case Intrinsic::nvvm_fma_rz_f:
582 case Intrinsic::nvvm_fma_rz_d:
583 case Intrinsic::nvvm_fma_rz_ftz_f:
584 return APFloat::rmTowardZero;
585 }
586 llvm_unreachable("Invalid FP instrinsic rounding mode for NVVM fma");
587}
588
589} // namespace nvvm
590} // namespace llvm
591#endif // LLVM_IR_NVVMINTRINSICUTILS_H
APFloat.h
This file declares a class to represent arbitrary precision floating point values and provide a varie...
uint8_t
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:164
llvm::nvvm::GetFMARoundingMode
APFloat::roundingMode GetFMARoundingMode(Intrinsic::ID IntrinsicID)
Definition: NVVMIntrinsicUtils.h:567
llvm::nvvm::GetNVVMDenormMode
DenormalMode GetNVVMDenormMode(bool ShouldFTZ)
Definition: NVVMIntrinsicUtils.h:411
llvm::nvvm::GetFDivRoundingMode
APFloat::roundingMode GetFDivRoundingMode(Intrinsic::ID IntrinsicID)
Definition: NVVMIntrinsicUtils.h:524
llvm::nvvm::FPToIntegerIntrinsicResultIsSigned
bool FPToIntegerIntrinsicResultIsSigned(Intrinsic::ID IntrinsicID)
Definition: NVVMIntrinsicUtils.h:117
llvm::nvvm::GetFPToIntegerRoundingMode
APFloat::roundingMode GetFPToIntegerRoundingMode(Intrinsic::ID IntrinsicID)
Definition: NVVMIntrinsicUtils.h:184
llvm::nvvm::RCPShouldFTZ
bool RCPShouldFTZ(Intrinsic::ID IntrinsicID)
Definition: NVVMIntrinsicUtils.h:366
llvm::nvvm::FPToIntegerIntrinsicShouldFTZ
bool FPToIntegerIntrinsicShouldFTZ(Intrinsic::ID IntrinsicID)
Definition: NVVMIntrinsicUtils.h:50
llvm::nvvm::FDivShouldFTZ
bool FDivShouldFTZ(Intrinsic::ID IntrinsicID)
Definition: NVVMIntrinsicUtils.h:503
llvm::nvvm::FAddShouldFTZ
bool FAddShouldFTZ(Intrinsic::ID IntrinsicID)
Definition: NVVMIntrinsicUtils.h:417
llvm::nvvm::FMinFMaxIsXorSignAbs
bool FMinFMaxIsXorSignAbs(Intrinsic::ID IntrinsicID)
Definition: NVVMIntrinsicUtils.h:311
llvm::nvvm::GetFMulRoundingMode
APFloat::roundingMode GetFMulRoundingMode(Intrinsic::ID IntrinsicID)
Definition: NVVMIntrinsicUtils.h:481
llvm::nvvm::UnaryMathIntrinsicShouldFTZ
bool UnaryMathIntrinsicShouldFTZ(Intrinsic::ID IntrinsicID)
Definition: NVVMIntrinsicUtils.h:340
llvm::nvvm::FMinFMaxShouldFTZ
bool FMinFMaxShouldFTZ(Intrinsic::ID IntrinsicID)
Definition: NVVMIntrinsicUtils.h:253
llvm::nvvm::GetFAddRoundingMode
APFloat::roundingMode GetFAddRoundingMode(Intrinsic::ID IntrinsicID)
Definition: NVVMIntrinsicUtils.h:438
llvm::nvvm::FMAShouldFTZ
bool FMAShouldFTZ(Intrinsic::ID IntrinsicID)
Definition: NVVMIntrinsicUtils.h:546
llvm::nvvm::FMulShouldFTZ
bool FMulShouldFTZ(Intrinsic::ID IntrinsicID)
Definition: NVVMIntrinsicUtils.h:460
llvm::nvvm::GetRCPRoundingMode
APFloat::roundingMode GetRCPRoundingMode(Intrinsic::ID IntrinsicID)
Definition: NVVMIntrinsicUtils.h:386
llvm::nvvm::FMinFMaxPropagatesNaNs
bool FMinFMaxPropagatesNaNs(Intrinsic::ID IntrinsicID)
Definition: NVVMIntrinsicUtils.h:282
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::RoundingMode
RoundingMode
Rounding mode.
Definition: FloatingPointMode.h:38
llvm::APFloatBase::rmTowardNegative
static constexpr roundingMode rmTowardNegative
Definition: APFloat.h:307
llvm::APFloatBase::rmNearestTiesToEven
static constexpr roundingMode rmNearestTiesToEven
Definition: APFloat.h:304
llvm::APFloatBase::rmTowardZero
static constexpr roundingMode rmTowardZero
Definition: APFloat.h:308
llvm::APFloatBase::rmTowardPositive
static constexpr roundingMode rmTowardPositive
Definition: APFloat.h:306
llvm::DenormalMode
Represent subnormal handling kind for floating point instruction inputs and outputs.
Definition: FloatingPointMode.h:71
llvm::DenormalMode::getPreserveSign
static constexpr DenormalMode getPreserveSign()
Definition: FloatingPointMode.h:119
llvm::DenormalMode::getIEEE
static constexpr DenormalMode getIEEE()
Definition: FloatingPointMode.h:115
Generated on Sat Aug 30 2025 05:09:42 for LLVM by doxygen 1.9.6